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32K x 16 Static RAM

CY7C1020

 

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

October 18, 1999

7C10

Features

• 5.0V operation (± 10%)

• High speed

— t

AA

 = 10 ns 

• Low active power

— 825 mW (max., 10 ns, “L” version)

• Very Low standby power

— 550 

µ

W (max., “L” version)

• Automatic power-down when deselected

• Independent Control of Upper and Lower bytes

• Available in 44-pin TSOP II and 400-mil SOJ

Functional Description

The CY7C1020 is a high-performance CMOS static RAM or-

ganized as 32,768 words by 16 bits. This device has an auto-

matic power-down feature that significantly reduces power

consumption when deselected. 

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O

1

 through I/O

8

), is

written into the location specified on the address pins (A

0

through A

14

). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O

9

 through I/O

16

) is written into the location

specified on the address pins (A

0

 through A

14

).

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

will appear on I/O

1

 to I/O

8

. If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O

9

 to I/O

16

. See the

truth table at the back of this data sheet for a complete descrip-

tion of read and write modes.

The input/output pins (I/O

1

 through I/O

16

) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

The CY7C1020 is available in standard 44-pin TSOP type II

and 400-mil-wide SOJ packages.

WE

Logic Block Diagram

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

14

31

32

36

35

34

33

37

40

39

38

Top View

SOJ / TSOP II

12

13

41

44

43

42

16

15

29

30

V

CC

A

10

A

9

A

8

A

7

NC

NC

A

14

OE

V

SS

A

0

I/O

16

A

13

CE

I/O

3

I/O

1

I/O

2

BHE

NC

A

12

A

11

1020-2

18

17

20

19

I/O

4

27

28

25

26

22

21

23

24

NC

V

SS

I/O

7

I/O

5

I/O

6

I/O

8

A

1

A

2

BLE

V

CC

I/O

15

I/O

14

I/O

13

I/O

12

I/O

11

I/O

10

I/O

9

A

3

A

4

A

5

A

6

32K x 16

RAM Array

I/O

1

 – I/O

8

ROW

 DE

CODE

A

6

A

5

A

4

A

3

A

0

COLUMN DECODER

A

9

A

10

A

11

A

12

A

13

A

14

SEN

SE

 AM

PS

DATA IN DRIVERS

OE

A

2

A

1

I/O

9

 – I/O

16

CE

WE

BLE

BHE

A

8

A

7

1020-1

Selection Guide

7C1020-10

7C1020-12

7C1020-15

7C1020-20

Maximum Access Time (ns)

10

12

15

20

Maximum Operating Current (mA)

180

170

160

160

L

150

140

130

130

Maximum CMOS Standby Current (mA)

3

3

3

3

L

0.1

0.1

0.1

0.1

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CY7C1020

2

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature  ................................. –65

°

C to +150

°

C

Ambient Temperature with

Power Applied ............................................. –55

°

C to +125

°

C

Supply Voltage on V

CC

 to Relative GND

[1]

.... –0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State

[1]

.....................................–0.5V to V

CC

 +0.5V

DC Input Voltage

[1]

..................................–0.5V to V

CC

 +0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage ........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current ..................................................... >200 mA

Operating Range

Range

Ambient

Temperature

[2]

V

CC

Commercial

0

°

C to +70

°

4.5V–5.5V

Electrical Characteristics 

Over the Operating Range

Parameter

Description

Test Conditions

7C1020-10

7C1020-12

7C1020-15

Unit

Min.

Max.

Min.

Max.

Min.

Max.

V

OH

Output HIGH Voltage

V

CC

 = Min., I

OH

 = –4.0 mA

2.4

2.4

2.4

V

V

OL

Output LOW Voltage

V

CC

 = Min., I

OL

 = 8.0 mA

0.4

0.4

0.4

V

V

IH

Input HIGH Voltage

2.2

6.0

2.2

6.0

2.2

6.0

V

V

IL

Input LOW Voltage

[1]

–0.5

0.8

–0.5

0.8

–0.5

0.8

V

I

IX

Input Load Current

GND < V

I

 < V

CC

–1

+1

–1

+1

–1

+1

µ

A

I

OZ

Output Leakage

Current

GND < V

< V

CC

,

Output Disabled

–2

+2

–2

+2

–2

+2

µ

A

I

CC

V

CC

 Operating 

Supply Current

V

CC

 = Max.,

 

I

OUT

 = 0 mA,

f = f

MAX

 = 1/t

RC

180

170

160

mA

L

150

140

130

I

SB1

Automatic CE 

Power-Down Current

— TTL Inputs

Max. V

CC

, CE > V

IH

V

IN

 > V

IH

 or 

V

IN

 < V

IL

, f = f

MAX

20

20

20

mA

L

10

10

10

I

SB2

Automatic CE 

Power-Down Current

— CMOS Inputs

Max. V

CC

CE > V

CC

 – 0.3V,

V

IN

 > V

CC

 – 0.3V,

or V

IN

 < 0.3V, f = 0

3

3

3

mA

L

100

100

100

µ

A

Notes:

1.

V

IL

 (min.) = –2.0V for pulse durations of less than 20 ns.

2.

T

A

 is the case temperature.

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CY7C1020

3

Electrical Characteristics 

Over the Operating Range (continued)

Parameter

Description

Test Conditions

7C1020-20

Unit

Min.

Max.

V

OH

Output HIGH Voltage

V

CC

 = Min., I

OH

 = –4.0 mA

2.4

V

V

OL

Output LOW Voltage

V

CC

 = Min., I

OL

 = 8.0 mA

0.4

V

V

IH

Input HIGH Voltage

2.2

6.0

V

V

IL

Input LOW Voltage

[1]

–0.5

0.8

V

I

IX

Input Load Current

GND < V

I

 < V

CC

–1

+1

µ

A

I

OZ

Output Leakage Current

GND < V

< V

CC

, Output Disabled

–2

+2

µ

A

I

CC

V

CC

 Operating 

Supply Current

V

CC

 = Max.,

 

I

OUT

 = 0 mA,

f = f

MAX

 = 1/t

RC

160

mA

L

130

I

SB1

Automatic CE 

Power-Down Current

— TTL Inputs

Max. V

CC

, CE > V

IH

V

IN

 > V

IH

 or 

V

IN

 < V

IL

, f = f

MAX

20

mA

L

10

I

SB2

Automatic CE 

Power-Down Current

— CMOS Inputs

Max. V

CC

CE > V

CC

 – 0.3V,

V

IN

 > V

CC

 – 0.3V,

or V

IN

 < 0.3V, f = 0

3

mA

L

100

µ

A

Capacitance

[3]

Parameter

Description

Test Conditions

Max.

Unit

C

IN

Input Capacitance

T

A

 = 25

°

C, f = 1 MHz,

V

CC

 = 5.0V

8

pF

C

OUT

Output Capacitance

8

pF

Note:

3.

Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

1020-3

1020-4

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

5V

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

5V

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

<3 ns

<3 ns

OUTPUT

R 481

R 481

R2

255

R2

255

167

Equivalent  to:

THÉVENIN

EQUIVALENT

1.73V

30 pF

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CY7C1020

4

Switching Characteristics

[4]

 Over the Operating Range

Parameter

Description

7C1020-10

7C1020-12

7C1020-15

7C1020-20

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

READ CYCLE

t

RC

Read Cycle Time

10

12

15

20

ns

t

AA

Address to Data Valid

10

12

15

20

ns

t

OHA

Data Hold from Address Change

3

3

3

3

ns

t

ACE

CE LOW to Data Valid

10

12

15

20

ns

t

DOE

OE LOW to Data Valid

5

5

7

9

ns

t

LZOE

OE LOW to Low Z

0

0

0

0

ns

t

HZOE

OE HIGH to High Z

[5, 6]

5

6

7

8

ns

t

LZCE

CE LOW to Low Z

[6]

3

3

3

3

ns

t

HZCE

CE HIGH to High Z

[5, 6]

5

6

7

8

ns

t

PU

CE LOW to Power-Up

0

0

0

0

ns

t

PD

CE HIGH to Power-Down

12

12

15

20

ns

t

DBE

Byte enable to Data Valid

5

6

7

9

ns

t

LZBE

Byte enable to Low Z

0

0

0

0

ns

t

HZBE

Byte disable to High Z

5

6

7

9

ns

WRITE CYCLE

[7]

t

WC

Write Cycle Time

10

12

15

12

ns

t

SCE

CE LOW to Write End

8

9

10

12

ns

t

AW

Address Set-Up to Write End

7

8

10

12

ns

t

HA

Address Hold from Write End

0

0

0

0

ns

t

SA

Address Set-Up to Write Start

0

0

0

0

ns

t

PWE

WE Pulse Width

7

8

10

12

ns

t

SD

Data Set-Up to Write End

5

6

10

10

ns

t

HD

Data Hold from Write End

0

0

0

0

ns

t

LZWE

WE HIGH to Low Z

[6]

3

3

3

3

ns

t

HZWE

WE LOW to High Z

[5, 6]

5

6

7

9

ns

t

BW

Byte enable to end of write

7

8

9

12

ns

Notes:

4.

Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified 

I

OL

/I

OH

 and 30-pF load capacitance.

5.

t

HZOE

, t

HZBE

, t

HZCE

, and t

HZWE

 are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 

±

500 mV from steady-state voltage.

6.

At any given temperature and voltage condition, t

HZCE

 is less than t

LZCE

, t

HZOE

 is less than t

LZOE

, and t

HZWE

 is less than t

LZWE

 for any given device.

7.

The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, 

and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

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CY7C1020

5

Switching Waveforms 

Notes:

8.

Device is continuously selected. OE, CE, BHE and/or BHE = V

IL

.

9.

WE is HIGH for read cycle.

10. Address valid prior to or coincident with CE transition LOW.

Read Cycle No. 1

PREVIOUS DATA VALID

DATA VALID

t

RC

t

AA

t

OHA

1020-5

ADDRESS

DATA OUT

[8, 9]

Read Cycle No. 2 (OE Controlled)

1020-6

50%

50%

DATA VALID

t

RC

t

ACE

t

DOE

t

LZOE

t

LZCE

t

PU

HIGH IMPEDANCE

t

HZOE

t

HZBE

t

PD

HIGH 

OE

CE

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

V

CC

SUPPLY

t

DBE

t

LZBE

t

HZCE

BHE, BLE

[9, 10]

CURRENT

I

CC

I

SB

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CY7C1020

6

Notes:

11. Data I/O is high impedance if OE or BHE and/or BLE= V

IH

.

12. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

Switching Waveforms 

 (continued)

Write Cycle No. 1 (CE Controlled)

1020-7

t

HD

t

SD

t

SCE

t

SA

t

HA

t

AW

t

PWE

t

WC

BW

DATAI/O

ADDRESS

CE

WE

BHE, BLE

[11, 12]

t

Write Cycle No.  2 (BLE or BHE Controlled)

t

HD

t

SD

t

BW

t

SA

t

HA

t

AW

t

PWE

t

WC

t

SCE

DATAI/O

ADDRESS

BHE, BLE

WE

CE

1020-8

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CY7C1020

7

Switching Waveforms 

 (continued)

Write Cycle No. 3 (WE ControlledOE LOW)

1020-10

t

HD

t

SD

t

SCE

t

HA

t

AW

t

PWE

t

WC

t

BW

DATA I/O

ADDRESS

CE

WE

BHE, BLE

t

SA

t

LZWE

t

HZWE

Truth Table

CE

OE

WE

BLE

BHE

I/O

1

–I/O

8

I/O

9

–I/O

16

Mode

Power

H

X

X

X

X

High Z

High Z

Power-Down

Standby (I

SB

)

L

L

H

L

L

Data Out

Data Out

Read - All bits

Active (I

CC

)

L

H

Data Out

High Z

Read - Lower bits only

Active (I

CC

)

H

L

High Z

Data Out

Read - Upper bits only

Active (I

CC

)

L

X

L

L

L

Data In

Data In

Write - All bits

Active (I

CC

)

L

H

Data In

High Z

Write - Lower bits only

Active (I

CC

)

H

L

High Z

Data In

Write - Upper bits only

Active (I

CC

)

L

H

H

X

X

High Z

High Z

Selected, Outputs Disabled 

Active (I

CC

)

L

X

X

H

H

High Z

High Z

Selected, Outputs Disabled

Active (I

CC

)

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CY7C1020

8

Ordering Information

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

10

CY7C1020-10VC

V34

44-Lead (400-Mil) Molded SOJ

Commercial

CY7C1020L-10VC

V34

44-Lead (400-Mil) Molded SOJ

Commercial

CY7C1020-10ZC

Z44

44-Lead TSOP Type II

Commercial

CY7C1020L-10ZC

Z44

44-Lead TSOP Type II

Commercial

12

CY7C1020-12VC

V34

44-Lead (400-Mil) Molded SOJ

Commercial

CY7C1020L-12VC

V34

44-Lead (400-Mil) Molded SOJ

Commercial

CY7C1020-12ZC

Z44

44-Lead TSOP Type II

Commercial

CY7C1020L-12ZC

Z44

44-Lead TSOP Type II

Commercial

15

CY7C1020-15VC

V34

44-Lead (400-Mil) Molded SOJ

Commercial

CY7C1020L-15VC

V34

44-Lead (400-Mil) Molded SOJ

Commercial

CY7C1020-15ZC

Z44

44-Lead TSOP Type II

Commercial

CY7C1020L-15ZC

Z44

44-Lead TSOP Type II

Commercial

20

CY7C1020-20VC

V34

44-Lead (400-Mil) Molded SOJ

Commercial

CY7C1020L-20VC

V34

44-Lead (400-Mil) Molded SOJ

Commercial

CY7C1020-20ZC

Z44

44-Lead TSOP Type II

Commercial

CY7C1020L-20ZC

Z44

44-Lead TSOP Type II

Commercial

Document #: 38-00542-C

Package Diagrams 

44-Lead (400-Mil) Molded SOJ V34

51-85082-B

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CY7C1020

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams 

 (continued)

44-Pin TSOP II Z44

51-85087-A