background image

© 1999 Fairchild Semiconductor Corporation

DS010932

www.fairchildsemi.com

March 1993

Revised November 1999

7

4

AC

TQ541

 Quie

Seri

es Oct

a

Buff

er/

L

in

e Dri

ver

 wit

h

 3-ST

A

T

E Outp

uts

74ACTQ541

Quiet Series Octal Buffer/Line Driver

with 3-STATE Outputs

General Description

The 74ACTQ541 is an octal buffer/line driver designed to

be employed as memory and address drivers, clock drivers

and bus oriented transmitter/receivers.

This device is similar in function to the 74ACTQ244 while

providing flow-through architecture (inputs on opposite side

from outputs). This pinout arrangement makes this device

especially useful as an output port for microprocessors,

allowing ease of layout and greater PC board density.

The 74ACTQ541 utilizes FACT Quiet Series

 technology

to guarantee quiet output switching and improved dynamic

threshold performance. FACT Quiet Series features GTO

output control and undershoot corrector in addition to split

ground bus for superior performance.

Features

s

I

CC

 and I

OZ

 reduced by 50%

s

Guaranteed simultaneous switching noise level and

dynamic threshold performance

s

Guaranteed pin-to-pin skew AC performance

s

Inputs and outputs on opposite sides of package for

easy board layout

s

Non-inverting 3-STATE outputs

s

Guaranteed 4 kV minimum ESD immunity

s

TTL compatible inputs

s

Outputs source/sink 24 mA

 

Ordering Code: 

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.

Logic Symbol

IEEE/IEC

Pin Descriptions

Connection Diagram

Truth Table

=

 HIGH Voltage Level

=

 Immaterial

=

 LOW Voltage Level

=

 High Impedance

FACT

, FACT Quiet Series

 and GTO

 are trademarks of Fairchild Semiconductor Corporation.

Order Number

Package Number

Package Description

74ACTQ541SC

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74ACTQ541MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACTQ541PC

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Name

Pin Description

OE

1

 – OE

2

3-STATE Output Enable (Active-LOW)

I

0

 –I

7

Inputs

O

1

 – O

7

Outputs

Inputs

Outputs

OE

1

OE

2

I

L

L

H

H

H

X

X

Z

X

H

X

Z

L

L

L

L

background image

www.fairchildsemi.com

2

7

4

AC

T

Q

541

Absolute Maximum Ratings

(Note 1)

Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with-

out exception, to ensure that the system design is reliable over its power

supply, temperature, and output/input loading variables. Fairchild does not

recommend operation of FACT

 circuits outside databook specifications.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: Plastic DIP package.

Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.

Note 6: Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V

ILD

),

0V to threshold (V

IHD

), f

=

 1 MHz.

Supply Voltage (V

CC

)

0.5V to 

+

7.0V

DC Input Diode Current (I

IK

)

V

I

 

=

 

0.5V

20 mA

V

I

 

=

 V

CC

 

+

 0.5V

+

20 mA

DC Input Voltage (V

I

)

0.5V to V

CC

 

+

 0.5V

DC Output Diode Current (I

OK

)

V

O

 

=

 

0.5V

20 mA

V

O

 

=

 V

CC

 

+

 0.5V

+

20 mA

DC Output Voltage (V

O

)

0.5V to V

CC

 

+

 0.5V

DC Output Source or Sink Current (I

O

)

±

50 mA

DC V

CC

 or Ground Current

per Output Pin (I

CC

 or I

GND

)

±

50 mA

Storage Temperature (T

STG

)

65

°

C to 

+

150

°

C

DC Latch-up Source or Sink Current

±

 300 mA

Junction Temperature (T

J

)

140

°

C

Supply Voltage V

CC

4.5V to 5.5V

Input Voltage (V

I

)

0V to V

CC

Output Voltage (V

O

)

0V to V

CC

Operating Temperature (T

A

40

°

C to 

+

85

°

C

Minimum Input Edge Rate 

V/

t

V

IN

 from 0.8V to 2.0V

V

CC

 @ 4.5V, 5.5V

125 mV/ns

Symbol

Parameter

V

CC

T

A

 

=

 

+

25

°

C

T

A

 

=

 

40

°

C to 

+

85

°

C

Units

Conditions

(V)

Typ

Guaranteed Limits

V

IH

Minimum HIGH Level

4.5

1.5

2.0

2.0

V

V

OUT

 

=

 0.1V

Input Voltage

5.5

1.5

2.0

2.0

or V

CC

 

 0.1V

V

IL

Maximum LOW Level

4.5

1.5

0.8

0.8

V

V

OUT

 

=

 0.1V

Input Voltage

5.5

1.5

0.8

0.8

or V

CC

 

 0.1V

V

OH

Minimum HIGH Level

3.0

2.99

2.9

2.9

V

I

OUT

 

=

 

50 

µ

A

Output Voltage

4.5

4.49

4.4

4.4

4.5

3.86

3.76

V

V

IN

 

=

 V

IL

 or V

IH

 (Note 2)

I

OH

 = 

24 mA

 

24 mA

5.5

4.86

4.76

V

OL

Maximum LOW Level

3.0

0.002

0.1

0.1

V

I

OUT

 

=

 50 

µ

A

Output Voltage

4.5

0.001

0.1

0.1

4.5

0.36

0.44

V

V

IN

 

=

 V

IL

 or V

IH

 (Note 2)

I

OH

 = 24 mA

24 mA

5.5

0.36

0.44

I

IN

Maximum Input Leakage Current

5.5

±

 0.1

±

 1.0

µ

A

V

I

 

=

 V

CC

, GND

I

OZ

Maximum 3-STATE

5.5

±

0.25

±

2.5

µ

A

V

=

 V

IL

, V

IH

Leakage Current

V

O

 

=

 V

CC

, GND

I

CCT

Maximum I

CC

/Input

5.5

0.6

1.5

mA

V

I

 

=

 V

CC

 

 2.1V

I

OLD

Minimum Dynamic 

5.5

75

mA

V

OLD

 

=

 1.65V Max

I

OHD

Output Current (Note 3)

5.5

75

mA

V

OHD

 

=

 3.85V Min

I

CC

Maximum Quiescent 

Supply Current

5.5

4.0

40.0

µ

A

V

IN

 

=

 V

CC

 or GND 

V

OLP

Quiet Output

5.0

1.1

1.5

V

Figure 1, Figure 2

Maximum Dynamic V

OL

(Note 4)(Note 5)

V

OLV

Quiet Output

5.0

0.6

1.2

V

Figure 1, Figure 2

Minimum Dynamic V

OL

(Note 4)(Note 5)

V

IHD

Minimum HIGH Level

5.0

1.9

2.2

V

(Note 4)(Note 6)

Dynamic Input Voltage

V

ILD

Maximum LOW Level

5.0

1.2

0.8

V

(Note 4)(Note 6)

Dynamic Input Voltage

background image

3

www.fairchildsemi.com

7

4

AC

TQ541

AC Electrical Characteristics

Note 7: Voltage Range 5.0 is 5.0V 

±

 0.5V

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guaranteed by design.

Capacitance

Symbol

Parameter

V

CC

T

A

 

=

 

+

25

°

C

T

A

 

=

 

40

°

C to 

+

85

°

C

Units

(V)

C

L

 

=

 50 pF

C

L

 

=

 50 pF

(Note 7)

Min

Typ

Max

Min

Max

t

PLH

Propagation Delay

5.0

2.0

4.5

7.0

2.0

7.5

ns

t

PHL

Data to Output

2.0

5.5

7.0

2.0

7.5

t

PZH

Output Enable Time

5.0

2.0

5.0

9.0

2.0

9.5

ns

t

PZL

2.0

6.5

9.0

2.0

9.5

t

PHZ

Output Disable Time

5.0

1.5

5.5

7.5

1.5

8.0

ns

t

PLZ

1.5

5.5

7.5

1.5

8.0

t

OSHL

Output to Output

0.5

1.0

1.0

ns

t

OSLH

Skew Data to Output (Note 8)

0.5

1.0

1.0

Symbol

Parameter

Typ

Units

Conditions

C

IN

Input Capacitance

4.5

pF

V

CC

 

=

 OPEN

C

PD

Power Dissipation Capacitance

70

pF

V

CC

 

=

 5.0V

background image

www.fairchildsemi.com

4

7

4

AC

T

Q

541

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical

to the accuracy and repeatability of the tests. The following

is a brief description of the setup used to measure the

noise characteristics of FACT.

Equipment:

Hewlett Packard Model 8180A Word Generator

PC-163A Test Fixture

Tektronics Model 7854 Oscilloscope

Procedure:

1. Verify Test Fixture Loading: Standard Load 50 pF,

500

.

2. Deskew the HFS generator so that no two channels

have greater than 150 ps skew between them. This

requires that the oscilloscope be deskewed first. It is

important to deskew the HFS generator channels

before testing. This will ensure that the outputs switch

simultaneously.

3. Terminate all inputs and outputs to ensure proper load-

ing of the outputs and that the input levels are at the

correct voltage.

4. Set the HFS generator to toggle all but one output at a

frequency of 1 MHz. Greater frequencies will increase

DUT heating and effect the results of the measure-

ment.

5. Set the HFS generator input levels at 0V LOW and 3V

HIGH for ACT devices and 0V LOW and 5V HIGH for

AC devices. Verify levels with an oscilloscope.

V

OHV

and V

OLP

 are measured with respect to ground reference.

Input pulses have the following characteristics: f 

=

 1 MHz, t

r

=

3 ns,  t

f

 

=

  3

ns, skew 

<

 150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

V

OLP

/V

OLV

 and V

OHP

/V

OHV

:

• Determine the quiet output pin that demonstrates the

greatest noise levels. The worst case pin will usually be

the furthest from the ground pin. Monitor the output volt-

ages using a 50

 coaxial cable plugged into a standard

SMB type connector on the test fixture. Do not use an

active FET probe.

• Measure V

OLP

 and V

OLV

 on the quiet output during the

worst case transition for active and enable. Measure

V

OHP

 and V

OHV

 on the quiet output during the worst

case active and enable transition.

• Verify that the GND reference recorded on the oscillo-

scope has not drifted to ensure the accuracy and repeat-

ability of the measurements.

V

ILD

 and V

IHD

:

• Monitor one of the switching outputs using a 50

 coaxial

cable plugged into a standard SMB type connector on

the test fixture. Do not use an active FET probe.

• First increase the input LOW voltage level, V

IL

, until the

output begins to oscillate or steps out a min of 2 ns.

Oscillation is defined as noise on the output LOW level

that exceeds V

IL

 limits, or on output HIGH levels that

exceed V

IH

 limits. The input LOW voltage level at which

oscillation occurs is defined as V

ILD

.

• Next decrease the input HIGH voltage level, V

IH

, until

the output begins to oscillate or steps out a min of 2 ns.

Oscillation is defined as noise on the output LOW level

that exceeds V

IL

 limits, or on output HIGH levels that

exceed V

IH

 limits. The input HIGH voltage level at which

oscillation occurs is defined as V

IHD

• Verify that the GND reference recorded on the oscillo-

scope has not drifted to ensure the accuracy and repeat-

ability on the measurements.

FIGURE 2. Simultaneous Switching Test Circuit

background image

5

www.fairchildsemi.com

7

4

AC

TQ541

Physical Dimensions 

inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

background image

www.fairchildsemi.com

6

7

4

AC

T

Q

541

Physical Dimensions 

inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

background image

Physical Dimensions 

inches (millimeters) unless otherwise noted (Continued)

7

www.fairchildsemi.com

7

4

AC

TQ541

 Quie

Seri

es Oct

a

Buff

er/

L

in

e Dri

ver

 wit

h

 3-ST

A

T

E Outp

uts

Physical Dimensions 

inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com