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1

Features

Low-voltage and Standard-voltage Operation

– 5.0 (V

CC

 = 4.5V to 5.5V)

– 2.7 (V

CC

 = 2.7V to 5.5V)

– 2.5 (V

CC

 = 2.5V to 5.5V)

– 1.8 (V

CC

 = 1.8V to 5.5V)

User-selectable Internal Organization

– 1K: 128 x 8 or 64 x 16

– 2K: 256 x 8 or 128 x 16

– 4K: 512 x 8 or 256 x 16

3-wire Serial Interface

2 MHz Clock Rate (5V)

Self-timed Write Cycle (10 ms max)

High Reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

Automotive Grade and Extended Temperature Devices Available

8-lead PDIP, 8-lead JEDEC and EIAJ SOIC, and 8-lead TSSOP Packages

Description

The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro-

grammable read only memory (EEPROM) organized as 64/128/256 words of 16 bits

each, when the ORG pin is connected to VCC and 128/256/512 words of 8 bits each

when it is tied to ground. The device is optimized for use in many industrial and com-

mercial applications where low power and low voltage operations are essential. The

AT93C46/56/66 is available in space-saving 8-lead PDIP and 8-lead JEDEC and EIAJ

SOIC packages.

3-wire Serial

EEPROMs

1K (128 x 8 or 64 x 16)

2K (256 x 8 or 128 x 16)

4K (512 x 8 or 256 x 16)

AT93C46

AT93C56

AT93C66

Rev. 0172O–08/01

Pin Configurations

Pin Name

Function

CS

Chip Select

SK

Serial Data Clock

DI

Serial Data Input

DO

Serial Data Output

GND

Ground

VCC

Power Supply

ORG

Internal Organization

DC

Don’t Connect

8-lead PDIP

1

2

3

4

8

7

6

5

CS

SK

DI

DO

VCC

DC

ORG

GND

8-lead SOIC

Rotated (R)

(1K JEDEC Only)

1

2

3

4

8

7

6

5

DC

VCC

CS

SK

ORG

GND

DO

DI

8-lead SOIC

1

2

3

4

8

7

6

5

CS

SK

DI

DO

VCC

DC

ORG

GND

(continued)

8-lead TSSOP

1

2

3

4

8

7

6

5

CS

SK

DI

DO

VCC

DC

ORG

GND

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2

AT93C46/56/66

0172O–08/01

The AT93C46/56/66 is enabled through the Chip Select pin (CS), and accessed via a

3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock

(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is

clocked out serially on the data output pin DO. The WRITE cycle is completely self-

timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is

only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought

“high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY

status of the part.

The AT93C46 is available in 4.5V to 5.5V, 2.7V to 5.5V, 2.5V to 5.5V, and 1.8V to 5.5V

versions. The AT93C56/66 is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V

versions.

Block Diagram

Absolute Maximum Ratings*

Operating Temperature.................................. -55

°C to +125°C

*NOTICE:

Stresses beyond those listed under “Absolute 

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and 

functional operation of the device at these or any 

other conditions beyond those indicated in the 

operational sections of this specification is not 

implied. Exposure to absolute maximum rating 

conditions for extended periods may affect 

device reliability

Storage Temperature ..................................... -65

°C to +150°C

Voltage on Any Pin

with Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Notes:

1.  When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 orga-

nization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of

the internal 1 Meg ohm pullup, then the x 16 organization is selected. The feature is not available on the 1.8V devices.

2. For the AT93C46, if x 16 organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends

using the AT93C46A device. For more details, see the AT93C46A datasheet.

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3

AT93C46/56/66

0172O–08/01

Note:

1. This parameter is characterized and is not 100% tested.

Note:

1. V

IL

 min and V

IH

 max are reference only and are not tested.

Pin Capacitance

(1)

Applicable over recommended operating range from T

A

 = 25

°C, f = 1.0 MHz, V

CC

 = +5.0V (unless otherwise noted).

Symbol

Test Conditions

Max

Units

Conditions

C

OUT

Output Capacitance (DO)

5

pF

V

OUT

 = 0V

C

IN

Input Capacitance (CS, SK, DI)

5

pF

V

IN

 = 0V

DC Characteristics

Applicable over recommended operating range from: T

AI

 = -40

°C to +85°C, V

CC

 = +1.8V to +5.5V, 

T

AC

 = 0

°C to +70°C, V

CC

 = +1.8V to +5.5V (unless otherwise noted).

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

V

CC1

Supply Voltage

1.8

5.5

V

V

CC2

Supply Voltage

2.5

5.5

V

V

CC3

Supply Voltage

2.7

5.5

V

V

CC4

Supply Voltage

4.5

5.5

V

I

CC

Supply Current

V

CC

 = 5.0V

READ at 1.0 MHz

0.5

2.0

mA

WRITE at 1.0 MHz

0.5

2.0

mA

I

SB1

Standby Current

V

CC

 = 1.8V

CS = 0V

0

0.1

µA

I

SB2

Standby Current

V

CC

 = 2.5V

CS = 0V

6.0

10.0

µA

I

SB3

Standby Current

V

CC

 = 2.7V

CS = 0V

6.0

10.0

µA

I

SB4

Standby Current

V

CC

 = 5.0V

CS = 0V

17

30

µA

I

IL

Input Leakage

V

IN

 = 0V to V

CC

 0.1

1.0

µA

I

OL

Output Leakage

V

IN

 = 0V to V

CC

 0.1

1.0

µA

V

IL1

(1)

V

IH1

(1)

Input Low Voltage

Input High Voltage

4.5V 

≤ V

CC

 

≤ 5.5V

-0.6

2.0

0.8

V

CC

 + 1

V

V

IL2

(1)

V

IH2

(1)

Input Low Voltage

Input High Voltage

1.8V 

≤ V

CC

 

≤ 2.7V

-0.6

V

CC

 x 0.7

V

CC

 x 0.3

V

CC

 + 1

V

V

OL1

V

OH1

Output Low Voltage

Output High Voltage

4.5V 

≤ V

CC

 

≤ 5.5V

I

OL

 = 2.1 mA

0.4

V

I

OH

 = -0.4 mA

2.4

V

V

OL2

V

OH2

Output Low Voltage

Output High Voltage

1.8V 

≤ V

CC

 

≤ 2.7V

I

OL

 = 0.15 mA

0.2

V

I

OH

 = -100 µA

V

CC

 - 0.2

V

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4

AT93C46/56/66

0172O–08/01

Note:

1. This parameter is characterized and is not 100% tested.

AC Characteristics

Applicable over recommended operating range from T

A

 = -40°C to + 85°C, V

CC

 = As Specified, 

CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

f

SK

SK Clock 

Frequency

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

0

0

0

0

2

1

0.5

0.25

MHz

t

SKH

SK High Time

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

250

250

500

1000

ns

t

SKL

SK Low Time

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

250

250

500

1000

ns

t

CS

Minimum CS 

Low Time

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

250

250

500

1000

ns

t

CSS

CS Setup Time

Relative to SK

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

50

50

100

200

ns

t

DIS

DI Setup Time

Relative to SK

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

100

100

200

400

ns

t

CSH

CS Hold Time

Relative to SK

0

ns

t

DIH

DI Hold Time

Relative to SK

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

100

100

200

400

ns

t

PD1

Output Delay to ‘1’

AC Test

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

250

250

500

1000

ns

t

PD0

Output Delay to ‘0’

AC Test

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

250

250

500

1000

ns

t

SV

CS to Status Valid

AC Test

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

250

250

500

1000

ns

t

DF

CS to DO in High 

Impedance

AC Test

CS = V

IL

4.5V 

≤ V

CC

 

 ≤ 5.5V

2.7V 

≤ V

CC

 

 ≤ 5.5V

2.5V 

≤ V

CC

 

 ≤ 5.5V

1.8V 

≤ V

CC

 

 ≤ 5.5V

100

100

200

400

ns

t

WP

Write Cycle Time

10

ms

4.5V 

≤ V

CC

 

 ≤ 5.5V

3

ms

Endurance

(1)

5.0V, 25°C, Page Mode

1M

Write Cycles

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5

AT93C46/56/66

0172O–08/01

Instruction Set for the AT93C46

Instruction

SB

Op 

Code

Address

Data

Comments

x 8

x 16

x 8

x 16

READ

1

10

A

- A

0

A

- A

0

Reads data stored in memory, at 

specified address.

EWEN

1

00

11XXXXX

11XXXX

Write enable must precede all 

programming modes.

ERASE

1

11

A

- A

0

A

- A

0

Erase memory location A

n

 - A

0

.

WRITE

1

01

A

- A

0

A

- A

0

D

- D

0

D

15 

- D

0

Writes memory location A

n

 -

 

A

0

.

ERAL

1

00

10XXXXX

10XXXX

Erases all memory locations. Valid 

only at V

CC

 = 4.5V to 5.5V.

WRAL

1

00

01XXXXX

01XXXX

D

- D

0

D

15 

- D

0

Writes all memory locations. Valid 

only at V

CC

 = 4.5V to 5.5V.

EWDS

1

00

00XXXXX

00XXXX

Disables all programming 

instructions.

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6

AT93C46/56/66

0172O–08/01

Functional 

Description

The AT93C46/56/66 is accessed via a simple and versatile 3-wire serial communication

interface. Device operation is controlled by seven instructions issued by the host pro-

cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit

(logic “1”) followed by the appropriate Op Code and the desired memory Address

location.

READ (READ): The Read (READ) instruction contains the Address code for the mem-

ory location to be read. After the instruction and address are decoded, data from the

selected memory location is available at the serial output pin DO. Output data changes

are synchronized with the rising edges of serial clock SK. It should be noted that a

dummy bit (logic “0”) precedes the 8- or 16-bit data output string.

ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the

Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable

(EWEN) instruction must be executed first before any programming instructions can be

carried out. Please note that once in the Erase/Write Enable state, programming

remains enabled until an Erase/Write Disable (EWDS) instruction is executed or V

CC

power is removed from the part.

ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified

memory location to the logical “1” state. The self-timed erase cycle starts once the

ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY

status of the part if CS is brought high after being kept low for a minimum of 250 ns (t

CS

).

A logic “1” at pin DO indicates that the selected memory location has been erased, and

the part is ready for another instruction.

WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be

written into the specified memory location. The self-timed programming cycle, t

WP

, starts

after the last bit of data is received at serial data input pin DI. The DO pin outputs the

READY/BUSY status of the part if CS is brought high after being kept low for a minimum

of 250 ns (t

CS

). A logic “0” at DO indicates that programming is still in progress. A logic

“1” indicates that the memory location at the specified address has been written with the

data pattern contained in the instruction and the part is ready for further instructions. A

READY/BUSY status cannot be obtained if the CS is brought high after the end of

the self-timed programming cycle, t

WP

.

ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-

ory array to the logic “1” state and is primarily used for testing purposes. The DO pin

outputs the READY/BUSY status of the part if CS is brought high after being kept low for

a minimum of 250 ns (t

CS

). The ERAL instruction is valid only at V

CC

 = 5.0V 

± 10%. 

WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations

with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY

status of the part if CS is brought high after being kept low for a minimum of 250 ns (t

CS

).

The WRAL instruction is valid only at V

CC

 = 5.0V ±

 10%. 

ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the

Erase/Write Disable (EWDS) instruction disables all programming modes and should be

executed after all programming operations. The operation of the READ instruction is

independent of both the EWEN and EWDS instructions and can be executed at any

time.

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7

AT93C46/56/66

0172O–08/01

Timing Diagrams

Synchronous Data Timing

Note:

1. This is the minimum SK period.

Notes:

1. A

8

 is a DON’T CARE value, but the extra clock is required.

2. A

7

 is a DON’T CARE value, but the extra clock is required.

READ Timing

Organization Key for Timing Diagrams

I/O

AT93C46 (1K)

AT93C56 (2K)

AT93C66 (4K)

x 8

x 16

x 8

x 16

x 8

x 16

A

N

A

6

A

5

A

8

(1)

A

7

(2)

A

8

A

7

D

N

D

7

D

15

D

7

D

15

D

7

D

15

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8

AT93C46/56/66

0172O–08/01

EWEN Timing

EWDS Timing

WRITE Timing

WRAL Timing

(1)

Note:

1. Valid only at V

CC

 = 4.5V to 5.5V.

CS

t

CS

1

1

...

0

0

1

SK

DI

CS

t

CS

SK

DI

1

0

0

0

0

...

SK

CS

t

CS

t

WP

1

1

A

N

D

N

0

A0

D0

...

...

DI

DO

HIGH IMPEDANCE

BUSY

READY

CS

SK

DI

DO

HIGH IMPEDANCE

BUSY

READY

1

0

0

1

...

D

N

t

CS

t

WP

...

D0

0

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9

AT93C46/56/66

0172O–08/01

ERASE Timing

ERAL Timing

(1)

Note:

1. Valid only at V

CC

 = 4.5V to 5.5V.

SK

1

1

...

1

CS

DI

A

N

t

CS

t

SV

t

DF

t

WP

A

N-1

A

N-2

A0

CHECK

STATUS

STANDBY

READY

BUSY

DO

HIGH IMPEDANCE

HIGH IMPEDANCE

SK

CS

DI

1

1

0

0

0

DO

HIGH IMPEDANCE

HIGH IMPEDANCE

READY

BUSY

CHECK

STATUS

STANDBY

t

WP

t

CS

t

SV

t

DF

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10

AT93C46/56/66

0172O–08/01

AT93C46 Ordering Information

t

WP

 (max)

(ms)

I

CC

 (max)

(µA)

I

SB

 (max)

(µA)

f

MAX

(kHz)

Ordering Code

Package

Operation Range

10

2000

30.0

2000

AT93C46-10PC

AT93C46-10SC

AT93C46R-10SC

AT93C46W-10SC

AT93C46-10TC

8P3

8S1

8S1

8S2

8T

Commercial

(0

°C to 70°C)

30.0

2000

AT93C46-10PI

AT93C46-10SI

AT93C46R-10SI

AT93C46W-10SI

AT93C46-10TI

8P3

8S1

8S1

8S2

8T

Industrial

(-40

°C to 85°C)

10

800

10.0

1000

AT93C46-10PC-2.7

AT93C46-10SC-2.7

AT93C46R-10SC-2.7

AT93C46W-10SC-2.7

AT93C46-10TC-2.7

8P3

8S1

8S1

8S2

8T

Commercial

(0

°C to 70°C)

10.0

1000

AT93C46-10PI-2.7

AT93C46-10SI-2.7

AT93C46R-10SI-2.7

AT93C46W-10SI-2.7

AT93C46-10TI-2.7

8P3

8S1

8S1

8S2

8T

Industrial

(-40

°C to 85°C)

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8S2

8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8T

8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

Blank

Standard Operation (4.5V to 5.5V)

-2.7

Low Voltage (2.7V to 5.5V)

-2.5

Low Voltage (2.5V to 5.5V)

R

Rotated Pinout

background image

11

AT93C46/56/66

0172O–08/01

10

600

10.0

500

AT93C46-10PC-2.5

AT93C46-10SC-2.5

AT93C46R-10SC-2.5

AT93C46W-10SC-2.5

AT93C46-10TC-2.5

8P3

8S1

8S1

8S2

8T

Commercial

(0

°C to 70°C)

10.0

500

AT93C46-10PI-2.5

AT93C46-10SI-2.5

AT93C46R-10SI-2.5

AT93C46W-10SI-2.5

AT93C46-10TI-2.5

8P3

8S1

8S1

8S2

8T

Industrial

(-40

°C to 85°C)

10

80

0.1

250

AT93C46-10PC-1.8

AT93C46-10SC-1.8

AT93C46R-10SC-1.8

AT93C46W-10SC-1.8

AT93C46-10TC-1.8

8P3

8S1

8S1

8S2

8T

Commercial

(0

°C to 70°C)

0.1

250

AT93C46-10PI-1.8

AT93C46-10SI-1.8

AT93C46R-10SI-1.8

AT93C46W-10SI-1.8

AT93C46-10TI-1.8

8P3

8S1

8S1

8S2

8T

Industrial

(-40

°C to 85°C)

AT93C46 Ordering Information (Continued)

t

WP

 (max)

(ms)

I

CC

 (max)

(µA)

I

SB

 (max)

(µA)

f

MAX

(kHz)

Ordering Code

Package

Operation Range

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8S2

8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8T

8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

Blank

Standard Operation (4.5V to 5.5V)

-2.7

Low Voltage (2.7V to 5.5V)

-2.5

Low Voltage (2.5V to 5.5V)

-1.8

Low Voltage (1.8V to 5.5V)

R

Rotated Pinout

background image

12

AT93C46/56/66

0172O–08/01

AT93C56 Ordering Information

t

WP

 (max)

(ms)

I

CC

 (max)

(µA)

I

SB

 (max)

(µA)

f

MAX

(kHz)

Ordering Code

Package

Operation Range

10

2000

30.0

2000

AT93C56-10PC

AT93C56-10SC

AT93C56W-10SC

8P3

8S1

8S2

Commercial

(0

°C to 70°C)

30.0

2000

AT93C56-10PI

AT93C56-10SI

AT93C56W-10SI

8P3

8S1

8S2

Industrial

(-40

°C to 85°C)

10

800

10.0

1000

AT93C56-10PC-2.7

AT93C56-10SC-2.7

AT93C56W-10SC-2.7

8P3

8S1

8S2

Commercial

(0

°C to 70°C)

10.0

1000

AT93C56-10PI-2.7

AT93C56-10SI-2.7

AT93C56W-10SI-2.7

8P3

8S1

8S2

Industrial

(-40

°C to 85°C)

10

600

10.0

500

AT93C56-10PC-2.5

AT93C56-10SC-2.5

AT93C56W-10SC-2.5

8P3

8S1

8S2

Commercial

(0

°C to 70°C)

10.0

500

AT93C56-10PI-2.5

AT93C56-10SI-2.5

AT93C56W-10SI-2.5

8P3

8S1

8S2

Industrial

(-40

°C to 85°C)

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8S2

8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

Options

Blank

Standard Operation (4.5V to 5.5V)

-2.7

Low Voltage (2.7V to 5.5V)

-2.5

Low Voltage (2.5V to 5.5V)

background image

13

AT93C46/56/66

0172O–08/01

AT93C66 Ordering Information

t

WP

 (max)

(ms)

I

CC

 (max)

(µA)

I

SB

 (max)

(µA)

f

MAX

(kHz)

Ordering Code

Package

Operation Range

10

2000

30.0

2000

AT93C66-10PC

AT93C66-10SC

AT93C66W-10SC

AT93C66-10TC

8P3

8S1

8S2

8T

Commercial

(0

°C to 70°C)

30.0

2000

AT93C66-10PI

AT93C66-10SI

AT93C66W-10SI

AT93C66-10TI

8P3

8S1

8S2

8T

Industrial

(-40

°C to 85°C)

10

800

10.0

1000

AT93C66-10PC-2.7

AT93C66-10SC-2.7

AT93C66W-10SC-2.7

AT93C66-10TC-2.7

8P3

8S1

8S2

8T

Commercial

(0

°C to 70°C)

10.0

1000

AT93C66-10PI-2.7

AT93C66-10SI-2.7

AT93C66W-10SI-2.7

AT93C66-10TI-2.7

8P3

8S1

8S2

8T

Industrial

(-40

°C to 85°C)

10

600

10.0

500

AT93C66-10PC-2.5

AT93C66-10SC-2.5

AT93C66W-10SC-2.5

AT93C66-10TC-2.5

8P3

8S1

8S2

8T

Commercial

(0

°C to 70°C)

10.0

500

AT93C66-10PI-2.5

AT93C66-10SI-2.5

AT93C66W-10SI-2.5

AT93C66-10TI-2.5

8P3

8S1

8S2

8T

Industrial

(-40

°C to 85°C)

10

80

0.1

250

AT93C66-10PC-1.8

AT93C66-10SC-1.8

AT93C66W-10SC-1.8

AT93C66-10TC-1.8

8P3

8S1

8S2

8T

Commercial

(0

°C to 70°C)

0.1

250

AT93C66-10PI-1.8

AT93C66-10SI-1.8

AT93C66W-10SI-1.8

AT93C66-10TI-1.8

8P3

8S1

8S2

8T

Industrial

(-40

°C to 85°C)

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8S2

8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8T

8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

Blank

Standard Operation (4.5V to 5.5V)

-2.7

Low Voltage (2.7V to 5.5V)

-2.5

Low Voltage (2.5V to 5.5V)

-1.8

Low Voltage (1.8V to 5.5V)

background image

Packaging Information

14

AT93C46/56/66

0172O–08/01

.400 (10.16)

.355 (9.02)

PIN

1

.280 (7.11)

.240 (6.10)

.037 (.940)

.027 (.690)

.300 (7.62) REF

.210 (5.33) MAX

SEATING

PLANE

.100 (2.54) BSC

.015 (.380) MIN

.022 (.559)

.014 (.356)

.150 (3.81)

.115 (2.92)

.070 (1.78)

.045 (1.14)

.325 (8.26)

.300 (7.62)

0

15

REF

.430 (10.9) MAX

.012 (.305)

.008 (.203)

.020 (.508)

.013 (.330)

PIN 1 

.157 (3.99)

.150 (3.81)

.244 (6.20)

.228 (5.79)

.050 (1.27) BSC

.196 (4.98)

.189 (4.80)

.068 (1.73)

.053 (1.35)

.010 (.254)

.004 (.102)

0

8

REF

.010 (.254)

.007 (.203)

.050 (1.27)

.016 (.406)

.020 (.508)

.012 (.305)

.213 (5.41)

.205 (5.21)

.330 (8.38)

.300 (7.62)

PIN 1 

.050 (1.27) BSC

.212 (5.38)

.203 (5.16)

.080 (2.03)

.070 (1.78)

.013 (.330)

.004 (.102)

0

8

REF

.010 (.254)

.007 (.178)

.035 (.889)

.020 (.508)

*Controlling dimension: millimeters

6.50 (.256)

6.25 (.246)

0.30 (.012)

0.19 (.008)

.65 (.026) BSC

1.05 (.041)

0.80 (.033)

3.10 (.122)

4.5 (.177)

2.90 (.114)

4.3 (.169)

0.15 (.006)

0.05 (.002)

1.20 (.047) MAX

0.20 (.008)

0.75 (.030)

0.09 (.004)

0.45 (.018)

0

8

REF

PIN 1

8P3, 8-lead, 0.300" Wide, Plastic Dual Inline 

Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 BA

8S1, 8-lead, 0.150" Wide, Plastic Gull Wing Small 

Outline (JEDEC SOIC)

Dimensions in Inches and (Millimeters)

8S2, 8-lead, 0.200" Wide, Plastic Gull Wing Small 

Outline (EIAJ SOIC)

Dimensions in Inches and (Millimeters)

8T, 8-lead, 0.170" Wide, Thin Shrink Small Outline 

Package (TSSOP)

Dimensions in Millimeters and (Inches)*

background image

 Printed on recycled paper.

© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

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Atmel Product Operations

Corporate Headquarters

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FAX (33) 0 2 40 18 19 60

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FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

0172O–08/01/xM

ATMEL

®

 is the registered trademark of Atmel.

Other terms and product names may be the trademarks of others.


Document Outline