background image

1

©2000 Integrated Device Technology, Inc.

MARCH  2000

  DSC-2911/8

I/O

Control

Address

Decoder

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/

W

L

UB

L

BUSY

L

A

11L

A

0L

2911 drw 01

LB

L

CE

L

OE

L

I/O

8L

-I/O

15L

I/O

0L

-I/O

7L

CE

L

OE

L

R/

W

L

SEM

L

INT

L

M/

S

R/

W

R

UB

R

BUSY

R

LB

R

CE

R

OE

R

I/O

8R

-I/O

15R

I/O

0R

-I/O

7R

A

11R

A

0R

R/

W

R

SEM

R

INT

R

CE

R

OE

R

(2)

(1,2)

(1,2)

(2)

12

12

IDT70V24S/L

HIGH-SPEED 3.3V

4K x 16 DUAL-PORT

STATIC RAM

Features

x

x

x

x

x

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

x

x

x

x

x

High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

x

x

x

x

x

Low-power operation

– IDT70V24S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V24L

Active: 380mW (typ.)

Standby: 660

µ

W (typ.)

x

x

x

x

x

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

x

x

x

x

x

IDT70V24 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

x

x

x

x

x

M/

S = V

IH

 for 

BUSY output flag on Master

M/

S = V

IL

 for 

BUSY input on Slave

x

x

x

x

x

BUSY and Interrupt Flag

x

x

x

x

x

On-chip port arbitration logic

x

x

x

x

x

Full on-chip hardware support of semaphore signaling

between ports

x

x

x

x

x

Fully asynchronous operation from either port

x

x

x

x

x

LVTTL-compatible, single 3.3V (±0.3V) power supply

x

x

x

x

x

Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP

x

x

x

x

x

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

NOTES:

1. (MASTER): 

BUSY is output; (SLAVE): BUSY is input.

2.

BUSY outputs and INT outputs are non-tri-stated push-pull.

background image

     

      6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

2

Description

The IDT70V24 is a high-speed 4K x 16 Dual-Port Static RAM. The

IDT70V24 is designed to be used as a stand-alone 64K-bit Dual-Port RAM

or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more

word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach

in 32-bit or wider memory system applications results in full-speed, error-

free operation without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asyn-chronous access for

reads or writes to any location in memory.  An automatic power down

feature controlled by 

CE permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology,

these devices typically operate on only 400mW of power.

The IDT70V24 is packaged in a ceramic 84-pin PGA, an 84-Pin

PLCC and a 100-pin Thin Quad Flatpack.

Pin Configurations

(1,2,3)

NOTES:

1. All V

CC

 pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.

PN100-1 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

2911 drw 02

14

15

16

17

18

19

20

INDEX

21

22

23

24

11 10 9 8 7 6 5 4

3 2 1 84 83

33 34 35 36 37 38 39 40 41 42 43 44 45

V

CC

GND

I/O

8L

A

7L

13

12

25

26

27

28

29

30

31

32

46 47 48 49 50 51 52 53

72

71

70

69

68

67

66

65

64

63

62

73

74

61

60

59

58

57

56

55

54

82 81 80 79 78 77 76 75

GND

BUSY

L

GND

IDT70V24J

J84-1

(4)

84-Pin PLCC

Top View

(5)

INT

L

M/

S

INT

R

I/O

9L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

I/O

15L

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

I/O

7R

I/O

8R

A

6L

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

BUSY

R

A

0R

A

2R

A

3R

A

4R

A

5R

A

6R

A

1R

I/

O

7

L

I/

O

6

L

I/

O

5

L

I/

O

4

L

I/

O

3

L

I/

O

2

L

V

C

C

R

/

W

L

SE

M

L

CE

L

UB

L

LB

L

N

/C

A

1

1

L

G

N

D

I/

O

1

L

I/

O

0

L

A

1

0

L

A

9

L

A

8

L

O

E

L

I/

O

9

R

I/

O

1

0

R

I/

O

1

1

R

I/

O

1

2

R

I/

O

1

3

R

I/

O

1

4

R

G

N

D

I/

O

1

5

R

G

N

D

N

/C

A

1

1

R

A

1

0

R

A

9

R

A

8

R

A

7

R

O

E

R

R

/

W

R

SE

M

R

CE

R

UB

R

LB

R

Index

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT70V24PF

PN100-1

(4)

100-Pin TQFP

Top View

(5)

N/C

N/C

N/C

N/C

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

I/O

3R

V

CC

I/O

4R

I/O

5R

I/O

6R

N/C

N/C

N/C

N/C

2911 drw 03

N/C

N/C

N/C

N/C

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

L

GND

M/

S

BUSY

R

INT

R

A

0R

N/C

N/C

N/C

N/C

BUSY

L

A

1R

A

2R

A

3R

A

4R

I/

O

9

L

I/

O

8

L

I/

O

7

L

I/

O

6

L

I/

O

5

L

I/

O

4

L

I/

O

3

L

I/

O

2

L

G

N

D

I/

O

1

L

I/

O

0

L

O

E

L

V

C

C

R

/

W

L

SE

M

L

C

E

L

U

B

L

LB

L

N

/C

A

1

1

L

A

1

0

L

A

9

L

A

8

L

A

7

L

A

6

L

I/

O

7

R

I/

O

8

R

I/

O

9

R

I/

O

1

0

R

I/

O

1

1

R

I/

O

1

2

R

I/

O

1

3

R

I/

O

1

4

R

G

N

D

I/

O

1

5

R

O

E

R

R

/

W

R

SE

M

R

C

E

R

U

B

R

LB

R

G

N

D

N

/C

A

1

1

R

A

1

0

R

A

9

R

A

8

R

A

7

R

A

6

R

A

5

R

background image

           6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

3

NOTES:

1. All V

CC

 pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Pin Names

Pin Configurations

(1,2,3)

 (con't.)

2911 drw 04

I/O

7L

63

61

60

58

55

54

51

48

46

45

66

67

69

72

75

76

79

81

82

83

1

2

5

7

8

11

10

12

14

17

20

23

26

28

29

32

31

33

35

38

41

43

IDT70V24G

G84-3

(4)

84-Pin PGA

Top View

(5)

A

B

C

D

E

F

G

H

J

K

L

42

59

56

49

50

40

25

27

30

36

34

37

39

84

3

4

6

9

15

13

16

18

22

24

19

21

68

71

70

77

80

UB

R

CE

R

GND

11

10

09

08

07

06

05

04

03

02

01

64

65

62

57

53

52

47

44

73

74

78

GND

GND

R/

W

R

OE

R

LB

R

GND

GND

SEM

R

N/C

UB

L

CE

L

R/

W

L

OE

L

GND

SEM

L

V

CC

LB

L

INT

R

BUSY

R

BUSY

L

M/

S

I

NT

L

A

11L

N/C

Index

I/O

5L

I/O

4L

I/O

2L

I/O

0L

I/O

10L

I/O

8L

I/O

6L

I/O

3L

I/O

1L

I/O

11L

I/O

9L

I/O

13L

I/O

12L

I/O

15L

I/O

14L

I/O

0R

A

9L

A

10L

A

8L

A

7L

A

5L

A

6L

A

4L

A

3L

A

2L

A

0L

A

1L

A

0R

A

2R

A

1R

A

5R

A

3R

A

6R

A

4R

A

9R

A

7R

A

8R

A

10R

A

11R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

7R

I/O

6R

I/O

9R

I/O

8R

I/O

11R

I/O

10R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

V

CC

Left Port

Right Port

Names

CE

L

CE

R

Chip Enable

R/

W

L

R/

W

R

Read/Write Enable

OE

L

OE

R

Output Enable

A

0L

 - A

11L

A

0R

 - A

11R

Address

I/O

0L

 - I/O

15L

I/O

0R

 - I/O

15R

Data Input/Output

SEM

L

SEM

R

Semaphore Enable

UB

L

UB

R

Upper Byte Select

LB

L

LB

R

Lower Byte Select

INT

L

INT

R

Interrupt Flag

BUSY

L

BUSY

R

Busy Flag

M/

S

Master or Slave Select

V

CC

Power

GND

Ground

2911 tbl 01

background image

     

      6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

4

Truth Table I:  Non-Contention Read/Write Control

Truth Table II:  Semaphore Read/Write Control

(1)

NOTE:

1.

A

0L

 — A

11L

 

 A

0R

 — A

11R

NOTE:

1.

There are eight semaphore flags written to via I/O

0

 and read from all of the I/O's (I/O

0

-I/O

15

). These eight semaphores are addressed by A

0

-A

2

.

Inputs

(1)

Outputs

Mode

CE

R/

W

OE

UB

LB

SEM

I/O

8-15

I/O

0-7

H

X

X

X

X

H

High-Z

High-Z

Deselected: Power Down

X

X

X

H

H

H

High-Z

High-Z

Both Bytes Deselected

L

L

X

L

H

H

DATA

IN

High-Z

Write to Upper Byte Only

L

L

X

H

L

H

High-Z

DATA

IN

Write to Lower Byte Only

L

L

X

L

L

H

DATA

IN

DATA

IN

Write to Both Bytes

L

H

L

L

H

H

DATA

OUT

High-Z

Read Upper Byte Only

L

H

L

H

L

H

High-Z

DATA

OUT

Read Lower Byte Only

L

H

L

L

L

H

DATA

OUT

DATA

OUT

Read Both Bytes

X

X

H

X

X

X

High-Z

High-Z

Outputs Disabled

2911 tbl 02

Inputs

Outputs

Mode

CE

R/

W

OE

UB

LB

SEM

I/O

8-15

I/O

0-7

H

H

L

X

X

L

DATA

OUT

DATA

OUT

Read Data in Semaphore Flag

X

H

L

H

H

L

DATA

OUT

DATA

OUT

Read Data in Semaphore Flag

H

X

X

X

L

DATA

IN

DATA

IN

Write D

IN0

 into Semaphore Flag

X

X

H

H

L

DATA

IN

DATA

IN

Write D

IN0

 into Semaphore Flag

L

X

X

L

X

L

____

____

Not Allowed

L

X

X

X

L

L

____

____

Not Allowed

2911 tbl 03

background image

           6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

5

Absolute Maximum Ratings

(1)

Maximum Operating Temperature

and Supply Voltage

(1)

Recommended DC Operating

Conditions

Capacitance

(TA = +25°C, f = 1.0MHz)

NOTES:

1.

Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2.

V

TERM

 must not exceed Vcc +0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period over V

TERM

 > Vcc + 0.3V

.

NOTES:

1.

This parameter is determined by device characterization but is not production

tested.

2.

3dV references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

NOTES:

1. This is the parameter T

A

.

NOTES:

1.

V

IL

> -1.5V for pulse width less than 10ns.

2.

V

TERM

 must not exceed Vcc + 0.3V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range 

(V

CC 

= 3.3V ± 0.3V)

NOTE:

1.

At V

CC

 < 2.0V input leakages are undefined.

Symbol

Rating

Commercial

& Industrial

Unit

V

TERM

(2)

Terminal Voltage

with Respect

to GND

-0.5 to +4.6

V

T

BIAS

Temperature

Under Bias

-55 to +125

o

C

T

STG

Storage

Temperature

-55 to +125

o

C

I

OUT

DC Output

Current

50

mA

2911 tbl 04

Grade

Ambient

Temperature

GND

Vcc

Commercial

0

O

C to +70

O

C

0V

3.3V 

+

 0.3V

Industrial

-40

O

C to +85

O

C

0V

3.3V 

+

 0.3V

2911 tbl 05

Symbol

Parameter

Min.

Typ.

Max.

Unit

V

CC

Supply Voltage

3.0

3.3

3.6

V

GND

Ground

0

0

0

V

V

IH

Input High Voltage

2.0

____

V

CC

+0.3

(2)

V

V

IL

Input Low Voltage

-0.3

(1)

____

0.8

V

2911 tbl  06

Symbol

Parameter

Conditions

(2)

Max.

Unit

C

IN

Input Capacitance

V

IN

 = 3dV

9

pF

C

OUT

Output Capacitance

V

OUT

 = 3dV

11

pF

2911 tbl 07

Symbol

Parameter

Test Conditions

70V24S

70V24L

Unit

Min.

Max.

Min.

Max.

|I

LI

|

Input Leakage Current

(1)

V

CC

 = 3.6V, V

IN

 = 0V to V

CC

___

10

___

5

µA

|I

LO

|

Output Leakage Current

CE

 = V

IH

, V

OUT

 = 0V to V

CC

___

10

___

5

µA

V

OL

Output Low Voltage

I

OL

 = +4mA

___

0.4

___

0.4

V

V

OH

Output High Voltage

I

OH

 = -4mA

2.4

___

2.4

___

V

2911 tbl 08

background image

     

      6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

6

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(1)

 

(V

CC 

= 3.3V ± 0.3V)

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. V

CC

 = 3.3V, T

A

 = +25°C, and are not production tested. I

CC DC 

= 115mA (

typ

.)

3. At f = f

MAX

,

 address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t

RC

, and using “AC Test Conditions” of input levels of GND

to 3V.

4. f = 0 means no address or control lines change.

5.   Port "A" may be either left or right port. Port "B" is the opposite from port "A".

70V24X15

Com'l Only

70V24X20

Com'l

& Ind

70V24X25

Com'l

& Ind

Symbol

Parameter

Test Condition

Version

Typ.

(2)

Max.

Typ.

(2)

Max.

Typ.

(2)

Max.

Unit

I

CC

Dynamic Operating

Current

(Both Ports Active)

CE

 = V

IL

, Outputs Open

SEM

 = V

IH

f = f

MAX

(3)

COM'L

S

L

150

140

215

185

140

130

200

175

130

125

190

165

mA

IND

S

L

____

____

____

____

140

130

225

195

130

125

210

180

I

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

CE

R

 and 

CE

L

 = V

IH

SEM

R

 = 

SEM

L

 = V

IH

f = f

MAX

(3)

COM'L

S

L

25

20

35

30

20

15

30

25

16

13

30

25

mA

MIL &

IND

S

L

____

____

____

____

20

15

45

40

16

13

45

40

I

SB2

Standby Current

(One Port - TTL

Level Inputs)

CE

"A"

 = V

IL

 and 

CE

"B" 

= V

IH

(5)

Active Port Outputs Open,

f=f

MAX

(3)

SEM

R

 = 

SEM

L

 = V

IH

COM'L

S

L

85

80

120

110

80

75

110

100

75

72

110

95

mA

MIL &

IND

S

L

____

____

____

____

80

75

130

115

75

72

125

110

I

SB3

Full Standby Current

(Both Ports  -

CMOS Level Inputs)

Both Ports 

CE

L

 and

CE

R

 > V

CC

 - 0.2V,

V

IN

 > V

CC

 - 0.2V or

V

IN

 < 0.2V, f = 0

(4)

SEM

R

 = 

SEM

L

 > V

CC

-0.2V

COM'L

S

L

1.0

0.2

5

2.5

1.0

0.2

5

2.5

1.0

0.2

5

2.5

mA

MIL &

IND

S

L

____

____

____

____

1.0

0.2

15

5

1.0

0.2

15

5

I

SB4

Full Standby Current

(One Port -

CMOS Level Inputs)

CE

"A"

  < 0.2V and

CE

"B"

  > V

CC

 - 0.2V

(5)

SEM

R

 = 

SEM

L

 > V

CC

-0.2V

V

IN

 > V

CC

 - 0.2V or V

IN

  < 0.2V

Active Port Outputs Open,

f = f

MAX

(3)

COM'L

S

L

85

80

125

105

80

75

115

100

75

70

105

90

mA

MIL &

IND

S

L

____

____

____

____

80

75

130

115

75

70

120

105

2911 tbl 09a

70V24X35

Com'l

& Ind

70V24X55

Com'l

& Ind

Symbol

Parameter

Test Condition

Version

Typ.

(2)

Max.

Typ.

(2)

Max.

Unit

I

CC

Dynamic Operating

Current

(Both Ports Active)

CE

 = V

IL

, Outputs Open

SEM

 = V

IH

f = f

MAX

(3)

COM'L

S

L

120

115

180

155

120

115

180

155

mA

IND

S

L

120

115

200

170

120

115

200

170

I

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

CE

R

 and 

CE

L

 = V

IH

SEM

R

 = 

SEM

L

 = V

IH

f = f

MAX

(3)

COM'L

S

L

13

11

25

20

13

11

25

20

mA

MIL &

IND

S

L

13

11

40

35

13

11

40

35

I

SB2

Standby Current

(One Port - TTL

Level Inputs)

CE

"A"

 = V

IL

 and 

CE

"B" 

= V

IH

(5)

Active Port Outputs Open,

f=f

MAX

(3)

SEM

R

 = 

SEM

L

 = V

IH

COM'L

S

L

70

65

100

90

70

65

100

90

mA

MIL &

IND

S

L

70

65

120

105

70

65

120

105

I

SB3

Full Standby Current

(Both Ports  -

CMOS Level Inputs)

Both Ports 

CE

L

 and

CE

R

 >  V

CC

 - 0.2V,

V

IN

 >  V

CC

 - 0.2V or

V

IN

 < 0.2V, f = 0

(4)

SEM

R

 = 

SEM

L

 >  V

CC

-0.2V

COM'L

S

L

1.0

0.2

5

2.5

1.0

0.2

5

2.5

mA

MIL &

IND

S

L

1.0

0.2

15

5

1.0

0.2

15

5

I

SB4

Full Standby Current

(One Port -

CMOS Level Inputs)

CE

"A"

  < 0.2V and

CE

"B"

  >  V

CC

 - 0.2V

(5)

SEM

R

 = 

SEM

L

 >  V

CC

-0.2V

V

IN

 >  V

CC

 - 0.2V or V

IN

 < 0.2V

Active Port Outputs Open,

f = f

MAX

(3)

COM'L

S

L

65

60

100

85

65

60

100

85

mA

MIL &

IND

S

L

65

60

115

100

65

60

115

100

2911 tbl 09b

background image

           6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

7

AC Test Conditions

Figure 1.  AC Output Test Load

(for t

LZ

, t

HZ

, t

WZ

, t

OW

)

Figure 2.  Output Test Load

(for t

LZ

, t

HZ

, t

WZ

, t

OW

)

* Including scope and jig.

Timing of Power-Up Power-Down

2911 drw 06

t

PU

I

CC

I

SB

t

PD

CE

50%

50%

,

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

1.5V

Figures 1 and 2

2911 tbl 10

2911 drw 05

590

30pF

435

3.3V

DATA

OUT

BUSY

I

NT

590

5pF*

435

3.3V

DATA

OUT

,

background image

     

      6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

8

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2.

This parameter is guaranteed by device characterization, but is not production tested.

3.

To access RAM, 

CE = V

IL

UB or LB = V

IL

, and 

SEM = V

IH. 

To access semaphore, 

CE = V

IH

 or 

UB and LB = V

IH

, and 

SEM = V

IL

.

4.

'X' in part number indicates power rating (S or L).

70V24X15

Com'l Only

70V24X20

Com'l

& Ind

70V24X25

Com'l

& Ind

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

READ CYCLE

t

RC

Read Cycle Time

15

____

20

____

25

____

ns

t

AA

Address Access Time

____

15

____

20

____

25

ns

t

ACE

Chip Enable Access Time

(3)

____

15

____

20

____

25

ns

t

ABE

Byte Enable Access Time

(3)

____

15

____

20

____

25

ns

t

AOE

Output Enable Access Time

(3)

____

10

____

12

____

13

ns

t

OH

Output Hold from Address Change

3

____

3

____

3

____

ns

t

LZ

Output Low-Z Time

(1,2)

3

____

3

____

3

____

ns

t

HZ

Output High-Z Time

(1,2)

____

10

____

12

____

15

ns

t

PU

Chip Enable to Power Up Time

(1,2)

0

____

0

____

0

____

ns

t

PD

Chip Disable to Power Down Time

(1,2)

____

15

____

20

____

25

ns

t

SOP

Semaphore Flag Update Pulse (

OE

 or 

SEM

)

10

____

10

____

10

____

ns

t

SAA

Semaphore Address Access

(3)

____

15

____

20

____

25

ns

2911 tbl 11a

70V24X35

Com'l

& Ind

70V24X55

Com'l

& Ind

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

READ CYCLE

t

RC

Read Cycle Time

35

____

55

____

ns

t

AA

Address Access Time

____

35

____

55

ns

t

ACE

Chip Enable Access Time

(3)

____

35

____

55

ns

t

ABE

Byte Enable Access Time

(3)

____

35

____

55

ns

t

AOE

Output Enable Access Time

(3)

____

20

____

30

ns

t

OH

Output Hold from Address Change

3

____

3

____

ns

t

LZ

Output Low-Z Time

(1,2)

3

____

3

____

ns

t

HZ

Output High-Z Time

(1,2)

____

15

____

25

ns

t

PU

Chip Enable to Power Up Time

(1,2)

0

____

0

____

ns

t

PD

Chip Disable to Power Down Time

(1,2)

____

35

____

50

ns

t

SOP

Semaphore Flag Update Pulse (

OE

 or 

SEM

)

15

____

15

____

ns

t

SAA

Semaphore Address Access

(3)

____

35

____

55

ns

2911 tbl 11b

background image

           6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

9

t

RC

R/

W

CE

ADDR

t

AA

OE

UB

,

LB

2911 drw 07

(4)

t

ACE

(4)

t

AOE

(4)

t

ABE

(4)

(1)

t

LZ

t

OH

(2)

t

HZ

(3,4)

t

BDD

DATA

OUT

BUSY

OUT

VALID DATA

(4)

Waveform of Read Cycles

(5)

NOTES:

1. Timing depends on which signal is asserted last, 

OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first 

CE, OE, LB, or UB.

3. t

BDD 

delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read  operations 

BUSY has no  relation

to valid output data.

4. Start of valid data depends on which timing becomes effective last t

ABE

, t

AOE

, t

ACE

, t

AA

 or t

BDD

.

5.

SEM = V

IH

.

background image

     

      6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

10

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2.

This parameter is guaranteed by device characterization, but is not production tested.

3. To access SRAM, 

CE = V

IL

UB or LB = V

IL

SEM = V

IH

. To access semaphore, 

CE = V

IH

 or 

UB and LB = V

IH

 and 

SEM = V

IL

. Either condition must be valid for

the entire t

EW

 time.

4. The specification for t

DH

 must be met by the device supplying write data to the SRAM under all operating conditions. Although t

DH

 and t

OW

 values will vary over

voltage and temperature, the actual t

DH

 will always be smaller than the actual t

OW

.

5. 'X' in part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage

(5)

Symbol

Parameter

70V24X15

Com'l Only

70V24X20

Com'l

& Ind

70V24X25

Com'l

& Ind

Unit

Min.

Max.

Min.

Max.

Min.

Max.

WRITE CYCLE

t

WC

Write Cycle Time

15

____

20

____

25

____

ns

t

EW

Chip Enable to End-of-Write

(3)

12

____

15

____

20

____

ns

t

AW

Address Valid to End-of-Write

12

____

15

____

20

____

ns

t

AS

Address Set-up Time

(3)

0

____

0

____

0

____

ns

t

WP

Write Pulse Width

12

____

15

____

20

____

ns

t

WR

Write Recovery Time

0

____

0

____

0

____

ns

t

DW

Data Valid to End-of-Write

10

____

15

____

15

____

ns

t

HZ

Output High-Z Time

(1,2)

____

10

____

12

____

15

ns

t

DH

Data Hold Time

(4)

0

____

0

____

0

____

ns

t

WZ

Write Enable to Output in High-Z

(1,2)

____

10

____

12

____

15

ns

t

OW

Output Active from End-of-Write

(1,2,4)

0

____

0

____

0

____

ns

t

SWRD

SEM Flag  Write to Read Time

5

____

5

____

5

____

ns

t

SPS

SEM Flag Contention Window

5

____

5

____

5

____

ns

2911   tbl 12a

Symbol

Parameter

70V24X35

Com'l

& Ind

70V24X55

Com'l

& Ind

Unit

Min.

Max.

Min.

Max.

WRITE CYCLE

t

WC

Write Cycle Time

35

____

55

____

ns

t

EW

Chip Enable to End-of-Write

(3)

30

____

45

____

ns

t

AW

Address Valid to End-of-Write

30

____

45

____

ns

t

AS

Address Set-up Time

(3)

0

____

0

____

ns

t

WP

Write Pulse Width

25

____

40

____

ns

t

WR

Write Recovery Time

0

____

0

____

ns

t

DW

Data Valid to End-of-Write

15

____

30

____

ns

t

HZ

Output High-Z Time

(1,2)

____

15

____

25

ns

t

DH

Data Hold Time

(4)

0

____

0

____

ns

t

WZ

Write Enable to Output in High-Z

(1,2)

____

15

____

25

ns

t

OW

Output Active from End-of-Write

(1,2,4)

0

____

0

____

ns

t

SWRD

SEM Flag  Write to Read Time

5

____

5

____

ns

t

SPS

SEM Flag Contention Window

5

____

5

____

ns

2911 tbl 12b

background image

           6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

11

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

(1,5,8)

NOTES:

1. R/

W or CE or UB & LB must be high during all address transitions.

2. A write occurs during the overlap (t

EW

 or t

WP

) of a low 

UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.

3. t

WR

 is measured from the earlier of 

CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the 

CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

6. Timing depends on which enable signal is asserted last, 

CE, R/W or byte control.

7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output

Test Load (Figure 2).

8. If 

OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t

WP

 or (t

WZ

 + t

DW

) to allow the I/O drivers to turn off and data to be placed on the

bus for the required t

DW

. If 

OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t

WP

.

9. To access SRAM,  

CE = V

IL

UB or LB = V

IL

SEM = V

IH

. To access semaphore, 

CE = V

IH

 or 

UB and LB = V

IH

 and 

SEM = V

IL

. Either condition must be valid for

the entire t

EW

 time.

R/

W

t

WC

t

HZ

t

AW

t

WR

t

AS

t

WP

DATA

OUT

(2)

t

WZ

t

DW

t

DH

t

OW

OE

ADDRESS

DATA

IN

(6)

(4)

(4)

(7)

CE

or

SEM

2911 drw 08

(9)

CE

or

SEM

(9)

(7)

(3)

2911 drw 09

t

WC

t

AS

t

WR

t

DW

t

DH

ADDRESS

DATA

IN

R/

W

t

AW

t

EW

UB

or

LB

(3)

(2)

(6)

CE

or

SEM

(9)

(9)

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing

(1,5)

background image

     

      6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

12

Timing Waveform of Semaphore Read after Write Timing, Either Side

(1)

Timing Waveform of Semaphore Write Contention

(1,3,4)

NOTES:

1. D

0R

 = D

0L

 = V

IL

CE

R

 = 

CE

L

 = V

IH

, or Both 

UB & LB = V

IH

.

2. All timing is the same for left or right port. “A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/

W

"A"

 or 

SEM

"A"

 going HIGH to R/

W

"B"

 or 

SEM

"B"

 going HIGH.

4. If t

SPS

 is not satisfied there is no guarantee which side will be granted the semaphore flag.

NOTES:

1.

CE = V

IH

 or 

UB & LB = V

IH

 for the duration of the above timing (both write and read cycle).

2. “DATA

OUT

 VALID” represents all I/O's (I/O

0

-I/O

15

)equal to the semaphore value.

SEM

"A"

2911 drw 11

t

SPS

MATCH

R/W

"A"

MATCH

A

0"A"

-A

2"A"

SIDE

"A"

(2)

SEM

"B"

R/W

"B"

A

0"B"

-A

2"B"

SIDE

(2)

"B"

SEM

2911 drw 10

t

AW

t

EW

t

SOP

I/O

0

VALID ADDRESS

t

SAA

R/

W

t

WR

t

OH

t

ACE

VALID ADDRESS

DATA

IN

VALID

t

DW

t

WP

t

DH

t

AS

t

SWRD

t

AOE

Read Cycle

Write Cycle

A

0

-A

2

OE

DATA

OUT

VALID

(2)

background image

           6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

13

AC Electrical Characteristics Over the

Operating Oemperature and Supply Voltage Range

(6)

NOTES:

1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With 

BUSY (M/S = V

IH

)" or "Timing Waveform of Write

With Port-To-Port Delay (M/

S = V

IL

)".

2. To ensure that the earlier of the two ports wins.

3. t

BDD

 is a calculated parameter and is the greater of 0ns, t

WDD

 – t

WP

 (actual) or t

DDD

 – t

DW

 (actual).

4. To ensure that the write cycle is inhibited during contention.

5. To ensure that a write cycle is completed after contention.

6. 'X' in part number indicates power rating (S or L).

70V24X15

Com'l Ony

70V24X20

Com'l

& Ind

70V24X25

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = V

IH

)

t

BAA

BUSY Access Time from Address Match

____

15

____

20

____

20

ns

t

BDA

BUSY Disable Time from Address Not Matched

____

15

____

20

____

20

ns

t

BAC

BUSY Access Time from Chip Enable LOW

____

15

____

20

____

20

ns

t

BDC

BUSY Disable Time from Chip Enable HIGH

____

15

____

17

____

17

ns

t

APS

Arbitration Priority Set-up Time

(2)

5

____

5

____

5

____

ns

t

BDD

BUSY Disable to Valid Data

(3)

____

18

____

30

____

30

ns

t

WH

Write Hold After 

BUSY

(5)

12

____

15

____

17

____

ns

BUSY TIMING (M/S = V

IL

)

t

WB

BUSY Input to Write

(4)

0

____

0

____

0

____

ns

t

WH

Write Hold After 

BUSY

(5)

12

____

15

____

17

____

ns

PORT-TO-PORT DELAY TIMING

t

WDD

Write  Pulse to Data Delay

(1)

____

30

____

45

____

50

ns

t

DDD

Write Data Valid  to Read Data Delay

(1)

____

25

____

35

____

35

ns

2911 tbl 13a

70V24X35

Com'l

& Ind

70V24X55

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = V

IH

)

t

BAA

BUSY Access Time from Address Match

____

20

____

45

ns

t

BDA

BUSY Disable Time from Address Not Matched

____

20

____

40

ns

t

BAC

BUSY Access Time from Chip Enable LOW

____

20

____

40

ns

t

BDC

BUSY Disable Time from Chip Enable HIGH

____

20

____

35

ns

t

APS

Arbitration Priority Set-up Time

(2)

5

____

5

____

ns

t

BDD

BUSY Disable to Valid Data

(3)

____

35

____

40

ns

t

WH

Write Hold After 

BUSY

(5)

25

____

25

____

ns

BUSY TIMING (M/S = V

IL

)

t

WB

BUSY Input to Write

(4)

0

____

0

____

ns

t

WH

Write Hold After 

BUSY

(5)

25

____

25

____

ns

PORT-TO-PORT DELAY TIMING

t

WDD

Write  Pulse to Data Delay

(1)

____

60

____

80

ns

t

DDD

Write Data Valid  to Read Data Delay

(1)

____

45

____

65

ns

2911 tbl 13b

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14

2911 drw 12

t

DW

t

APS

ADDR

"A"

t

WC

DATA

OUT "B"

MATCH

t

WP

R/

W

"A"

DATA

IN "A"

ADDR

"B"

t

DH

VALID

(1)

MATCH

BUSY

"B"

t

BDA

VALID

t

BDD

t

DDD

(3)

t

WDD

t

BAA

Timing Waveform of Read with BUSY

(2,4,5)

 

(M/S = V

IH

)

NOTES:

1. To ensure that the earlier of the two ports wins. t

APS

 is ignored for M/

S = V

IL

 (slave).

2.

CE

L

 = 

CE

R

 = V

IL

.

3.

OE =  V

IL

 for the reading port.

4. If M/

S = V

IL 

(slave), 

BUSY is an input. Then for this example BUSY

"A"

 = V

IH

 and 

BUSY

"B"

 input is shown above.

5.   All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".

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15

Timing Waveform of Slave Write (M/S = V

IL

)

2911 drw 13

R/

W

"A"

BUSY

"B"

t

WP

t

WB

(3)

R/

W

"B"

t

WH

(1)

(2)

NOTES:

1.

t

WH

 must be met for both 

BUSY input (slave) and output (master).

2.

Busy is asserted on port "B" blocking R/

W

"B"

, until 

BUSY

"B"

 goes HIGH.

3.

t

WB

 is only for the “slave” version.

Waveform of BUSY Arbitration Controlled by CE Timing

(1)

 

(M/S = V

IH

)

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing

(1) 

(M/S = V

IH

)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If t

APS

 is not satisfied, the 

BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

2911 drw 14

ADDR

"A"

and

"B"

ADDRESSES MATCH

CE

"A"

CE

"B"

BUSY

"B"

t

APS

t

BAC

t

BDC

(2)

2911 drw 15

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

t

APS

t

BAA

t

BDA

(2)

MATCHING ADDRESS "N"

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16

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

(1)

NOTES:

1. 'X' in part number indicates power rating (S or L).

70V24X15

Com'l Only

70V24X20

Com'l

& Ind

70V24X25

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

t

AS

Address Set-up Time

0

____

0

____

0

____

ns

t

WR

Write Recovery Time

0

____

0

____

0

____

ns

t

INS

Interrupt Set Time

____

15

____

20

____

20

ns

t

INR

Interrupt Reset Time

____

15

____

20

____

20

ns

2911 tbl 14a

70V24X35

Com'l

& Ind

70V24X55

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

t

AS

Address Set-up Time

0

____

0

____

ns

t

WR

Write Recovery Time

0

____

0

____

ns

t

INS

Interrupt Set Time

____

25

____

40

ns

t

INR

Interrupt Reset Time

____

25

____

40

ns

2911 tbl 14b

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17

Waveform of Interrupt Timing

(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (

CE or R/W) is asserted last.

4. Timing depends on which enable signal (

CE or R/W) is de-asserted first.

2911 drw 16

ADDR

"A"

INTERRUPT SET ADDRESS

CE

"A"

R/

W

"A"

t

AS

t

WC

t

WR

(3)

(4)

t

INS

(3)

INT

"B"

(2)

2911 drw 17

ADDR

"B"

INTERRUPT CLEAR ADDRESS

CE

"B"

OE

"B"

t

AS

t

RC

(3)

t

INR

(3)

INT

"B"

(2)

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18

Truth Table IV — Address BUSY

Arbitration

NOTES:

1.

Pins 

BUSY

L

 and 

BUSY

R

 are both outputs when the part is configured as a master.  Both are inputs when configured as a slave. 

BUSY outputs on the IDT70V24 are push

pull, not open drain outputs. On slaves the 

BUSY input internally inhibits writes.

2.

L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. V

IH

 if the inputs to the opposite port became stable after the address and

enable inputs of this port. If t

APS

 is not met, either 

BUSY

L

 or 

BUSY

R

 = LOW will result. 

BUSY

L

 and 

BUSY

R

 outputs cannot be LOW simultaneously.

3.

Writes to the left port are internally ignored when 

BUSY

L

 outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when

BUSY

R

 outputs are driving LOW regardless of actual logic level on the pin.

Truth Table V — Example of Semaphore Procurement Sequence

(1,2,3)

NOTES:

1.

This table denotes a sequence of events for only one of the eight semaphores on the IDT70V24.

2.

There are eight semaphore flags written to via I/O

0

 and read from all I/O's (I/O

0

-I/O

15

). These eight semaphores are addressed by A

0

-A

2

.

3.

CE = V

IH

SEM = V

IL

 to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Truth Table III — Interrupt Flag

(1)

NOTES:

1.

Assumes 

BUSY

L

 = 

BUSY

R

 = V

IH

.

2.

If 

BUSY

L

 = V

IL

, then no change.

3.

If 

BUSY

R

 = V

IL

, then no change.

Left Port

Right Port

Function

R/

W

L

CE

L

OE

L

A

11L

-A

0L

INT

L

R/

W

R

CE

R

OE

R

A

11R

-A

0R

INT

R

L

L

X

FFF

X

X

X

X

X

 

 

L

(2)

Set Right 

INT

R

 Flag

X

X

X

X

X

X

L

L

FFF

 

 

H

(3)

Reset Right 

INT

R

 Flag

X

X

X

X

 

 

L

(3)

L

L

X

FFE

X

Set  Left 

INT

L

 Flag

X

L

L

FFE

 

 

H

(2)

X

X

X

X

X

Reset Left 

INT

L

 Flag

2911 tbl 15

Inputs

Outputs

Function

CE

L

CE

R

A

0L

-A

11L

A

0R

-A

11R

BUSY

L

(1)

BUSY

R

(1)

X

X

NO  MATCH

H

H

Normal

H

X

MATCH

H

H

Normal

X

H

MATCH

H

H

Normal

L

L

MATCH

(2)

(2)

Write Inhibit

(3)

2911 tbl 16

Functions

D

0

 - D

15

 Left

D

0

 - D

15

 Right

Status

No Action

1

1

Semaphore free

Left Port Writes "0" to Semaphore

 0

1

Left port has semaphore token

Right Port Writes "0" to Semaphore

 0

1

No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore

1

 0

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

1

 0

No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore

 0

1

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

Right Port Writes "0" to Semaphore

1

 0

Right port has semaphore token

Right Port Writes "1" to Semaphore

1

1

Semaphore free

Left Port Writes "0" to Semaphore

 0

1

Left port has semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

2911 tbl  17

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19

Figure 3.  Busy and chip enable routing for both width and depth expansion with IDT70V24 SRAMs.

prevented to a port by tying the 

BUSY pin for that port LOW.

The busy outputs on the IDT 70V24 SRAM in master mode, are push-

pull type outputs and do not require pull up resistors to operate. If these

RAMs are being expanded in depth, then the 

BUSY indication for the

resulting array requires the use of an external AND gate.

Width Expansion with BUSY Logic

Master/Slave Arrays

When expanding an IDT70V24 SRAM array in width while using busy

logic, one master part is used to decide which side of the SRAM array will

receive a 

BUSY indication, and to output that indication. Any number of

slaves to be addressed in the same address range as the master, use the

BUSY signal as a write inhibit signal. Thus on the IDT70V24 SRAM the

BUSY pin is an output if the part is used as a master (M/S pin = V

IH

), and

the 

BUSY pin is an input if the part used as a slave (M/S pin = V

IL

) as  shown

in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating 

BUSY on one side

of the array and another master indicating 

BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for the

other part of the word.

The 

BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a 

BUSY flag to be output from the master before the

actual write pulse can be initiated with either the R/

W signal or the byte

enables. Failure to observe this timing can result in a glitched internal

write inhibit signal and corrupted data in the slave.

Semaphores

The IDT70V24 is an extremely fast Dual-Port 4K x 16 CMOS Static

RAM with an additional 8 address locations dedicated to binary

semaphore flags. These flags allow either processor on the left or right

side of the Dual-Port SRAM to claim a privilege over the other

processor for functions defined by the system designer’s software. As

an example, the semaphore can be used by one processor to inhibit

the other from accessing a portion of the Dual-Port SRAM or any other

shared resource.

2911 drw 18

MASTER

Dual Port

SRAM

BUSY

L

BUSY

R

CE

MASTER

Dual Port

SRAM

BUSY

L

BUSY

R

CE

SLAVE

Dual Port

SRAM

BUSY

L

BUSY

R

CE

SLAVE

Dual Port

SRAM

BUSY

L

BUSY

R

CE

BUSY

L

BUSY

R

D

E

C

O

D

E

R

Functional Description

The IDT70V24 provides two ports with separate control, address

and I/O pins that permit independent access to any location in memory.

The IDT70V24 has an automatic power down feature controlled by 

CE.

The 

CE controls on-chip power down circuitry that permits the respec-

tive port to go into a standby mode when not selected (

CE HIGH).

When a port is enabled, access to the entire memory array is

permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port.  The left port interrupt

flag (

INT

L

) is asserted when the right port writes to memory location

FFE (HEX), where a write is defined as the 

CE=R/W=V

IL

 per Truth

Table III. The left port clears the interrupt by accessing address

location FFE when 

CE

OE

= V

IL

, R/

W is a "don't care". Likewise,

the right port interrupt flag (

INT

R

) is asserted when the left port writes

to memory location FFF (HEX) and to clear the interrupt flag (

INT

R

),

the right port must read the memory location FFF. The message (16

bits) at FFE or FFF is user-defined, since it is an addressable SRAM

location. If the interrupt function is not used, address locations FFE and

FFF are not used as mail boxes, but as part of the random access

memory. Refer to Truth Table IIII for the interrupt operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

SRAM have accessed the same location at the same time. It also

allows one of the two accesses to proceed and signals the other side

that the SRAM is “busy”. The 

BUSY pin can then be used to stall the access

until the operation on  the other side is completed. If a write operation has

been attemp-ted from the side that receives a 

BUSY indication, the write

signal is gated internally to prevent the write from proceeding.

The use of 

BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the 

BUSY outputs together

and use any 

BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of 

BUSY logic is

not desirable, the 

BUSY logic can be disabled by placing the part in slave

mode with the M/

S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying

the 

BUSY pins HIGH. If desired, unintended write operations can be

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IDT70V24S/L

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20

The Dual-Port SRAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be accessed

to, at the same time with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphore location. Semaphores are protected against such ambiguous

situations and may be used by the system program to avoid any conflicts

in the non-semaphore portion of the Dual-Port SRAM. These devices

have an automatic power-down feature controlled by 

CE, the Dual-Port

SRAM enable, and 

SEM, the semaphore enable. The CE and SEM pins

control on-chip power down circuitry that permits the respective port to go

into standby mode when not selected. This is the condition which is shown

in Truth Table I where 

CE and SEM are both HIGH.

Systems which can best use the IDT70V24 contain multiple processors

or controllers and are typically very high-speed systems which are

software controlled or software intensive. These systems can benefit from

a performance increase offered by the IDT70V24's hardware sema-

phores, which provide a lockout mechanism without requiring complex

programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70V24 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port SRAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that shared

resource is in use. If the left processor wants to use this resource, it

requests the token by setting the latch. This processor then verifies its

success in setting the latch by reading it. If it was successful, it

proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side

processor has set the latch first,  has the token and is using the shared

resource. The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

The eight semaphore flags reside within the IDT70V24 in a

separate memory space from the Dual-Port SRAM. This address

space is accessed by placing a LOW input on the 

SEM pin (which acts as

a chip select for the semaphore flags) and using the other control pins

(Address, 

OE, and R/W) as they would be used in accessing a standard

Static RAM. Each of the flags has a unique address which can be accessed

by either side through address pins A

0

 – A

2

.  When accessing the

semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D

0

 is used. If a LOW level

is written into an unused semaphore location, that flag will be set to a zero

on that side and a one on the other side (see Truth Table V). That

semaphore can now only be modified by the side showing the zero. When

a one is written into the same location from the same side, the flag will be

set to a one for both sides (unless a semaphore request from the other side

is pending) and then can be written to by both sides. The fact that the side

which is able to write a zero into a semaphore subsequently locks out writes

from the other side is what makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this feature follows

shortly.) A zero written into the same location from the other side will be

stored in the semaphore request latch for that side until the semaphore is

freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing

a zero reads as all zeros. The read value is latched into one side’s output

register when that side's semaphore select (

SEM) and output enable (OE)

signals go active. This serves to disallow the semaphore from changing

state in the middle of a read cycle due to a write cycle from the other side.

Because of this latch, a repeated read of a semaphore in a test loop must

cause either signal (

SEM or OE) to go inactive or the output will never

change.

A sequence WRITE/READ must be used by the semaphore in

order to guarantee that no system level contention will occur. A

processor requests access to shared resources by attempting to write

a zero into a semaphore location. If the semaphore is already in use,

the semaphore request latch will contain a zero, yet the semaphore

flag will appear as one, a fact which the processor will verify by the

subsequent read (see Truth Table V). As an example, assume a

processor writes a zero to the left port at a free semaphore location. On

a subsequent read, the processor will verify that it has written success-

fully to that location and will assume control over the resource in

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

fact that a one will be read from that semaphore on the right side during

subsequent read.  Had a sequence of READ/WRITE been used

instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the  semaphore flag will force its side of the

semaphore flag LOW and the other side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

Should the other side’s semaphore request latch have been written to

a zero in the meantime, the semaphore flag will flip over to the other

side as soon as a one is written into the first side’s request latch. The second

side’s flag will now stay LOW until its semaphore request latch is written to

a one. From this it is easy to understand that, if a semaphore is requested

and the processor which requested it no longer needs the resource, the

entire system can hang up until a one is written into that semaphore request

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High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

21

latch.

The critical case of semaphore timing is when both sides request

a single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneous requests are made, the logic guarantees that only one

side receives the token. If one side is earlier than the other in making

the request, the first side to make the request will receive the token. If

both requests arrive at the same time, the assignment will be arbitrarily

made to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is

secure. As with any powerful programming technique, if semaphores

are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be

handled via the initialization program at power-up. Since any sema-

phore request flag which contains a zero must be reset to a one, all

semaphores on both sides should have a one written into them at

initialization from both sides to assure that they will be free when

needed.

Using Semaphores—Some Examples

Perhaps the simplest application of semaphores is their applica-

tion as resource markers for the IDT70V24’s Dual-Port SRAM.  Say the

4K x 16 SRAM was to be divided into two 2K x 16 blocks which were to

be dedicated at any one time to servicing either the left or right port.

Semaphore 0 could be used to indicate the side which would control

the lower section of memory, and Semaphore 1 could be defined as the

indicator for the upper section of memory.

To take a resource, in this example the lower 2K of Dual-Port

SRAM, the processor on the left port could write and then read a

zero in to Semaphore 0. If this task were successfully completed

(a zero was read back rather than a one), the left processor would

assume control of the lower 2K. Meanwhile the right processor was

attempting to gain control of the  resource after the left processor, it would

read back a one in response to the zero it had attempted to write into

Semaphore 0. At this point, the software could choose to try and gain control

of the second 2K section by writing, then reading a zero into Semaphore

1. If it succeeded in gaining control, it would lock out the left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could undo

its semaphore request and perform other tasks until it was able to write, then

read a zero into Semaphore 1. If the right processor performs a similar task

with Semaphore 0, this protocol would allow the two processors to swap

2K blocks of Dual-Port SRAM with each other.

The blocks do not have to be any particular size and can even be

variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the

Dual-Port SRAM or other shared resources into eight parts. Sema-

phores can even be assigned different meanings on different sides

rather than being given a common meaning as was shown in the

example above.

Semaphores are a useful form of arbitration in systems like disk

interfaces where the CPU must be locked out of a section of memory

during a transfer and the I/O device cannot tolerate any wait states.

With the use of semaphores, once the two devices has determined

which memory area was “off-limits” to the CPU, both the CPU and the

I/O devices could access their assigned portions of memory continu-

ously without any wait states.

Semaphores are also useful in applications where no memory

“WAIT” state is available on one or both sides. Once a semaphore

handshake has been performed, both processors can access their

assigned SRAM segments at full speed.

Another application is in the area of complex data structures. In this

case, block arbitration is very important. For this application one

processor may be responsible for building and updating a data

structure. The other processor then reads and interprets that data

structure. If the interpreting processor reads an incomplete data

structure, a major error condition may exist. Therefore, some sort of

arbitration must be used between the two different processors. The

building processor arbitrates for the block, locks it and then is able to

go in and update the data structure. When the update is completed, the

data structure block is released. This allows the interpreting processor

to come back and read the complete data structure, thereby guaran-

teeing a consistent data structure.

D

2911 drw 19

0

D

Q

WRITE

D

0

D

Q

WRITE

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

L PORT

R PORT

SEMAPHORE

READ

SEMAPHORE

READ

,

Figure 4.  IDT70V24 Semaphore Logic

background image

     

      6.42

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM                                       Industrial and Commercial Temperature Ranges

22

Ordering Information

2911 drw 20

A

Power

999

Speed

A

Package

A

Process/

Temperature

Range

Blank

I

Commercial (0

°

C to +70

°

C)

Industrial (-40

°

C to +85

°

C)

PF

G

J

100-pin TQFP (PN100-1)

84-pin PGA (G84-3)

84-pin PLCC (J84-1)

15

20

25

35

55

S

L

Standard Power

Low Power

XXXXX

Device

Type

64K (4K x 16) 3.3V Dual-Port RAM

70V24

IDT

Speed in nanoseconds

Commercial Only

Commercial & Industrial

Commercial & Industrial

Commercial & Industrial

Commercial & Industrial

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975 Stender Way

800-345-7015 or 408-727-6116

831-754-4613

Santa Clara, CA 95054

fax: 408-492-8674

DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

3/8/99:

Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Pages 2 and 3 Added additional notes to pin configurations

6/10/99:

Changed drawing format

8/1/99:

Page 2 TQFP for corrected pinout (no pin 55 was shown)

8/30/99:

Page 1 Changed 660mW to 660

µ

W

11/12/99:

Replaced IDT logo

3/10/00:

Added 15 and 20ns speed grades

Upgraded DC parameters

Added Industrial Temperature information

Changed ±200 mV to 0mV in notes