background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

256Mb E-die SDRAM Specification

Revision 1.3

September. 2003

* Samsung Electronics reserves the right to change products or specification without notice. 

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

Revision History

Revision 1.0 (May. 2003)

- First release.

Revision 1.1 (June. 2003)

- Correct Typo

Revision 1.2 (June. 2003)

- Added 166MHz speed bin in x16

Revision 1.3 (September. 2003)

- Corrected typo in ordering information.

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

Part No.

Orgainization

Max Freq.

Interface

Package

K4S560432E-TC(L)75

64M x 4  

133MHz

LVTTL

54pin TSOP

K4S560832E-TC(L)75

32M x 8 

133MHz

LVTTL

54pin TSOP

K4S561632E-TC(L)60/75

16M x 16

166MHz

LVTTL

54pin TSOP

  The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x

16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchro-

nous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of oper-

ating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high

bandwidth, high performance memory system applications.

•  JEDEC standard 3.3V power supply 

•  LVTTL compatible with multiplexed address

•  Four banks operation 

•  MRS cycle with address key programs

     -. CAS latency (2 & 3)

     -. Burst length (1, 2, 4, 8 & Full page)

     -. Burst type (Sequential & Interleave)

•  All inputs are sampled at the positive going edge of the system clock.  

•  Burst read single-bit write operation

•  DQM (x4,x8) & L(U)DQM (x16) for masking

•  Auto & self refresh

•  64ms refresh period (8K Cycle)

GENERAL DESCRIPTION

FEATURES

16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM

Ordering Information

 Row & Column address configuration

Organization

Row Address

Column Address

64Mx4

A0~A12

A0-A9, A11

32Mx8

A0~A12

A0-A9

16Mx16

A0~A12

A0-A8

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

 

11

.7

6

±

0.2

0

0.46

3

±

0.0

0

8

0.002

0.05

MIN

0.008

0.21

± 

0.002

± 

0.05

0

.020

0.

5

0

     

     

  

)

0.005

-0.001

+0.003

0.125

-0.035

+0.075

0.40

0

10.1

6

0.4

5

~0.7

5

0.

018~

0.03

0

0.010

0.25

TYP

0~8

°

C

#54

#28

#1

#27

0.004

0.10

MAX

0.028

0.71

(         )

0.012

 0.30

 

0.0315

0.80

0.047

1.20

MAX

0.039

1.00

± 

0.004

± 

0.10

0.891

22.62

MAX

0.875

22.22

± 

0.004

± 

0.10

+0.10

-0.05

+

0.004

-0.002

54Pin TSOP Package Dimension

Package Physical Dimension

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SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

FUNCTIONAL BLOCK DIAGRAM

Bank Select

Data Input Register

16M x 4 / 8M x 8 / 4M x 16

16M x 4 / 8M x 8 / 4M x 16

Sense AMP

Output Buf

fer

I/O

 Control

Column Decoder

Latency & Burst Length

Programming Register

Addr

ess Register

Row Buf

fer

Refresh Counter

Row Decoder

Col. Buf

fer

LRAS

LCBR

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

CS

RAS

CAS

WE

L(U)DQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

16M x 4 / 8M x 8 / 4M x 16

16M x 4 / 8M x 8 / 4M x 16

Timing Register

* Samsung Electronics reserves the right to change products or specification without notice. 

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

PIN CONFIGURATION   (Top view)

V

DD

N.C

V

DDQ

N.C

DQ0

V

SSQ

N.C

N.C

V

DDQ

N.C

DQ1

V

SSQ

N.C

V

DD

N.C

WE

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

V

SS

N.C

V

SSQ

N.C

DQ3

V

DDQ

N.C

N.C

V

SSQ

N.C

DQ2

V

DDQ

N.C

V

SS

N.C/RFU

DQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

V

SS

54Pin TSOP

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

CS

Chip select

Disables or enables device operation by masking or enabling all inputs except 

CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A

0

 ~ A

12

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA

0

 ~ RA

12

Column address : (x4 : CA

0

 ~ CA

9

,CA

11

),

    

(x8 : CA

0

 ~ CA

9

),

    

(x16 : CA

0

 ~ CA

8

)

BA

0

 ~ BA

1

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE

Write enable

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM

Data input/output mask

Makes data output Hi-Z, t

SHZ

 after the clock and masks the output.

Blocks data input when DQM active.

DQ

0

 ~ 

N

Data input/output

Data inputs/outputs are multiplexed on the same pins.

(x4 : DQ

0

 ~ 

3

),    (x8 : DQ

0

 ~ 

7

),    (x16 : DQ

0

 ~ 

15

)

V

DD

/V

SS

Power supply/ground

Power and ground for the input buffers and the core logic.

V

DDQ

/V

SSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise 

immunity.

N.C/RFU

No connection

/reserved for future use

This pin is recommended to be left No Connection on the device.

V

DD

DQ0

V

DDQ

N.C

DQ1

V

SSQ

N.C

DQ2

V

DDQ

N.C

DQ3

V

SSQ

N.C

V

DD

N.C

WE

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

V

SS

DQ7

V

SSQ

N.C

DQ6

V

DDQ

N.C

DQ5

V

SSQ

N.C

DQ4

V

DDQ

N.C

V

SS

N.C/RFU

DQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

V

SS

V

DD

DQ0

V

DDQ

DQ1

DQ2

V

SSQ

DQ3

DQ4

V

DDQ

DQ5

DQ6

V

SSQ

DQ7

V

DD

LDQM

WE

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

V

SS

DQ15

V

SSQ

DQ14

DQ13

V

DDQ

DQ12

DQ11

V

SSQ

DQ10

DQ9

V

DDQ

DQ8

V

SS

N.C/RFU

UDQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

V

SS

x16

x8

x4

x16

x8

x4

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

ABSOLUTE MAXIMUM RATINGS

                       Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

V

IN

, V

OUT

-1.0 ~ 4.6

V

Voltage on V

DD

 supply relative to Vss

V

DD

, V

DDQ

-1.0 ~ 4.6

V

Storage temperature

T

STG

-55 ~ +150

°

C

Power dissipation

P

D

1

W

Short circuit current

I

OS

50

mA

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 

Note :

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

SS

 = 0V, T

A

 = 0 to 70

°

C)

 

              Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

V

DD

, V

DDQ

3.0

3.3

3.6

V

Input logic high voltage

V

IH

2.0

3.0

V

DD

+0.3

V

1

Input logic low voltage

V

IL

-0.3

0

0.8

V

2

Output logic high voltage

V

OH

2.4

-

-

V

I

OH

 = -2mA

Output logic low voltage

V

OL

-

-

0.4

V

I

OL

 = 2mA

Input leakage current 

I

LI

-10

-

10

uA

3

1. V

IH

 (max) = 5.6V AC. The overshoot voltage duration is 

 3ns.

2. V

IL

 (min) = -2.0V AC. The undershoot voltage duration is 

 3ns.

3. Any input 0V 

 V

IN 

 V

DDQ

.

    Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

CAPACITANCE  

(V

DD

 = 3.3V, T

A

 = 23

°

C, f = 1MHz, V

REF

 =1.4V

 ± 

200

 

mV)

Pin

Symbol

Min

Max

Unit

Note

Clock

C

CLK

2.5

3.5

pF

RAS, CAS, WE, CS, CKE, DQM

C

IN

2.5

3.8

pF

Address

C

ADD

2.5

3.8

pF

(x4 : DQ

0

 ~ DQ

3

), (x8 : DQ

0

 ~ DQ

7

), (x16 : DQ

0

 ~ DQ

15

) C

OUT

4.0

6.0

pF

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

(Recommended operating condition unless otherwise noted, T

A

 = 0 to 70

°

C)

 

Parameter

Symbol

Test Condition

Version

Unit

Note

-75

Operating current

(One bank active)

I

CC1

 Burst length = 1

 t

RC 

≥ 

t

RC

(min)

 I

O

 = 0 mA

80

mA

1

Precharge standby current in 

power-down mode

I

CC2

P

CKE 

≤ 

V

IL

(max), t

CC

 = 10ns

2

mA

I

CC2

PS

CKE & CLK 

≤ 

V

IL

(max), t

CC

 = 

2

Precharge standby current in 

non power-down mode

I

CC2

N

CKE 

≥ 

V

IH

(min), CS 

≥ 

V

IH

(min), t

CC

 = 10ns

Input signals are changed one time during 20ns

20

mA

I

CC2

NS

CKE 

≥ 

V

IH

(min), CLK 

≤ 

V

IL

(max), t

CC

 = 

Input signals are stable

10

Active standby current in 

power-down mode

I

CC3

P

CKE 

≤ 

V

IL

(max), t

CC

 = 10ns

6

mA

I

CC3

PS

CKE & CLK 

≤ 

V

IL

(max), t

CC

 = 

6

Active standby current in 

non power-down mode

(One bank active)

I

CC3

N

CKE 

≥ 

V

IH

(min), CS 

≥ 

V

IH

(min), t

CC

 = 10ns

Input signals are changed one time during 20ns

25

mA

I

CC3

NS

CKE 

≥ 

V

IH

(min), CLK 

≤ 

V

IL

(max), t

CC

 = 

Input signals are stable

25

mA

Operating current

(Burst mode)

I

CC4

 I

O

 = 0 mA 

 Page burst

4banks  Activated.

t

CCD

 = 2CLKs

100

mA

1

Refresh current

I

CC5

t

RC 

≥ 

t

RC

(min)

180

mA

2

Self refresh current

I

CC6

CKE 

≤ 

0.2V

C

3

mA

3

L

1.5

mA

4

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S5604(08)32E-TC

4. K4S5604(08)32E-TL

5. Unless otherwise noticed, input swing level is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ

).

Notes :

DC CHARACTERISTICS (x4, x8)

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

SDRAM 256Mb E-die (x4, x8, x16)

SDRAM 256Mb E-die (x4, x8, x16)

(Recommended operating condition unless otherwise noted, T

A

 = 0 to 70

°

C)

 

Parameter

Symbol

Test Condition

Version

Unit Note

-60

-75

Operating current

(One bank active)

I

CC1

Burst length = 1

t

RC

 ≥

 t

RC

(min)

I

O

 = 0 mA

140

90

mA

1

Precharge standby current in 

power-down mode

I

CC2

P

CKE

 ≤

 V

IL

(max), t

CC

 = 10ns

2

mA

I

CC2

PS

CKE & CLK

 ≤

 V

IL

(max), t

CC

 = 

 ∞

2

Precharge standby current in 

non power-down mode

I

CC2

N

CKE

 ≥

 V

IH

(min), CS

 ≥

 V

IH

(min), t

CC

 = 10ns

Input signals are changed one time during 20ns

20

mA

I

CC2

NS

CKE

 ≥

 V

IH

(min), CLK

 ≤

 V

IL

(max), t

CC

 =

 ∞

Input signals are stable

10

Active standby current in 

power-down mode

I

CC3

P

CKE

 ≤

 V

IL

(max), t

CC

 = 10ns

6

mA

I

CC3

PS

CKE & CLK

 ≤

 V

IL

(max), t

CC

 =

 ∞

6

Active standby current in 

non power-down mode

(One bank active)

I

CC3

N

CKE

 ≥

 V

IH

(min), CS

 ≥

 V

IH

(min), t

CC

 = 10ns

Input signals are changed one time during 20ns

25

mA

I

CC3

NS

CKE

 ≥

 V

IH

(min), CLK

 ≤

 V

IL

(max), t

CC

 =

 ∞

Input signals are stable

25

mA

Operating current

(Burst mode)

I

CC4

I

O

 = 0 mA

Page burst

4banks  Activated.

t

CCD

 = 2CLKs

170

130

mA

1

Refresh current

I

CC5

t

RC

 ≥

 t

RC

(min)

200

180

mA

2

Self refresh current

I

CC6

CKE

 ≤

 0.2V

      C

3

mA

3

      L

1.5

mA

4

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S561632E-TC

4. K4S561632E-TL

5. Unless otherwise noticed, input swing level is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ

).

Notes :

DC CHARACTERISTICS (x16)

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

AC OPERATING TEST CONDITIONS 

(V

DD

 = 3.3V 

± 

0.3V, T

A

 = 0 to 70

°

C)

                             Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall time

tr/tf = 1/1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig. 2

3.3V

1200

870

Output

50pF

V

OH 

(DC) = 2.4V, I

OH

 = -2mA

V

OL 

(DC) = 0.4V, I

OL

 = 2mA

Vtt = 1.4V

50

Output

50pF

Z0 = 50

 

(Fig. 2) AC output load circuit 

(Fig. 1) DC output load circuit 

OPERATING AC PARAMETER 

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-60

-75

Row active to row active delay

t

RRD

(min)

12

15

ns

1

RAS to CAS delay

t

RCD

(min)

18

20

ns

1

Row precharge time

t

RP

(min)

18

20

ns

1

Row active time

t

RAS

(min)

42

45

ns

1

t

RAS

(max)

100

us

Row cycle time

t

RC

(min)

60

65

ns

1

Last data in to row precharge

t

RDL

(min)

2

CLK

2, 5

Last data in to Active delay

t

DAL

(min)

2 CLK + tRP

-

5

Last data in to new col. address delay

t

CDL

(min)

1

CLK

2

Last data in to burst stop

t

BDL

(min)

1

CLK

2

Col. address to col. address delay

t

CCD

(min)

1

CLK

3

Number of valid  output data

CAS latency=3

2

ea

4

CAS latency=2

-

1

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time 

    and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz  operating conditions,  tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

   SAMSUNG recommends  tRDL=2CLK and tDAL=2CLK + tRP.

Notes :

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Notes

     Output rise time

trh

   Measure in linear

   region : 1.2V ~ 1.8V

1.37

4.37

Volts/ns

3

     Output fall time

tfh

   Measure in linear

   region : 1.2V ~ 1.8V

1.30

3.8

Volts/ns

3

     Output rise time

trh

   Measure in linear

   region : 1.2V ~ 1.8V

2.8

3.9

5.6

Volts/ns

1,2

     Output fall time

tfh

   Measure in linear

   region : 1.2V ~ 1.8V

2.0

2.9

5.0

Volts/ns

1,2

1. Rise time specification based on 0pF + 50 

 to V

SS

, use these values to design to.

2. Fall time specification based on 0pF + 50 

 to V

DD

, use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to V

SS

.

Notes :

AC CHARACTERISTICS 

(AC operating conditions unless otherwise noted)

Parameter

Symbol

-60

-75

Unit

Note

Min

Max

Min

Max

CLK cycle time

CAS latency=3

t

CC

6

1000

7.5

1000

ns

1

CAS latency=2

-

10

CLK to valid

output delay

CAS latency=3

t

SAC

5

5.4

ns

1,2

CAS latency=2

-

6

Output data

hold time

CAS latency=3

t

OH

2.5

3

ns

2

CAS latency=2

-

3

CLK high pulse width

t

CH

2.5

2.5

ns

3

CLK low pulse width

t

CL

2.5

2.5

ns

3

Input setup time

t

SS

1.5

1.5

ns

3

Input hold time

t

SH

1

0.8

ns

3

CLK to output in Low-Z

t

SLZ

1

1

ns

2

CLK to output  in Hi-Z

CAS latency=3

t

SHZ

5

5.4

ns

CAS latency=2

-

6

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

    If tr & tf is longer than 1ns, transient time compensation should be considered,

    i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

I

OH

 Characteristics (Pull-up)

Voltage

100MHz

133MHz

Min

100MHz

133MHz

Max

66MHz

Min

(V)

I (mA)

I (mA)

I (mA)

  3.45

    -2.4

3.3

  -27.3

3.0

   0.0

  -74.1

  -0.7

2.6

-21.1

-129.2

  -7.5

2.4

-34.1

-153.3

-13.3

2.0

-58.7

-197.0

-27.5

1.8

-67.3

-226.2

-35.5

  1.65

-73.0

-248.0

-41.1

1.5

-77.9

-269.7

-47.9

1.4

-80.8

-284.3

-52.4

1.0

-88.6

-344.5

-72.5

0.0

-93.0

-502.4

-93.0

IBIS SPECIFICATION

I

OL

 Characteristics (Pull-down)

Voltage

100MHz

133MHz

Min

100MHz

133MHz

Max

66MHz

Min

(V)

I (mA)

I (mA)

I (mA)

0.0

  0.0

    0.0

  0.0

0.4

27.5

  70.2

17.7

  0.65

41.8

107.5

26.9

  0.85

51.6

133.8

33.3

1.0

58.0

151.2

37.6

1.4

70.7

187.7

46.6

1.5

72.9

194.4

48.0

  1.65

75.4

202.5

49.5

1.8

77.0

208.6

50.7

  1.95

77.6

212.0

51.5

3.0

80.3

219.6

54.2

  3.45

81.4

222.6

54.9

0

-100

-200

-300

-400

-500

-600

0

3

0.5

1

1.5

2

2.5

3.5

Voltage

mA

250

200

150

100

50

0

0

3

0.5

1

1.5

2

2.5

3.5

Voltage

mA

66MHz and 100MHz/133MHz Pull-up

66MHz and 100MHz/133MHz Pull-down

I

OH

 Min (100MHz)

I

OH

 Max (66 and 100MHz)

I

OH

 Min (66MHz)

I

OL

 Min (100MHz)

I

OL

 Max (100MHz)

I

OL

 Min (66MHz)

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

V

DD

 Clamp @ CLK, CKE, CS, DQM & DQ

V

DD 

(V)

I (mA)

0.0

0.0

0.2

0.0

0.4

0.0

0.6

0.0

0.7

0.0

0.8

0.0

0.9

0.0

1.0

  0.23

1.2

  1.34

1.4

  3.02

1.6

  5.06

1.8

  7.35

2.0

  9.83

2.2

12.48

2.4

15.30

2.6

18.31

V

SS

 Clamp @ CLK, CKE, CS, DQM & DQ

V

SS 

(V)

I (mA)

-2.6

-57.23

-2.4

-45.77

-2.2

-38.26

-2.0

-31.22

-1.8

-24.58

-1.6

-18.37

-1.4

-12.56

-1.2

  -7.57

-1.0

  -3.37

-0.9

  -1.75

-0.8

  -0.58

-0.7

  -0.05

-0.6

 0.0

-0.4

 0.0

-0.2

 0.0

 0.0

 0.0

20

15

10

5

0

0

3

1

2

Voltage

mA

I (mA)

Voltage

mA

I (mA)

Minimum V

DD

 clamp current

(Referenced to V

DD

)

Minimum V

SS

 clamp current

0

-10

-20

-30

-40

-3

0

-2

-1

-50

-60

background image

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

 Rev. 1.3 September. 2003

SDRAM 256Mb E-die (x4, x8, x16)

SIMPLIFIED TRUTH TABLE

                                                                              (V=Valid, X=Don't care, H=Logic high, L=Logic low)

Command

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

BA

0,1

A

10

/AP

A

~ A

9

 A

11, 

A

12

Note

Register

Mode register set

H

X

L

L

L

L

X

OP code

1,2

Refresh

Auto refresh

H

H

L

L

L

H

X

X

3

Self 

refresh

Entry

L

3

Exit

L

H

L

H

H

H

X

X

3

H

X

X

X

3

Bank active & row addr.

H

X

L

L

H

H

X

V

Row address

Read &

column address

Auto precharge disable

H

X

L

H

L

H

X

V

L

Column

address

4

Auto precharge enable

H

4,5

Write &

column address

Auto precharge disable

H

X

L

H

L

L

X

V

L

Column

address

4

Auto precharge enable

H

4,5

Burst stop

H

X

L

H

H

L

X

X

6

Precharge

Bank selection

H

X

L

L

H

L

X

V

L

X

All banks

X

H

Clock suspend or

active power down

Entry

H

L

H

X

X

X

X

X

L

V

V

V

Exit

L

H

X

X

X

X

X

Precharge power down mode

Entry

H

L

H

X

X

X

X

X

L

H

H

H

Exit

L

H

H

X

X

X

X

L

V

V

V

DQM

H

X

V

X

7

No operation command

H

X

H

X

X

X

X

X

L

H

H

H

Notes : 1. OP Code  : Operand code

    A

0

 ~ A

12 

& BA

0

 ~ BA

1

 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

    A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

    The automatical precharge without row precharge command is meant by "Auto".

    Auto/self refresh can be issued only at all banks precharge state.

4. BA

0

 ~ BA

1

 : Bank select addresses.

    If both BA

0

 and BA

are "Low" at read, write, row active and precharge, bank A is selected.

    If BA

0

 is "High" and BA

is "Low" at read, write, row active and precharge, bank B is selected.

    If BA

0

 is "Low" and BA

is "High" at read, write, row active and precharge, bank C is selected.

    If both BA

0

 and BA

are "High" at read, write, row active and precharge, bank D is selected.

    If A

10

/AP is "High" at row precharge, BA

0

 and  BA

1

 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

    Another bank read/write command can be issued after the end of burst.

    New row active of the associated bank can be issued at t

RP

 after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks  the data-in at the very CLK (Write DQM latency is 0),

    but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)