background image

M48Z02

M48Z12

16 Kbit (2Kb x 8) ZEROPOWER

®

 SRAM

May 1999

1/12

INTEGRATED ULTRA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and

BATTERY

UNLIMITED WRITE CYCLES 

READ CYCLE TIME EQUALS WRITE CYCLE

TIME

AUTOMATIC POWER-FAIL CHIP DESELECT and

WRITE PROTECTION

WRITE PROTECT VOLTAGES 

(V

PFD

 = Power-fail Deselect Voltage):

– M48Z02: 4.50V 

  V

PFD 

≤ 

 4.75V

– M48Z12: 4.20V 

  V

PFD 

≤ 

 4.50V

SELF-CONTAINED BATTERY in the CAPHAT

DIP PACKAGE

PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 2K x 8 SRAMs

DESCRIPTION

The M48Z02/12 ZEROPOWER

®

 RAM is a 2K x 8

non-volatile static RAM which is pin and functional

compatible with the DS1220. 

A special 24 pin 600mil DIP CAPHAT

 package

houses the M48Z02/12 silicon with a long life lith-

ium button cell to form a highly integrated battery

backed-up memory solution.

The M48Z02/12 button cell has sufficient capacity

and storage life to maintain data and clock function-

ality for an accumulated time period of at least 10

years in the absence of power over the operating

temperature range.

AI01186

11

A0-A10

W

DQ0-DQ7

VCC

M48Z02

M48Z12

G

VSS

8

E

Figure 1.  Logic Diagram

A0-A10

Address Inputs

DQ0-DQ7

Data Inputs / Outputs

E

Chip Enable 

G

Output Enable

W

Write Enable

V

CC

Supply Voltage

V

SS

Ground

Table 1.  Signal Names

24

1

PCDIP24  (PC)

Battery CAPHAT

background image

Symbol

Parameter

Value

Unit

T

A

Ambient Operating Temperature

–40 to 85         

°

C

T

STG

Storage Temperature (V

CC

 Off)

–40 to 85         

°

C

T

SLD

 (2)

Lead Solder Temperature for 10 seconds

260

°

C

V

IO

Input or Output Voltages

–0.3 to 7       

V

V

CC

Supply Voltage

–0.3 to 7       

V

I

O

Output Current

20

mA

P

D

Power Dissipation

1

W

Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational 

section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may 

affect reliability.

2. Soldering temperature not to exceed 260

°

C for 10 seconds (total thermal budget not to exceed 150

°

C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.

Table 2.  Absolute Maximum Ratings 

(1)

Mode

V

CC

E

G

W

DQ0-DQ7

Power

Deselect

4.75V to 5.5V

or

4.5V to 5.5V

V

IH

X

X

High Z

Standby

Write

V

IL

X

V

IL

D

IN

Active

Read

V

IL

V

IL

V

IH

D

OUT

Active

Read

V

IL

V

IH

V

IH

High Z

Active

Deselect

V

SO

 to V

PFD

 (min)

X

X

X

High Z

CMOS Standby

Deselect

 V

SO

X

X

X

High Z

Battery Back-up Mode

Notes: X = V

IH

 or V

IL

; V

SO

 = Battery Back-up Switchover Voltage.

Table 3.  Operating Modes

A1

A0

DQ0

A7

A4

A3

A2

A6

A5

A10

A8

A9

DQ7

W

G

E

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

VCC

AI01187

M48Z02

M48Z12

8

1

2

3

4

5

6

7

9

10

11

12

16

15

24

23

22

21

20

19

18

17

14

13

Figure 2.  DIP Pin Connections

The M48Z02/12 is a non-volatile pin and function

equivalent to any JEDEC standard 2K x 8 SRAM.

It also easily fits into many ROM, EPROM, and

EEPROM sockets, providing the non-volatility of

PROMs without any requirement for special write

timing or limitations on the number of writes that

can be performed.

The M48Z02/12 also has its own Power-fail Detect

circuit. The control circuitry constantly monitors the

single 5V supply for an out of tolerance condition.

When V

CC

 is out of tolerance, the circuit write

protects the SRAM, providing a high degree of data

security in the midst of unpredictable system op-

eration brought on by low V

CC

. As V

CC

 falls below

approximately 3V, the control circuitry connects the

battery which maintains data and clock operation

until valid power returns.

DESCRIPTION (cont’d)

2/12

M48Z02, M48Z12

background image

AI01019

5V

OUT

CL = 100pF

CL includes JIG capacitance        

1.8k

DEVICE

UNDER

TEST

1k

Figure 4.  AC Testing Load Circuit 

Input Rise and Fall Times

 5ns

Input Pulse Voltages

0V to 3V

Input and Output Timing Ref. Voltages

1.5V

Note that Output Hi-Z is defined as the point where data is no

longer driven.

Table 4. AC Measurement Conditions

AI01255

LITHIUM

CELL

VPFD

VCC

VSS

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

2K x 8

SRAM ARRAY

A0-A10

DQ0-DQ7

E

W

G

POWER

Figure 3.  Block Diagram

READ MODE

The M48Z02/12 is in the Read Mode whenever W

(Write Enable) is high and E (Chip Enable) is low.

The device architecture allows ripple-through ac-

cess of data from eight of 16,384 locations in the

static storage array. Thus, the unique address

specified by the 11 Address Inputs defines which

one of the 2,048 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

within Address Access time (t

AVQV

) after the last

address input signal is stable, providing that the E

and G access times are also satisfied. If the E and

G access times are not met, valid data will be

available after the latter of the Chip Enable Access

time (t

ELQV

) or Output Enable Access time (t

GLQV

).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activated

before t

AVQV

, the data lines will be driven to an

indeterminate state until t

AVQV

. If the Address In-

puts are changed while E and G remain active,

output data will remain valid for Output Data Hold

time (t

AXQX

) but will go indeterminate until the next

Address Access.

3/12

M48Z02, M48Z12

background image

Symbol

Parameter

Test Condition

Min

Max

Unit

I

LI

 (1)

Input Leakage Current

0V 

 V

IN

 

 V

CC

±

1

µ

A

I

LO

 (1)

Output Leakage Current

0V 

 V

OUT

 

 V

CC

±

5

µ

A

I

CC

 

Supply Current

Outputs open

80

mA

I

CC1

 

Supply Current (Standby) TTL

E = V

IH

3

mA

I

CC2

 

Supply Current (Standby) CMOS

E = V

CC

 – 0.2V

3

mA

V

IL

 

(2)

Input Low Voltage

–0.3

0.8

V

V

IH

Input High Voltage

2.2

V

CC

 + 0.3

V

V

OL

Output Low Voltage

I

OL

 = 2.1mA

0.4

V

V

OH

Output High Voltage

I

OH

 = –1mA

2.4

V

Notes: 1. Outputs Deselected.

2. Negative spikes of –1V allowed for up to 10ns once per cycle.

Table 6.  DC Characteristics  

(T

A

 = 0 to 70

°

C or –40 to 85

°

C; V

CC

 = 4.75V to 5.5V or 4.5V to 5.5V)

Symbol

Parameter

Test Condition

Min

Max

Unit

C

IN

Input Capacitance

V

IN

 = 0V

10

pF

C

IO 

(2)

Input / Output Capacitance

V

OUT

 = 0V

10

pF

Notes: 1. Effective capacitance measured with power supply at 5V.

2. Outputs deselected

Table 5.  Capacitance 

(1) 

 

(T

A

 = 25 

°

C)

Symbol

Parameter

Min

Typ

Max

Unit

V

PFD

Power-fail Deselect Voltage (M48Z02)

4.5

4.6

4.75

V

V

PFD

Power-fail Deselect Voltage (M48Z12)

4.2

4.3

4.5

V

V

SO

Battery Back-up Switchover Voltage

3.0

V

t

DR

Expected Data Retention Time

10

YEARS

Note: 1. All voltages referenced to V

SS

.

Table 7.  Power Down/Up Trip Points DC Characteristics 

(1)

 

(T

A

 = 0 to 70

°

C or –40 to 85

°

C)

4/12

M48Z02, M48Z12

background image

Symbol

Parameter

Min

Max

Unit

t

PD

E or W at V

IH

 before Power Down

0

µ

s

t

(1)

V

PFD

 (max) to V

PFD

 (min) V

CC

 Fall Time

300

µ

s

t

FB

 (2)

V

PFD

 (min) to V

SO

 V

CC

 Fall Time

10

µ

s

t

R

V

PFD

(min) to V

PFD

 (max) V

CC

 Rise Time

0

µ

s

t

RB

V

SO

 to V

PFD

 (min) V

CC

 Rise Time

1

µ

s

t

REC

E or W at V

IH

 after Power Up

2

ms

Notes: 1. V

PFD

 (max) to V

PFD

 (min) fall time of less than t

F

 may result in deselection/write protection not occurring  until 50 

µ

s after 

V

CC

 passes V

PFD

 (min).

2. V

PFD

 (min) to V

SO

 fall time of less than t

FB

 may cause corruption of RAM data.

Table 8.  Power Down/Up Mode AC Characteristics 

(T

A

 = 0 to 70

°

C or –40 to 85

°

C)

AI00606

VCC

INPUTS

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tF

tFB

tR

tREC

tPD

tRB

tDR

VALID

VALID

NOTE

(PER CONTROL INPUT)

RECOGNIZED

RECOGNIZED

VPFD (max)

VPFD (min)

VSO 

Figure 5.  Power Down/Up Mode AC Waveforms

Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E

 

high as V

CC

 rises past V

PFD

(min). Some systems

may perform inadvertent write cycles after V

CC

 rises above V

PFD

(min) but before normal system  operations begin. Even though a power on

reset is being applied to the processor, a reset condition may not occur until after the system clock is running.

5/12

M48Z02, M48Z12

background image

Symbol

Parameter

M48Z02 / M48Z12

Unit

-70

-150

-200

Min

Max

Min

Max

Min

Max

t

AVAV

Read Cycle Time

70

150

200

ns

t

AVQV

Address Valid to Output Valid

70

150

200

ns

t

ELQV

Chip Enable Low to Output Valid

70

150

200

ns

t

GLQV

Output Enable Low to Output Valid

35

75

80

ns

t

ELQX

Chip Enable Low to Output Transition

5

10

10

ns

t

GLQX

Output Enable Low to Output Transition

5

5

5

ns

t

EHQZ

Chip Enable High to Output Hi-Z

25

35

40

ns

t

GHQZ

Output Enable High to Output Hi-Z

25

35

40

ns

t

AXQX

Address Transition to Output Transition

10

5

5

ns

Table 9. Read Mode AC Characteristics  

(T

A

 = 0 to 70

°

C or –40 to 85

°

C; V

CC

 = 4.75V to 5.5V or 4.5V to 5.5V)

AI01330

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A10

E

G

DQ0-DQ7

VALID

Figure 6.  Read Mode AC Waveforms

Note: Write Enable (W) = High.

6/12

M48Z02, M48Z12

background image

Symbol

Parameter

M48Z02 / M48Z12

Unit

-70

-150

-200

Min

Max

Min

Max

Min

Max

t

AVAV

Write Cycle Time

70

150

200

ns

t

AVWL

Address Valid to Write Enable Low

0

0

0

ns

t

AVEL

Address Valid to Chip Enable Low

0

0

0

ns

t

WLWH

Write Enable Pulse Width

50

90

120

ns

t

ELEH

Chip Enable Low to Chip Enable High

55

90

120

ns

t

WHAX

Write Enable High to Address Transition

0

10

10

ns

t

EHAX

Chip Enable High to Address Transition

0

10

10

ns

t

DVWH

Input Valid to Write Enable High

30

40

60

ns

t

DVEH

Input Valid to Chip Enable High

30

40

60

ns

t

WHDX

Write Enable High to Input Transition

5

5

5

ns

t

EHDX

Chip Enable High to Input Transition

5

5

5

ns

t

WLQZ

Write Enable Low to Output Hi-Z

25

50

60

ns

t

AVWH

Address Valid to Write Enable High

60

120

140

ns

t

AVEH

Address Valid to Chip Enable High

60

120

140

ns

t

WHQX

Write Enable High to Output Transition

5

10

10

ns

Table 10. Write Mode AC Characteristics  

(T

A

 = 0 to 70

°

C or –40 to 85

°

C; V

CC

 = 4.75V to 5.5V or 4.5V to 5.5V)

WRITE MODE

The M48Z02/12 is in the Write Mode whenever W

and E are active. The start of a write is referenced

from the latter occurring falling edge of W or E. A

write is terminated by the earlier rising edge of W

or E. The addresses must be held valid throughout

the cycle. E or W must return high for a minimum

of t

EHAX

 from Chip Enable or t

WHAX

 from Write

Enable prior to the initiation of another read or write

cycle.  Data-in must be valid t

DVWH

 prior to the end

of write and remain valid for t

WHDX

 afterward. G

should be kept high during write cycles to avoid bus

contention; although, if the output bus has been

activated by a low on E and G, a low on W will

disable the outputs t

WLQZ

 after W falls.

7/12

M48Z02, M48Z12

background image

AI01331

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A10

E

W

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

Figure 7.  Write Enable Controlled, Write AC Waveforms

AI01332B

tAVAV

tEHAX

tDVEH

A0-A10

E

W

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

Figure 8. Chip Enable Controlled, Write AC Waveforms

8/12

M48Z02, M48Z12

background image

DATA RETENTION MODE

With valid V

CC

 applied, the M48Z02/12 operates as

a conventional BYTEWIDE

 static RAM. Should

the supply voltage decay, the RAM will automat-

ically power-fail deselect, write protecting itself

when V

CC

 falls within the V

PFD

(max), V

PFD

(min)

window. All outputs become high impedance, and

all inputs are treated as "don’t care."

Note: A power failure during a write cycle may

corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM’s

content. At voltages below V

PFD

(min), the user can

be assured the memory will be in a write protected

state, provided the V

CC

 fall time is not less than t

F

.

The M48Z02/12 may respond to transient noise

spikes on V

CC

 that reach into the deselect window

during the time the device is sampling V

CC

. There-

fore, decoupling of the power supply lines is rec-

ommended.

The power switching circuit connects external V

CC

to the RAM and disconnects the battery when V

CC

rises above V

SO

. As V

CC

 rises, the battery voltage

is checked. If the voltage is too low, an internal

Battery Not OK (BOK) flag will be set. The BOK flag

can be checked after power up. If the BOK flag is

set, the first write attempted will be blocked. The

flag is automatically cleared after the first write, and

normal RAM operation resumes. Figure 9 illus-

trates how a BOK check routine could be struc-

tured.

POWER SUPPLY DECOUPLING and UNDER-

SHOOT PROTECTION

I

CC

 transients, including those produced by output

switching, can produce voltage fluctuations, result-

ing in spikes on the V

CC

 bus. These transients can

be reduced if capacitors are used to store energy,

which stabilizes the V

CC

 bus. The energy stored in

the bypass capacitors will be released as low going

spikes are generated or energy will be absorbed

when overshoots occur. A ceramic bypass capaci-

tor value of 0.1

µ

F (as shown in Figure 10) is

recommended in order to provide the needed filter-

ing.

In addition to transients that are caused by normal

SRAM operation, power cycling can generate

negative voltage spikes on V

CC

 that drive it to

values below V

SS

 by as much as one Volt. These

negative spikes can cause data corruption in the

SRAM while in battery backup mode. To protect

from these voltage spikes, it is recommeded to

connect a schottky diode from V

CC

 to V

SS

 (cathode

connected to V

CC

, anode to V

SS

). Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

READ DATA

AT ANY ADDRESS

AI00607

IS DATA

COMPLEMENT

OF FIRST

READ?

(BATTERY OK)

POWER-UP

YES

NO

WRITE DATA

COMPLEMENT BACK

TO SAME ADDRESS

READ DATA

AT SAME 

ADDRESS AGAIN

NOTIFY SYSTEM

OF LOW BATTERY

(DATA MAY BE

CORRUPTED) 

WRITE ORIGINAL

DATA BACK TO

SAME ADDRESS

(BATTERY LOW)

CONTINUE

Figure 9. Checking the BOK Flag Status

AI02169

VCC

0.1

µ

F

DEVICE

VCC

VSS

Figure 10.  Supply Voltage Protection

9/12

M48Z02, M48Z12

background image

ORDERING INFORMATION SCHEME

Supply Voltage and Write

Protect Voltage

02

V

CC

 = 4.75V to 5.5V

V

PFD

 = 4.5V to 4.75V

12

V

CC

 = 4.5V to 5.5V

V

PFD

 = 4.2V to 4.5V

Speed

-70

70ns

-150

150ns

-200

200ns

Package

PC

PCDIP24

Temp. Range

1

0 to 70 

°

C

6

–40 to 85 

°

C

Example:                     M48Z02         -70    PC    1  

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,

please contact the STMicroelectronics Sales Office nearest to you.

10/12

M48Z02, M48Z12

background image

PCDIP

A2

A1

A

L

B1

B

e1

D

E

N

1

C

eA

e3

Symb

mm

inches

Typ

Min

Max

Typ

Min

Max

A

8.89

9.65

0.350

0.380

A1

0.38

0.76

0.015

0.030

A2

8.38

8.89

0.330

0.350

B

0.38

0.53

0.015

0.021

B1

1.14

1.78

0.045

0.070

C

0.20

0.31

0.008

0.012

D

34.29

34.80

1.350

1.370

E

17.83

18.34

0.702

0.722

e1

2.29

2.79

0.090

0.110

e3

25.15

30.73

0.990

1.210

eA

15.24

16.00

0.600

0.630

L

3.05

3.81

0.120

0.150

N

24

24

Drawing is not to scale.

PCDIP24 - 24 pin Plastic DIP, battery CAPHAT

11/12

M48Z02, M48Z12

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