background image

Philips Semiconductors

Product specification

 TrenchMOS

 transistor

BUK7508-55

 Standard level FET

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel

enhancement

mode

SYMBOL

PARAMETER

MAX.

UNIT

standard level field-effect power

transistor in a plastic envelope using

V

DS

Drain-source voltage

55

V

trench’ technology. The device

I

D

Drain current (DC)

75

A

features very low on-state resistance

P

tot

Total power dissipation

187

W

and has integral zener diodes giving

T

j

Junction temperature

175

˚C

ESD protection up to 2kV. It is

R

DS(ON)

Drain-source on-state

8

m

intended for use in automotive and

resistance

V

GS

 = 10 V

general

purpose

switching

applications.

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

tab

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

-

55

V

V

DGR

Drain-gate voltage

R

GS

 = 20 k

-

55

V

±

V

GS

Gate-source voltage

-

-

16

V

I

D

Drain current (DC)

T

mb

 = 25 ˚C

-

75

A

I

D

Drain current (DC)

T

mb

 = 100 ˚C

-

65

A

I

DM

Drain current (pulse peak value)

T

mb

 = 25 ˚C

-

240

A

P

tot

Total power dissipation

T

mb

 = 25 ˚C

-

187

W

T

stg

, T

j

Storage & operating temperature

-

- 55

175

˚C

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

C

Electrostatic discharge capacitor

Human body  model

-

2

kV

voltage, all pins

(100 pF, 1.5 k

)

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R

th j-mb

Thermal resistance junction to

-

-

0.8

K/W

mounting base

R

th j-a

Thermal resistance junction to

in free air

60

-

K/W

ambient

d

g

s

1 2 3

tab

February 1997

1

Rev 1.000

background image

Philips Semiconductors

Product specification

 TrenchMOS

 transistor

BUK7508-55

 Standard level FET

STATIC CHARACTERISTICS

T

j

= 25˚C  unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V

(BR)DSS

Drain-source breakdown

V

GS

 = 0 V; I

D

 = 0.25 mA;

55

-

-

V

voltage

T

j

 = -55˚C

50

-

-

V

V

GS(TO)

Gate threshold voltage

V

DS

 = V

GS

; I

D

 = 1 mA

2

3.0

4.0

V

 T

j

 = 175˚C

1

-

-

V

T

j

 = -55˚C

-

-

4.4

V

I

DSS

Zero gate voltage drain current

V

DS

 = 55 V; V

GS

 = 0 V;

-

0.05

10

µ

A

 T

j

 = 175˚C

-

-

500

µ

A

I

GSS

Gate source leakage current

V

GS

 = 

±

10 V; V

DS

 = 0 V

-

0.02

1

µ

A

 T

j

 = 175˚C

-

-

20

µ

A

±

V

(BR)GSS

Gate-source breakdown

I

G

 = 

±

1 mA;

16

-

-

V

voltage

R

DS(ON)

Drain-source on-state

V

GS

 = 10 V; I

D

 = 25 A

-

6.5

8

m

resistance

T

j

 = 175˚C

-

-

17

m

DYNAMIC CHARACTERISTICS

T

mb

 = 25˚C unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

g

fs

Forward transconductance

V

DS

 = 25 V; I

D

 = 25 A

10

45

-

S

C

iss

Input capacitance

V

GS

 = 0 V; V

DS

 = 25 V; f = 1 MHz

-

3600

4500

pF

C

oss

Output capacitance

-

830

1000

pF

C

rss

Feedback capacitance

-

320

440

pF

t

d on

Turn-on delay time

V

DD

 = 30 V; I

D

 = 25 A;

-

27

40

ns

t

r

Turn-on rise time

V

GS

 = 10 V; R

G

 = 10 

-

70

105

ns

t

d off

Turn-off delay time

Resistive load

-

100

140

ns

t

f

Turn-off fall time

-

50

70

ns

L

d

Internal drain inductance

Measured from contact screw on

-

3.5

-

nH

tab to centre of die

L

d

Internal drain inductance

Measured from drain lead 6 mm

-

4.5

-

nH

from package to centre of die

L

s

Internal source inductance

Measured from source lead 6 mm

-

7.5

-

nH

from package to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T

j

 = 25˚C unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I

DR

Continuous reverse drain

-

-

75

A

current

I

DRM

Pulsed reverse drain current

-

-

240

A

V

SD

Diode forward voltage

I

F

 = 25 A; V

GS

 = 0 V

-

0.85

1.2

V

I

F

 = 75 A; V

GS

 = 0 V

-

1.0

-

V

t

rr

Reverse recovery time

I

F

 = 75 A; -dI

F

/dt = 100 A/

µ

s;

-

65

-

ns

Q

rr

Reverse recovery charge

V

GS

 = -10 V; V

R

 = 30 V

-

0.18

-

µ

C

February 1997

2

Rev 1.000

background image

Philips Semiconductors

Product specification

 TrenchMOS

 transistor

BUK7508-55

 Standard level FET

AVALANCHE LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

W

DSS

Drain-source non-repetitive

I

D

 = 75 A; V

DD

 

 25 V;

-

-

500

mJ

unclamped inductive turn-off

V

GS

 = 10 V; R

GS

 = 50 

; T

mb

 = 25 ˚C

energy

Fig.1.   Normalised power dissipation.

PD% = 100

P

D

/P

D 25 ˚C 

= f(T

mb

)

Fig.2.   Normalised continuous drain current.

ID% = 100

I

D

/I

D 25 ˚C 

= f(T

mb

); conditions: V

GS

 

 5 V

Fig.3.   Safe operating area. T

mb

 = 25 ˚C

I

D

 & I

DM

 = f(V

DS

); I

DM

 single pulse; parameter t

p

Fig.4.  Transient thermal impedance.

Z

th j-mb

 = f(t); parameter D = t

p

/T

0

20

40

60

80

100

120

140

160

180

Tmb /   C

PD%

Normalised Power Derating

120 

110 

100 

90 

80 

70 

60 

50 

40 

30 

20 

10 

VDS / V

ID / A

100 us

1 ms

10 ms

100 ms

1

10

100

1000

1

10

RDS(ON) = VDS/ID 

DC 

100

BUKX508-55

tp = 10 us

0

20

40

60

80

100

120

140

160

180

Tmb /   C

ID%

Normalised Current Derating

120 

110 

100 

90 

80 

70 

60 

50 

40 

30 

20 

10 

1E-07

1E-05

1E-03

1E-01

1E+01

t / s

Zth / (K/W)

1E+00 

1E-01 

1E-02 

1E-03 

0

0.5

0.2

0.1

0.05

0.02

D = 

t

p

t

p

T

T

P

t

D

February 1997

3

Rev 1.000

background image

Philips Semiconductors

Product specification

 TrenchMOS

 transistor

BUK7508-55

 Standard level FET

Fig.5.  Typical output characteristics, T

j

 = 25 ˚C.

I

D

 = f(V

DS

); parameter V

GS

Fig.6.   Typical on-state resistance, T

j

 = 25 ˚C.

R

DS(ON)

 = f(I

D

); parameter V

GS

Fig.7.   Typical transfer characteristics.

I

D

 = f(V

GS

) ; conditions: V

DS

 = 25 V; parameter T

j

Fig.8.   Typical transconductance, T

j

 = 25 ˚C.

g

fs

 = f(I

D

); conditions: V

DS

 = 25 V

Fig.9.   Normalised drain-source on-state resistance.

a = R

DS(ON)

/R

DS(ON)25 ˚C 

= f(T

j

); I

D

 = 25 A; V

GS

 = 5 V

Fig.10.   Gate threshold voltage.

V

GS(TO)

 = f(T

j

); conditions: I

D

 = 1 mA; V

DS

 = V

GS

0

2

4

6

8

10

0

20

40

60

80

100

VGS/V =

6.0

5.5

5.0

4.5

4.0

6.5

16

10

ID/A

VDS/V

0

20

40

60

80

100

0

10

20

30

40

50

60

70

gfs/S

ID/A

0

20

40

60

80

100

120

0

5

10

15

RDS(ON)/mOhm

ID/A

10

8

7

6.5

6

5.5

BUK7508-55

VGS/V=

-100

-50

0

50

100

150

200

0.5

1

1.5

2

2.5

BUK959-60

Tmb / degC

Rds(on) normlised to 25degC

a

0

1

2

3

4

5

6

7

0

20

40

60

80

100

Tj/C = 175

25

ID/A

VGS/V

BUK759-60

-100

-50

0

50

100

150

200

0

1

2

3

4

5

Tj / C

VGS(TO) / V

max.

typ.

min.

February 1997

4

Rev 1.000

background image

Philips Semiconductors

Product specification

 TrenchMOS

 transistor

BUK7508-55

 Standard level FET

Fig.11.   Sub-threshold drain current.

I

D

 = f(V

GS)

; conditions: T

j

 = 25 ˚C; V

DS

 = V

GS

Fig.12.   Typical capacitances, C

iss

, C

oss

, C

rss

.

C = f(V

DS

); conditions: V

GS

 = 0 V; f = 1 MHz

Fig.13.  Typical turn-on gate-charge characteristics.

V

GS 

= f(Q

G

); conditions: I

D

 = 50 A; parameter V

DS

Fig.14.   Typical reverse diode current.

I

F

 = f(V

SDS

); conditions: V

GS 

= 0 V; parameter T

j

Fig.15.   Normalised avalanche energy rating.

W

DSS

% = f(T

mb

); conditions: I

D

 = 75 A

Fig.16.   Avalanche energy test circuit.

0

1

2

3

4

5

1E-06

1E-05

1E-04

1E-03

1E-02

1E-01

Sub-Threshold Conduction

typ

2%

98%

0

0.2

0.4

0.6

0.8

1

1.2

0

20

40

60

80

100

Tj/C =

175

25

IF/A

VSDS/V

0.01

0.1

1

10

100

0

1

2

3

4

5

6

7

Thousands pF

Ciss

Coss

Crss

VDS/V

20

40

60

80

100

120

140

160

180

Tmb /   C

120 

110 

100 

90 

80 

70 

60 

50 

40 

30 

20 

10 

WDSS%

0

10

20

30

40

50

60

70

80

90

100

0

2

4

6

8

10

12

VDS = 14V

VDS = 44V

VGS/V

QG/nC

BUK7508-55

L

T.U.T.

VDD

RGS

R 01

VDS

-ID/100

+

-

shunt

VGS

0

W

DSS

=

0.5

LI

D

2

BV

DSS

/(

BV

DSS

V

DD

)

February 1997

5

Rev 1.000

background image

Philips Semiconductors

Product specification

 TrenchMOS

 transistor

BUK7508-55

 Standard level FET

Fig.17.   Switching test circuit.

RD

T.U.T.

VDD

RG

VDS

+

-

VGS

0

February 1997

6

Rev 1.000

background image

Philips Semiconductors

Product specification

 TrenchMOS

 transistor

BUK7508-55

 Standard level FET

MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

Fig.18.  SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the  general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

10,3

max

3,7

2,8

3,0

3,0 max

not tinned

1,3

max

(2x)

1 2 3

2,4

0,6

4,5

max

5,9

min

15,8

max

1,3

2,54 2,54

0,9 max (3x)

13,5

min

February 1997

7

Rev 1.000

background image

Philips Semiconductors

Product specification

 TrenchMOS

 transistor

BUK7508-55

 Standard level FET

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134).  Stress above one

or more of the limiting values may cause permanent damage to the device.  These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied.  Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

©

 Philips Electronics N.V. 1998

All rights are reserved.  Reproduction in whole or in part is prohibited without the prior written consent of the

copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice.  No liability will be accepted by the publisher for any

consequence of its use.  Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury.  Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

February 1997

8

Rev 1.000