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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88512CA

512Kx8 Monolithic SRAM, SMD 5962-95600

FEATURES

Access Times of 15, 17, 20, 25, 35, 45, 55ns

Data Retention Function (LPA version)

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

Organized as 512Kx8

Commercial, Industrial and Military Temperature Ranges

32 lead JEDEC Approved Evolutionary Pinout

• Ceramic Sidebrazed 600 mil DIP (Package 9)

• Ceramic Sidebrazed 400 mil DIP (Package 326)

• Ceramic 32 pin Flatpack (Package 344)

• Ceramic Thin Flatpack (Package 321)

• Ceramic SOJ (Package 140)

36 lead JEDEC Approved Revolutionary Pinout

• Ceramic Flatpack (Package 316)

• Ceramic SOJ (Package 327)

• Ceramic LCC (Package 502)

Single +5V (±10%) Supply Operation

The EDI88512CA is a 4 megabit Monolithic CMOS

Static RAM.

The 32 pin DIP pinout adheres to the JEDEC evolu-

tionary standard for the four megabit device. All 32 pin

packages are pin for pin upgrades for the single chip

enable 128K x 8, the EDI88128CS. Pins 1 and 30 be-

come the higher order addresses.

The 36 pin revolutionary pinout also adheres to the

JEDEC standard for the four megabit device. The cen-

ter pin power and ground pins help to reduce noise in

high performance systems. The 36 pin pinout also

allows the user an upgrade path to the future 2Mx8.

A Low Power version with Data Retention

(EDI88512LPA) is also available for battery backed

applications. Military product is available compliant to

Appendix A of MIL-PRF-38535.

36 P

IN

T

OP

 V

IEW

P

IN

 D

ESCRIPTION

I/O

0-7

Data Inputs/Outputs

A

0-18

Address Inputs

WE

Write Enables

CS

Chip Selects

OE

Output Enable

V

CC

Power (+5V ±10%)

V

SS

Ground

NC

Not Connected

B

LOCK

 D

IAGRAM

Memory Array

Address

Buffer

Address

Decoder

I/O

Circuits

A

-18

I/O

-7

WE

CS

OE

FIG. 1    PIN CONFIGURATION

32 P

IN

T

OP

 V

IEW

32 

31 

30 

29

28 

27 

26 

25 

24 

23 

22 

21 

20

19 

18 

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

V

CC

 A15

 A17

 WE

 A13

 A8

 A9

 A11

 OE

 A10

 CS

 I/O7

 I/O6

 I/O5

 I/O4

 I/O3

A18

 A16

 A14

 A12

 A7

 A6

 A5

 A4

 A3

 A2

 A1

 A0

 I/O0

 I/O1

 I/O2

 V

SS

Aug. 2002  Rev. 9

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White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

EDI88512CA

A

BSOLUTE

 M

AXIMUM

 R

ATINGS

Parameter

Unit

Voltage on any pin relative to Vss

-0.5 to 7.0

V

Operating Temperature T

A

 (Ambient)

Commercial

0 to +70

°C

Industrial

-40 to +85

°C

Military

-55 to +125

°C

Storage Temperature, Plastic

-65 to +150

°C

Power Dissipation

1.5

W

Output Current

20

mA

Junction Temperature, T

J

175

°C

R

ECOMMENDED

 O

PERATING

 C

ONDITIONS

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

V

CC

4.5

5.0

5.5

V

Supply Voltage

V

SS

0

0

0

V

Input High Voltage

V

IH

2.2

3.0

V

Input Low Voltage

V

IL

-0.3

+0.8

V

Parameter

Symbol

Condition

Max Unit

Address Lines

C

I

V

IN

 = Vcc or Vss, f = 1.0MHz

12

pF

Data Lines

C

O

V

OUT

 = Vcc or Vss, f = 1.0MHz 14

pF

These parameters are sampled, not 100% tested.

C

APACITANCE

(T

A

 = +25°C)

T

RUTH

 T

ABLE

OE

CS

WE

Mode

Output

 Power

X

H

X

Standby

High Z

Icc

2

, Icc

3

H

L

H

Output Deselect

High Z

Icc

1

L

L

H

Read

Data Out

Icc

1

X

L

L

Write

Data In

Icc

1

NOTE:

Stress greater than those listed under "Absolute Maximum Ratings"

may cause permanent damage to the device.  This is a stress rating

only and functional operation of the device at these or any other

conditions greater than those indicated in the operational sections of

this specification is not implied.  Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

Input Pulse Levels

V

SS

 to 3.0V

Input Rise and Fall Times

5ns

Input and Output Timing Levels

1.5V

Output Load

Figure 1

NOTE:  For t

EHQZ

, t

GHQZ

  and t

WLQZ

, CL = 5pF Figure 2)

30pF

480

Vcc

Q

Figure 1

Figure 2

255

5pF

480

Vcc

Q

255

AC TEST CONDITIONS

Parameter

Symbol

                             Conditions

Units

Min

Max

Input Leakage Current

I

LI

V

IN

 = 0V to V

CC

-10

10

µA

Output Leakage Current

I

LO

V

I

/O

 = 0V to V

CC

-10

10

µA

Operating Power Supply Current

I

CC

1

WE, CS = V

IL

, I

I

/O

 = 0mA, Min Cycle         (17ns)

250

mA

                                                      (20 -55ns)

225

mA

Standby (TTL) Power Supply Current

I

CC

2

CS 

³ V

IH

, V

IN

 

£ V

IL

, V

IN

 

³ V

IH

60

mA

Full Standby Power Supply Current

I

CC

3

CS 

³ V

CC

 -0.2V                                   CA

25

mA

V

IN

 

³ Vcc -0.2V or V

IN

 

£ 0.2V               LPA

20

mA

Output Low Voltage

V

OL

I

OL

 = 8.0mA

0.4

V

Output High Voltage

V

OH

I

OH

 = -4.0mA

2.4

V

NOTE: DC test conditions: V

IL

 = 0.3V, V

IH

 = Vcc -0.3V

DC C

HARACTERISTICS

(V

CC

 

= 5V, T

A

 = -55°C 

TO

 +125°C)

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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88512CA

AC C

HARACTERISTICS

 – READ CYCLE

(V

CC

 

= 5.0V, V

SS

 = 0V, T

A

 

= -55°C 

TO

 +125°C)

          Symbol

       15ns          17ns         20ns         25ns        35ns       45ns        55ns

Parameter

JEDEC

Alt.

Min Max

Min Max

Min Max

Min Max Min Max Min Max Min Max Units

Read Cycle Time

t

AVAV

t

RC

15

17

20

25

35

45

55

ns

Address Access Time

t

AVQV

t

AA

15

17

20

25

35

45

55

ns

Chip Enable Access Time

t

ELQV

t

ACS

15

17

20

25

35

45

55

ns

Chip Enable to Output  in Low Z (1)

t

ELQX

t

CLZ

2

3

3

3

3

3

3

ns

Chip Disable to Output in High Z (1)

t

EHQZ

t

CHZ

0

7

0

7

0

8

0

10

0

15

0

20

0

20

ns

Output Hold from Address Change

t

AVQX

t

OH

0

0

0

0

0

0

0

ns

Output Enable to Output Valid

t

GLQV

t

OE

8

8

10

12

15

25

30

ns

Output Enable to Output in Low Z (1)

t

GLQX

t

OLZ

0

0

0

0

0

0

0

ns

Output Disable to Output in High Z(1)

t

GHQZ

t

OHZ

0

7

0

7

0

8

0

10

0

15

0

20

0

20

ns

1.  This parameter is guaranteed by design but not tested.

AC C

HARACTERISTICS

 – WRITE CYCLE

(V

CC

 

= 5.0V, V

SS

 = 0V, T

A

 

= -55°C 

TO

 +125°C)

          Symbol          15ns          17ns          20ns        25ns        35ns        45ns         55ns

Parameter

JEDEC

Alt.

Min Max Min

Max

Min Max Min Max Min Max Min Max Min Max Units

Write Cycle Time

t

AVAV

t

W C

15

17

20

25

35

45

55

ns

Chip Enable to End of Write

t

ELWH

t

C W

13

14

15

17

25

30

50

ns

t

ELEH

t

C W

13

14

15

17

25

30

50

ns

Address Setup Time

t

AVWL

t

AS

0

0

0

0

0

0

0

ns

t

AVEL

t

AS

0

0

0

0

0

0

0

ns

Address Valid to End of Write

t

AVWH

t

AW

13

14

15

17

25

30

50

ns

t

AVEH

t

AW

13

14

15

17

25

30

50

ns

Write Pulse Width

t

W LWH

t

W P

13

14

15

17

25

30

45

ns

t

WLEH

t

W P

13

14

15

17

25

30

45

ns

Write Recovery Time

t

WHAX

t

W R

0

0

0

0

0

0

0

ns

t

EHAX

t

W R

0

0

0

0

0

0

0

ns

Data Hold Time

t

WHDX

t

DH

0

0

0

0

0

0

0

ns

t

EHDX

t

DH

0

0

0

0

0

0

0

ns

Write to Output  in High Z (1)

t

WLQZ

t

WHZ

0

8

0

8

0

8

0

10

0

25

0

30

0

30

ns

Data to Write Time

t

DVWH

t

D W

8

8

10

12

20

25

40

ns

t

DVEH

t

D W

8

8

10

12

20

25

30

ns

Output Active from End of Write (1)

t

WHQX

t

WLZ

0

0

0

0

0

0

0

ns

1.  This parameter is guaranteed by design but not tested.

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White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

EDI88512CA

ADDRESS

DATA I/O

READ CYCLE 1  (WE HIGH; OE, CS LOW)

t

AVQX

t

AVQV

t

AVAV

DATA 2

ADDRESS 1

ADDRESS 2

DATA 1

ADDRESS

DATA OUT

READ CYCLE 2  (WE HIGH)

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

AVAV

t

EHQZ

t

GHQZ

OE

CS

WS32K32-XHX

FIG. 2   TIMING WAVEFORM - READ CYCLE

FIG. 4   WRITE CYCLE - CS CONTROLLED

FIG. 3   WRITE CYCLE - WE CONTROLLED

ADDRESS

DATA IN

WRITE CYCLE 2,  CS CONTROLLED

t

AVEH

t

ELEH

t

EHAX

t

WLEH

t

DVEH

t

EHDX

t

AVAV

DATA VALID

HIGH Z

WE

CS

DATA OUT

t

AVEL

ADDRESS

DATA IN

WRITE CYCLE 1,  WE CONTROLLED

t

AVWH

t

ELWH

t

WHAX

t

WLWH

t

DVWH

t

WLQZ

t

WHQX

t

AVWL

t

WHDX

t

AVAV

DATA VALID

HIGH Z

WE

CS

DATA OUT

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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88512CA

Characteristic

Sym

Conditions

Min

Typ

Max

Units

Low Power Version only

Data Retention Voltage

V

DD

V

DD

 = 2.0V

2

V

Data Retention Quiescent Current

I

CCDR

CS 

³ V

DD

 -0.2V

2

mA

Chip Disable to Data Retention Time

T

CDR

V

IN

 

³ V

DD

 -0.2V

0

ns

Operation Recovery Time

T

R

or V

IN

 

£ 0.2V

T

AVAV

ns

D

ATA

 R

ETENTION

 C

HARACTERISTICS

 (EDI88512LPA ONLY)

(T

A

 = -55°C 

TO

 +125°C)

WS32K32-XHX

FIG. 5   DATA RETENTION - CS CONTROLLED

DATA RETENTION MODE

CS = V

DD

 -0.2V 

V

CC

CS 

t

CDR

 

V

DD

 

4.5V 

4.5V 

t

R

 

DATA RETENTION, CS CONTROLLED

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White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

EDI88512CA

PACKAGE 9:   32 LEAD SIDEBRAZED CERAMIC DIP, SMD 5962-95600XXMXA

ALL DIMENSIONS ARE IN  INCHES

Pin 1 Indicator

0.020

0.016

0.200

0.125

0.100

TYP

15 x 0.100 = 1.500

0.155

0.115

1.616

1.584

0.061

0.017

0.600

 NOM

0.060

0.040

0.620

 0.600

PACKAGE 326:   32 LEAD SIDEBRAZED CERAMIC DIP

Pin 1 Indicator

0.020

0.016

0.200

0.125

0.100

TYP

15 x 0.100 = 1.500

0.155

0.115

0.420

0.400

1.616

1.584

0.061

0.017

0.400

 NOM

1

1

PACKAGE 140:   32 LEAD CERAMIC SOJ, SMD 5962-95600XXMUA

0.050

TYP

0.444

0.430

0.840

0.820

0.155

0.106

0.379

0.010

0.006

0.019

0.015

ALL DIMENSIONS ARE IN  INCHES

ALL DIMENSIONS ARE IN  INCHES

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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88512CA

PACKAGE 316:   36 PIN CERAMIC FLATPACK, SMD 5962-95600XXMTA

Pin 1

0.019

0.015

0.040

0.030

0.395

0.385

0.125

0.100

0.050

TYP

0.515

0.505

1.00 REF

0.045

0.020

0.007

0.003

0.920 – 0.010

0.370

0.250

PACKAGE 321:   32 PIN THINPACK™ FLATPACK, SMD 5962-95600XXMYA

PACKAGE 344:   32 PIN CERAMIC FLATPACK, SMD 5962-95600XXM9A

0.050

TYP

0.016 ± 0.008 

0.118

MAX.

0.020

0.030

0.008

0.005

0.427

0.429

0.838

MAX

0.567

0.559

ALL DIMENSIONS ARE IN  INCHES

ALL DIMENSIONS ARE IN  INCHES

ALL DIMENSIONS ARE IN  INCHES

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White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

EDI88512CA

PACKAGE 327:   36 LEAD CERAMIC SOJ, SMD 5962-95600XXMMA

0.050 

TYP 

0.444

0.434

0.920

0.940

0.155

0.106

0.379

0.010

0.006

0.019

0.015 

 

PACKAGE 502:  36 LEAD CERAMIC LCC, SMD 5962-95600XXMNA (Pending)

0.080

0.100

0.054

0.066

0.022

0.028

0.910

0.930

0.840

0.860

0.445

0.460

0.050

BSC 

0.100

TYP 

0.115

0.135

0.009 TYP

36

1

ALL DIMENSIONS ARE IN  INCHES

ALL DIMENSIONS ARE IN  INCHES

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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88512CA

O

RDERING

 I

NFORMATION

WHITE ELECTRONIC DESIGNS

SRAM

ORGANIZATION, 512Kx8

TECHNOLOGY:

CA = CMOS Standard Power

LPA = Low Power

ACCESS TIME (ns)

PACKAGE TYPE:

C = 32 lead Sidebrazed DIP, 600 mil (Package 9)

K = 36 lead Ceramic LCC (Package 502)

N = 32 lead Ceramic SOJ (Package 140)

T = 32 lead Sidebrazed DIP, 400 mil (Package 326)

B32 = 32 pin Ceramic Thinpack™ Flatpack (Package 321)

F32 = 32 pin Ceramic Flatpack (Package 344)

F36 = 36 pin Ceramic Flatpack (Package 316)

N36 = 36 lead Ceramic SOJ (Package 327)

DEVICE GRADE:

B = MIL-STD-883 Compliant

M = Military Screened

-55°C to +125°C

 I = Industrial

-40°C to +85°C

C = Commercial

0°C to +70°C

 EDI  8  8 512  CA  X  X  X