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1

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

WF128K32-XXX5

128K

X

32 5V FLASH MODULE, SMD 5962-94716

FEATURES

Access Times of 50*, 60, 70, 90, 120, 150ns

Packaging:

 

•66 pin, PGA Type, 1.075 inch square, Her metic

  Ceramic HIP (Package 400)

 

    •68 lead, Hermetic CQFP (G2U)

1

, 22.4mm (0.880 inch)

square, 3.56mm (0.140 inch) high (Package 510)

      •68 lead, Hermetic CQFP (G1U), 23.9mm (0.940 inch)

  square, 3.56mm (0.140 inch) high (Package 519)

      •68 lead, Hermetic CQFP (G1T), 23.9mm (0.940 inch)

  square, 4.06mm (0.160 inch) high (Package 524)

Sector  Architecture

 

   •8 equal size sectors of 16KBytes each

      •Any combination of sectors can be concurrently

  erased.

  Also supports full chip erase

100,000 Erase/Program Cycles Typical, 0°C to +70°C

Organized as 128Kx32

Commercial, Industrial and Military Temperature Ranges

FIG. 1    PIN CONFIGURATION FOR WF128K32N-XH1X5

PIN DESCRIPTION

I/O

0-31

Data Inputs/Outputs

A

0-16

Address Inputs

WE

1-4

Write Enables

CS

1-4

Chip Selects

OE

Output Enable

V

CC

Power Supply

GND

Ground

NC

Not Connected

TOP VIEW

December 2001 Rev. 4

5 Volt Programming. 5V ± 10% Supply

Low Power CMOS, 1mA Standby Typical

Embedded Erase and Program Algorithms

TTL Compatible Inputs and CMOS Outputs

Built-in Decoupling Caps and Multiple Ground Pins for

Low Noise Operation

Page Program Operation and Internal Program Control

Time

Weight

WF128K32-XG1UX5 - 5 grams typical

WF128K32-XG1TX5 - 5 grams typical

WF128K32-XG2UX5

1

 - 8 grams typical

WF128K32-XH1X5 - 13 grams typical

Note 1: Package Not Recommended For New Design

Note: For programming information refer to Flash Programming 1M5

Application Note.

* The access time of 50ns is available in Industrial and Commercial temperature

ranges only.

BLOCK DIAGRAM

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WF128K32-XXX5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

9    8    7    6    5    4    3    2    1   68  67  66  65  64  63  62  61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

8

I/O

9

I/O

10

I/O

11

I/O

12

I/O

13

I/O

14

I/O

15

V

CC

A

11

A

12

A

13

A

14

A

15

A

16

CS

1

OE

CS

2

NC

E

2

E

3

E

4

NC

NC

NC

I/O

16

I/O

17

I/O

18

I/O

19

I/O

20

I/O

21

I/O

22

I/O

23

GND

I/O

24

I/O

25

I/O

26

I/O

27

I/O

28

I/O

29

I/O

30

I/O

31

NC

A

0

A

1

A

2

A

3

A

4

A

5

CS

3

GND

CS

4

WE

1

A

6

A

7

A

8

A

9

A

10

V

CC

PIN DESCRIPTION

I/O

0-31

Data Inputs/Outputs

A

0-16

Address Inputs

WE

1-4

Write Enables

CS

1-4

Chip Selects

OE

Output Enable

V

CC

Power Supply

GND

Ground

NC

Not Connected

FIG. 3    PIN CONFIGURATION FOR WF128K32-XG1UX5, WF128K32-XG1TX5 AND

               WF128K32-XG2UX5

1

BLOCK DIAGRAM

TOP VIEW

Note 1: Package Not Recommended For New Design

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WF128K32-XXX5

ABSOLUTE MAXIMUM RATINGS (1)

NOTES:

1. Stresses above the absolute maximum rating may cause permanent damage to

the device. Extended operation at the maximum levels may degrade

performance and affect reliability.

2.  Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions,

inputs may overshoot Vss to -2.0 V for periods of up to 20ns. Maximum DC

voltage on output and I/O pins is Vcc + 0.5V. During voltage transitions, outputs

may overshoot to Vcc + 2.0 V for periods of up to 20ns.

3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9

may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage

on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.

DC CHARACTERISTICS - CMOS COMPATIBLE

(V

CC

 = 5.0V, V

SS 

= 0V, T

= -55°C TO +125°C)

NOTES:

1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).

    The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2. ICC active while Embedded Algorithm (program or erase) is in progress.

3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Max

Unit

Supply Voltage

V

CC

4.5

5.5

V

Input High Voltage

V

IH

2.0

V

CC

 + 0.3

V

Input Low Voltage

V

IL

-0.5

+0.8

V

Operating Temp. (Mil.)

T

A

-55

+125

°C

A

9

 Voltage for Sector Protect

V

ID

11.5

12.5

V

Parameter

Unit

Operating Temperature

-55 to +125

°C

Supply Voltage Range (V

CC

)

-2.0 to +7.0

V

Signal voltage range (any pin except A9) (2)

-2.0 to +7.0

V

Storage Temperature Range

-65 to +150

°C

Lead Temperature (soldering, 10 seconds)

+300

°C

Data Retention Mil Temp

10 years

Endurance (write/erase cycles) Mil Temp

10,000  cycles  min.

A

9

 Voltage for sector protect (V

ID

) (3)

-2.0 to +14.0

V

 Parameter

Symbol

Conditions

Unit

Min

Max

Input Leakage Current

I

LI

V

CC

 = 5.5, V

IN

 = GND to V

CC

10

µA

Output Leakage Current

I

LOx32

V

CC

 = 5.5, V

IN

 = GND to V

CC

10

µA

V

CC

 Active Current for Read

 

(1)

I

CC1

CS = V

IL

, OE = V

IH

140

mA

V

CC

 Active Current for Program

I

CC2

CS = V

IL

, OE = V

IH

200

mA

or Erase

 

(2)

V

CC

 Standby Current

I

CC3

V

CC

 = 5.5, CS = V

IH

, f = 5MHz

6.5

mA

V

CC

 Static Current

I

CC4

V

CC

 = 5.5, CS = V

IH

0.6

mA

Output Low Voltage

V

OL

I

OL

 = 8.0 mA, V

CC

 = 4.5

0.45

V

Output High Voltage

V

OH1

I

OH

 = -2.5 mA, V

CC

 = 4.5

0.85 x

V

V

CC

Output High Voltage

V

OH2

I

OH

 = -100 µA, V

CC

 = 4.5

V

CC

V

-0.4

Low V

CC

 Lock Out Voltage

V

LKO

3.2

V

Parameter

Symbol

Conditions

Max

Unit

OE capacitance

C

OE

V

IN

 = 0 V, f = 1.0 MHz

 50

pF

WE

1-4

 capacitance

C

WE

V

IN

 = 0 V, f = 1.0 MHz

pF

          HIP (PGA)

20

           CQFP G2U/G1U/G1T

15

CS

1-4

 capacitance

C

CS

V

IN

 = 0 V, f = 1.0 MHz

 20

pF

Data I/O capacitance

C

I/O

V

I/O

 = 0 V, f = 1.0 MHz

 20

pF

Address input capacitance

C

AD

V

IN 

 = 0 V, f = 1.0 MHz

 50

pF

   This parameter is guaranteed by design but not tested.

CAPACITANCE

(T

A

 = +25ºC)

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WF128K32-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED

(V

CC 

= 5.0V, V

SS

 = 0V, T

= -55°C TO+125°C)

FIG. 4

Notes:

VZ is programmable from -2V to +7V.

IOL & IOH programmable from 0 to 16mA.

Tester Impedance  Z0 = 75 ý.

VZ is typically the midpoint of VOH and VOL.

IOL & IOH

 

are adjusted to simulate a typical resistive load circuit.

ATE tester includes jig capacitance.

AC TEST CONDITIONS

Parameter

  Typ

   Unit

Input Pulse Levels

    V

IL

 = 0, V

IH

 = 3.0

    V

Input Rise and Fall

  5

    ns

Input and Output Reference Level

  1.5

    V

Output Timing Reference Level

  1.5

    V

Parameter

Symbol

-50

-60

-70

-90

-120

-150

Unit

Min

Max

Min

Max

Min Max

Min

Max

Min

Max

Min

Max

Write Cycle Time

t

AVAV

t

WC

50

60

70

90

120

150

ns

WE Setup Time

t

W L E L

t

WS

0

0

0

0

0

0

ns

CS Pulse Width

t

ELEH

t

CP

25

30

35

45

50

50

ns

Address Setup  Time

t

AVEL

t

AS

0

0

0

0

0

0

ns

Data Setup Time

t

DVEH

t

DS

25

30

30

45

50

50

ns

Data Hold Time

t

EHDX

t

DH

0

0

0

0

0

0

ns

Address Hold Time

t

E L A X

t

AH

40

45

45

45

50

50

ns

WE Hold from WE High

t

EHWH

t

WH

0

0

0

0

0

0

ns

CS Pulse Width High

t

EHEL

t

CPH

20

20

20

20

20

20

ns

Duration of Programming Operation

t

WHWH1

14

14

14

14

14

14

µs

Duration of Erase Operation

t

WHWH2

2.2

60

2.2

60

2.2

60

2.2

60

2.2

60

2.2

60

sec

Read Recovery before Write

t

GHEL

0

0

0

0

0

0

ns

Chip Programming Time

12.5

12.5

12.5

12.5

12.5

12.5

sec

AC T

EST

 C

IRCUIT

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WF128K32-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED

(V

CC

 = 5.0V, V

SS

 = 0V, T

A

 = -55°C TO +125°C)

Parameter

Symbol

-50

-60

-70

-90

-120

-150

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Write Cycle Time

t

AVAV

t

WC

50

60

70

90

120

150

ns

Chip Select Setup Time

t

E L W L

t

CS

0

0

0

0

0

0

ns

Write Enable Pulse Width

t

WLWH

t

WP

25

30

35

45

50

50

ns

Address Setup Time

t

A V W L

t

AS

0

0

0

0

0

0

ns

Data Setup Time

t

DVWH

t

DS

25

30

30

45

50

50

ns

Data Hold Time

t

WHDX

t

DH

0

0

0

0

0

0

ns

Address Hold Time

t

W L A X

t

AH

40

45

45

45

50

50

ns

Chip Select Hold Time

t

WHEH

t

CH

0

0

0

0

0

0

ns

Write Enable Pulse Width High

t

WHWL

t

WPH

20

20

20

20

20

20

ns

Duration of  Byte Programming Operation (min)

t

WHWH1

14

14

14

14

14

14

µs

Sector Erase Time

t

WHWH2

2.2

60

2.2

60

2.2

60

2.2

60

2.2

60

2.2

60

sec

Read Recovery Time Before Write

t

G H W L

0

0

0

0

0

0

ns

V

CC

 Setup Time

t

VCS

50

50

50

50

50

50

µs

Chip Programming Time

12.5

12.5

12.5

12.5

12.5

12.5

sec

Output Enable Setup Time

t

OES

0

0

0

0

0

0

ns

Output Enable Hold Time (1)

t

OEH

10

10

10

10

10

10

ns

1. For Toggle and Data Polling.

AC CHARACTERISTICS – READ ONLY OPERATIONS

(V

CC

 = 5.0V, V

SS

 = 0V,  T

= -55°C TO +125°C)

Parameter

Symbol

-50

-60

-70

-90

-120

-150

Unit

Min

Max

Min

Max

Min

Max

Min Max

Min

Max

Min

Max

Read Cycle Time

t

AVAV

t

RC

50

60

70

90

120

150

ns

Address Access Time

t

AVQV

t

ACC

50

60

70

90

120

150

ns

Chip Select Access Time

t

ELQV

t

CE

50

60

70

90

120

150

ns

OE to Output Valid

t

GLQV

t

OE

25

30

35

40

50

55

ns

Chip Select to Output High Z (1)

t

EHQZ

t

DF

20

20

20

25

30

35

ns

OE High to Output High Z (1)

t

GHQZ

t

DF

20

20

20

25

30

35

ns

Output Hold from Address, CS or OE Change,

t

AXQX

t

OH

0

0

0

0

0

0

ns

whichever is first

1. Guaranteed by design, not tested.

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WF128K32-XXX5

FIG. 5

AC WAVEFORMS FOR READ OPERATIONS

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WF128K32-XXX5

FIG. 6

NOTES

:

1. PA is the address of the memory location  to be programmed.

2. PD is the data to be programmed at byte address.

3. D7 is the output of the complement of the data written to the device (for each chip).

4. DOUT is the output of the data written to the device.

5.Figure indicates last two bus cycles of four bus cycle sequence.

WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED

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WF128K32-XXX5

FIG. 7

Notes:

1.  SA is the sector address for Sector Erase.

AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS

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WF128K32-XXX5

FIG. 8

AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS

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WF128K32-XXX5

FIG. 9

NOTES:

1. PA represents the address of the memory location to be programmed.

2. PD represents the data to be programmed at byte address.

3. D7 is the output of the complement of the data written to the device (for each chip).

4. DOUT is the output of the data written to the device.

5. Figure indicates the last two bus cycles of a four bus cycle sequence.

WRITE/ERASE/PROGRAM OPERATION, CS CONTROLLED

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WF128K32-XXX5

PACKAGE 400:

27.3 (1.075) 

±

  0.25 (0.010) SQ

PIN 1 IDENTIFIER

SQUARE PAD

ON BOTTOM

25.4 (1.0) TYP

15.24 (0.600) TYP

0.76 (0.030) 

±

 0.13 (0.005)

4.34 (0.171)

MAX

3.81 (0.150)

±

 0.13 (0.005)

2.54 (0.100)

TYP

25.4 (1.0) TYP

1.42 (0.056) 

±

  0.13 (0.005)

1.27 (0.050) TYP DIA

0.46 (0.018) 

±

 0.05 (0.002) DIA

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)

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WF128K32-XXX5

PACKAGE 510:   

68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)

1

0.940"

TYP

The White 68 lead G2U CQFP

fills the same fit and function as

the JEDEC 68 lead CQFJ or 68

PLCC. But the G2U has the

TCE and lead inspection

advantage of the CQFP form.

Note 1: Package Not Recommended For New Design

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

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WF128K32-XXX5

PACKAGE 519:   

68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G1U)

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

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WF128K32-XXX5

PACKAGE 524:   

68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G1T)

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

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WF128K32-XXX5

LEAD FINISH:

Blank = Gold plated leads

A = Solder dip leads

V

PP

 PROGRAMMING VOLTAGE

5  =  5V

DEVICE GRADE:

Q = MIL - STD 833 Compliant

M = Military Screened

-55°C to +125°C

 I = Industrial

-40°C to +85°C

C = Commercial

0°C to + 70°C

PACKAGE TYPE:

H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400)

G2U

1

 = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 510)

G1U = 23.9mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 519)

G1T = 23.9mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 524)

ACCESS TIME (ns)

IMPROVEMENT MARK

N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrade

ORGANIZATION, 128K x 32

User configurable as 256K x 16 or 512K x 8

Flash

WHITE ELECTRONIC DESIGNS CORP.

ORDERING INFORMATION

W  F   128K32  X - XXX X X 5 X

Note 1: Package Not Recommended For New Design

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WF128K32-XXX5

DEVICE TYPE

SPEED

PACKAGE

SMD NO.

128K  x  32  Flash

150ns

66 pin HIP (H1)

5962-94716  01H8X

128K  x  32  Flash

120ns

66 pin HIP (H1)

5962-94716  02H8X

128K  x  32  Flash

90ns

66 pin HIP (H1)

5962-94716  03H8X

128K  x  32  Flash

70ns

66 pin HIP (H1)

5962-94716  04H8X

128K  x  32  Flash

60ns

66 pin HIP (H1)

5962-94716  05H8X

128K  x  32  Flash

150ns

68  lead  CQFP  (G1U)

5962-94716  01H9X

128K  x  32  Flash

120ns

68  lead  CQFP  (G1U)

5962-94716  02H9X

128K  x  32  Flash

90ns

68  lead  CQFP  (G1U)

5962-94716  03H9X

128K  x  32  Flash

70ns

68  lead  CQFP  (G1U)

5962-94716  04H9X

128K  x  32  Flash

60ns

68  lead  CQFP  (G1U)

5962-94716  05H9X

128K  x  32  Flash

150ns

68  lead  CQFP  (G2U)

1

5962-94716  01HNX

1

128K  x  32  Flash

120ns

68  lead  CQFP  (G2U)

1

5962-94716  02HNX

1

128K  x  32  Flash

90ns

68  lead  CQFP  (G2U)

1

5962-94716  03HNX

1

128K  x  32  Flash

70ns

68  lead  CQFP  (G2U)

1

5962-94716  04HNX

1

128K  x  32  Flash

60ns

68  lead  CQFP  (G2U)

1

5962-94716  05HNX

1

Note 1: Package Not Recommended For New Design