background image

   Avalanche  Rugged  Technology

   Rugged  Gate  Oxide  Technology 

   Lower  Input  Capacitance

   Improved  Gate  Charge

   Extended  Safe  Operating  Area

   175

o

C  Operating  Temperature

   Lower  Leakage  Current  :  10 

µ

A (Max.)  @  V

DS

 = -60V

   Low  R

DS(ON) 

 :  0.22 

 (Typ.)

Advanced  Power  MOSFET

Thermal  Resistance

Junction-to-Case

Junction-to-Ambient

Junction-to-Ambient

R

θ

JC

R

θ

JA

R

θ

JA

o

C/W

Characteristic

Max.

Units

Symbol

Typ.

FEATURES

D

2

-PAK

1. Gate  2. Drain  3. Source

1

3

2

1

2

3

I

2

-PAK

*

*

   When  mounted  on  the  minimum  pad  size  recommended (PCB  Mount).

Absolute  Maximum  Ratings

Drain-to-Source Voltage

Continuous  Drain  Current  (T

C

=25

o

C)

Continuous  Drain  Current  (T

C

=100

o

C)

Drain  Current-Pulsed                              

Gate-to-Source  Voltage

Single  Pulsed  Avalanche  Energy         

Avalanche  Current                                 

Repetitive  Avalanche  Energy                

Peak  Diode  Recovery  dv/dt               

Total  Power  Dissipation  (T

A

=25

o

C)

Total  Power  Dissipation  (T

C

=25

o

C)

Linear  Derating  Factor

Operating  Junction  and

Storage  Temperature  Range

Maximum  Lead  Temp.  for  Soldering

Purposes,  1/8” from  case  for  5-seconds

Characteristic

Value

Units

Symbol

I

DM

V

GS

E

AS

I

AR

E

AR

dv/dt

P

D

I

D

T

J  

, T

STG

T

L

A

V

mJ

A

mJ

V/ns

W

W

W/

o

C

A

o

C

V

DSS

V

*

O

1

O

2

O

3

O

1

O

1

SFW/I2955

BV

DSS

  =  -60 V

R

DS(on)  

=  0.3

I

D

  =  -9.4 A

-60

-9.4

-6.6

-38

151

-9.4

4.9

-5.5

3.8

49

0.33

- 55  to  +175

300

3.06

40

62.5

--

--

--

20

 +

_

©1999 Fairchild Semiconductor Corporation

Rev. B

background image

P-CHANNEL

POWER MOSFET

Electrical Characteristics 

(T

C

=25

o

C  unless  otherwise  specified)

Drain-Source  Breakdown  Voltage

Breakdown  Voltage  Temp.  Coeff.

Gate  Threshold  Voltage

Gate-Source  Leakage ,  Forward

Gate-Source  Leakage ,  Reverse

Characteristic

Symbol

Max. Units

Typ.

Min.

Test  Condition

Static  Drain-Source

On-State  Resistance

Forward  Transconductance

Input  Capacitance

Output  Capacitance

Reverse  Transfer  Capacitance

Turn-On  Delay  Time

Rise  Time

Turn-Off  Delay  Time

Fall  Time

Total  Gate  Charge

Gate-Source  Charge

Gate-Drain(“Miller”) Charge

g

fs

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q

g

Q

gs

Q

gd

    BV

DSS

  ∆

BV/

T

J

    V

GS(th)

R

DS(on)

I

GSS

I

DSS

V

V/

o

C

V

nA

µ

A

pF

ns

nC

--

--

--

--

--

--

--

--

--

--

--

--

--

V

GS

=0V,I

D

=-250

µ

I

D

=-250

µ

A      See Fig 7

V

DS

=-5V,I

D

=-250

µ

A

V

GS

=-20V

V

GS

=20V

V

DS

=-60V

V

DS

=-48V,T

C

=150

o

V

GS

=-10V,I

D

=-4.7A      

V

DS

=-30V,I

D

=-4.7A

V

DD

=-30V,I

D

=-9.4A,

R

G

=18

See Fig 13        

V

DS

=-48V,V

GS

=-10V,

I

D

=-9.4A

See Fig 6 & Fig 12   

Drain-to-Source  Leakage  Current

V

GS

=0V,V

DS

=-25V,f =1MHz

      See Fig 5

Source-Drain  Diode  Ratings  and  Characteristics

Continuous  Source  Current

Pulsed-Source  Current

Diode  Forward  Voltage

Reverse  Recovery  Time

Reverse  Recovery  Charge

I

S

I

SM

V

SD

t

rr

Q

rr

Characteristic

Symbol

Max. Units

Typ.

Min.

Test  Condition

--

--

--

--

--

A

V

ns

µ

C

Integral reverse pn-diode

in the MOSFET

T

J

=25

o

C,I

S

=-9.4A,V

GS

=0V

T

J

=25

o

C,I

F

=-9.4A

di

F

/dt=100A/

µ

s             

O

4

O

5

O

4

O

4

O

5

O

4

O

4

O

4

O

1

SFW/I2955

-60

--

-2.0

--

--

--

--

--

-0.04

--

--

--

--

--

140

40

11

21

29

20

15

2.9

6.0

--

--

-4.0

-100

100

-10

-100

0.3

--

600

215

60

30

50

65

50

19

--

--

4.0

465

--

--

--

80

0.22

-9.4

-38

-3.8

--

--

Notes ;

  Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature

  L=2.0mH, I

AS

=-9.4A, V

DD

=-25V, R

G

=27

*

, Starting T

=25

o

C

  I

SD       

-9.4A, di/dt     250A/

µ

s, V

DD       

BV

DSS 

, Starting T

=25

o

C

  Pulse Test : Pulse Width = 250

µ

s, Duty Cycle     2%

  Essentially Independent of Operating Temperature

O

1

O

2

O

3

O

4

O

5

_

<

_

<

_

<

_

<

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P-CHANNEL

POWER MOSFET

Fig 1.  Output Characteristics

Fig 2.  Transfer Characteristics

Fig 6.  Gate Charge vs. Gate-Source Voltage

Fig 5.  Capacitance vs. Drain-Source Voltage

Fig 4.  Source-Drain Diode Forward Voltage

Fig 3.  On-Resistance vs. Drain Current

SFW/I2955

2

4

6

8

10

10

-1

10

0

10

1

25 

o

C

175 

o

C

- 55 

o

C

@ Notes :

  1. V

GS

 = 0 V

  2. V

DS

 = -30 V

  3. 250 

µ

s Pulse Test

-I

D

 , Drain Current  [A]

-V

GS

 , Gate-Source Voltage  [V]

0

10

20

30

40

50

60

70

0.0

0.1

0.2

0.3

0.4

@ Note : T

J

 = 25 

o

C

V

GS

 = -20 V

V

GS

 = -10 V

R

DS(on)

 , [

]

Drain-Source On-Resistance

-I

D

 , Drain Current  [A]

0.5

1.0

1.5

2.0

2.5

3.0

3.5

10

-1

10

0

10

1

175 

o

C

25 

o

C

@ Notes :

  1. V

GS

 = 0 V

  2. 250 

µ

s Pulse Test

-I

DR

 , Reverse Drain Current  [A]

-V

SD

 , Source-Drain Voltage  [V]

10

0

10

1

0

200

400

600

800

C

iss

= C

gs

+ C

gd

 ( C

ds

= shorted )

C

oss

= C

ds

+ C

gd

C

rss

= C

gd

@ Notes :

  1. V

GS

 = 0 V

  2. f = 1 MHz

rss

oss

iss

Capacitance  [pF]

-V

DS

 , Drain-Source Voltage [V]

10

-1

10

0

10

1

10

-1

10

0

10

1

@ Notes :

  1. 250 

µ

s Pulse Test

  2. T

C

 = 25 

o

C

                     V

GS

Top  :          - 15 V

                   - 10 V

                  - 8.0 V

                  - 7.0 V

                  - 6.0 V

                  - 5.5 V

                  - 5.0 V

Bottom  :   -  4.5 V

-I

D

 , Drain Current  [A]

-V

DS

 , Drain-Source Voltage  [V]

0

2

4

6

8

10

12

14

16

0

5

10

V

DS

 = -48 V

V

DS

 = -30 V

V

DS

 = -12 V

@ Notes : I

D

 =-9.4 A

-V

GS

 , Gate-Source Voltage  [V]

Q

G

 , Total Gate Charge  [nC]

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P-CHANNEL

POWER MOSFET

Fig 7.  Breakdown Voltage vs. Temperature

Fig 8.  On-Resistance vs. Temperature

Fig 11.  Thermal Response

Fig 10.  Max. Drain Current vs. Case Temperature

Fig 9.  Max. Safe Operating Area

P

DM

.

t

1.

t

2.

SFW/I2955

10

0

10

1

10

2

10

-1

10

0

10

1

10

2

10 ms

DC

1 ms

0.1 ms

@ Notes :

  1. T

C

 = 25 

o

C

  2. T

J

 = 175 

o

C

  3. Single Pulse

Operation in This Area 

is Limited by R 

DS(on)

-I

D

 , Drain Current  [A]

-V

DS

 , Drain-Source Voltage  [V]

-75

-50

-25

0

25

50

75

100

125

150

175

200

0.8

0.9

1.0

1.1

1.2

@ Notes :

  1. V

GS

 = 0 V

  2. I

D

 = -250 

µ

A

-BV

DSS

 , (Normalized)

Drain-Source Breakdown Voltage

T

J

 , Junction Temperature  [

o

C]

25

50

75

100

125

150

175

0

2

4

6

8

10

-I

D

 , Drain Current  [A]

T

c

 , Case Temperature  [

o

C]

-75

-50

-25

0

25

50

75

100

125

150

175

200

0.0

0.5

1.0

1.5

2.0

2.5

@ Notes :

  1. V

GS

 = -10 V

  2. I

D

 = -4.7 A

R

DS(on)

 , (Normalized)

Drain-Source On-Resistance

T

J

 , Junction Temperature  [

o

C]

10

- 5

10

- 4

10

- 3

10

- 2

10

- 1

10

0

10

1

10

- 1

10

0

single pulse

0.2

0.1

0.01

0.02

0.05

D=0.5

@ Notes :

  1. Z

θ

J C

(t)=3.06 

o

C/W Max.

  2. Duty Factor, D=t

1

/t

2

  3. T

J M

-T

C

=P

D M

*Z

θ

J C

(t)

Z

θ

JC

(t) ,  Thermal Response

t

1

  ,   S q u a r e   W a v e   P u l s e   D u r a t i o n     [ s e c ]

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P-CHANNEL

POWER MOSFET

Fig 12.  Gate Charge Test Circuit  &  Waveform

Fig 13.  Resistive Switching Test Circuit  &  Waveforms

Fig 14.  Unclamped Inductive Switching Test Circuit  &  Waveforms

E

AS 

=

L

I

AS

2

----

2

1

--------------------

BV

DSS

 -- V

DD

BV

DSS

V

in

V

out

10%

90%

 t

d(on)

t

r

t

 on

t

 off

t

d(off)

t

f

Charge

V

GS

-10V

Q

g

Q

gs

Q

gd

Vary t

p

 to obtain

required peak I

D

-10V

V

DD

C

L

L

V

DS

I

D

R

G

t

 p

DUT

BV

DSS

p

V

DD

I

AS

V

DS 

(t)

I

(t)

Time

V

DD

( 0.5 rated V

DS 

)

-10V

V

out

V

in

R

L

DUT

R

G

-3mA

V

GS

Current Sampling (I

G

)

Resistor

Current Sampling (I

D

)

Resistor

DUT

V

DS

300nF

50K

200nF

12V

Same Type

as DUT

“ Current Regulator ”

R

1

R

2

SFW/I2955

background image

P-CHANNEL

POWER MOSFET

Fig 15.  Peak Diode Recovery dv/dt Test Circuit  &  Waveforms

DUT

V

DS

+

--

L

I

 S

Driver

V

GS

R

G

Compliment of DUT

(N-Channel)

V

GS

• dv/dt controlled by “R

G

• I

S

 controlled by Duty Factor “D”

V

DD

10V

V

GS

( Driver )

I

 S

( DUT )

V

DS

( DUT )

V

DD

Body Diode

Forward Voltage Drop

V

f

I

FM

 , Body Diode Forward Current

 Body Diode Reverse Current

I

RM

Body Diode Recovery dv/dt

di/dt

D =

Gate Pulse Width

Gate Pulse Period

--------------------------

SFW/I2955

background image

TRADEMARKS

ACEx™

CoolFET™

CROSSVOLT™

E

2

CMOS

TM

FACT™

FACT Quiet Series™

FAST

®

FASTr™

GTO™

HiSeC™

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench™

QS™

Quiet Series™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

TinyLogic™

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Formative or

In Design

First Production

Full Production

Not In Production

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

UHC™

VCX™