background image

CONNECTION DIAGRAM

8-Pin Plastic Mini-DIP (N),

Cerdip (Q) and SOIC (R) Packages

1

2

3

4

8

7

6

5

AD797

DECOMPENSATION & 

DISTORTION 

NEUTRALIZATION

OUTPUT

OFFSET NULL

–IN

+IN

+V

S

–V

S

OFFSET NULL

TOP VIEW

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

a

Ultralow Distortion,

Ultralow Noise Op Amp

AD797*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,  U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

FEATURES

Low Noise

0.9 nV/

Hz typ (1.2 nV/

Hz max) Input Voltage

Noise at 1 kHz

50 nV p-p Input Voltage Noise, 0.1 Hz to 10 Hz

Low Distortion

–120 dB Total Harmonic Distortion at 20 kHz

Excellent AC Characteristics

800 ns Settling Time to 16 Bits (10 V Step)

110 MHz Gain Bandwidth (G = 1000)

8 MHz Bandwidth (G = 10)

280 kHz Full Power Bandwidth at 20 V p-p

20 V/

s Slew Rate

Excellent DC Precision

80 

V max Input Offset Voltage

1.0 

V/؇C V

OS

 Drift

Specified for 

؎5 V and ؎15 V Power Supplies

High Output Drive Current of 50 mA

APPLICATIONS

Professional Audio Preamplifiers

IR, CCD, and Sonar Imaging Systems

Spectrum Analyzers

Ultrasound Preamplifiers

Seismic Detectors

⌺⌬ ADC/DAC Buffers

PRODUCT DESCRIPTION

The AD797 is a very low noise, low distortion operational

amplifier ideal for use as a preamplifier. The low noise of

0.9 nV/

Hz

 and low total harmonic distortion of –120 dB at

audio bandwidths give the AD797 the wide dynamic range

5

0

10M

3

1

100

2

10

4

1M

100k

10k

1k

FREQUENCY – Hz

INPUT VOLTAGE NOISE – nV/

Hz

AD797 Voltage Noise Spectral Density

*Patent pending.

necessary for preamps in microphones and mixing consoles.

Furthermore, the AD797’s excellent slew rate of 20 V/

µ

s and

110 MHz gain bandwidth make it highly suitable for low fre-

quency ultrasound applications.

The AD797 is also useful in IR and Sonar Imaging applications

where the widest dynamic range is necessary. The low distor-

tion and 16-bit settling time of the AD797 make it ideal for

buffering the inputs to 

Σ∆

 ADCs or the outputs of high resolu-

tion DACs especially when they are used in critical applications

such as seismic detection and spectrum analyzers. Key features

such as a 50 mA output current drive and the specified power

supply voltage range of 

±

5 to 

±

15 volts make the AD797 an

excellent general purpose amplifier.

–90

–130

300k

–120

300

100

–110

–100

100k

30k

10k

3k

1k

FREQUENCY – Hz

THD – dB

MEASUREMENT

LIMIT

0.001

0.0003

0.0001

THD – %

THD vs. Frequency

background image

REV. C

–2–

AD797–SPECIFICATIONS

(@ T

A

 = +25

؇C and V

S

 = 

؎15 V dc, unless otherwise noted)

   AD797A/S

1

AD797B

Model

Conditions

V

S

Min

Typ

Max

Min

Typ

Max

Units

INPUT OFFSET VOLTAGE

±

5 V, 

±

15 V

25

80

10

40

µ

V

T

MIN

 to T

MAX

50

125/180

30

60

µ

V

Offset Voltage Drift

±

5 V, 

±

15 V

0.2

1.0

0.2

0.6

µ

V/

°

C

INPUT BIAS CURRENT

±

5 V, 

±

15 V

0.25

1.5

0.25

0.9

µ

A

T

MIN

 to T

MAX

0.5

3.0

0.25

2.0

µ

A

INPUT OFFSET CURRENT

±

5 V, 

±

15 V

100

400

80

200

nA

T

MIN

 to T

MAX

120

600/700

120

300

nA

OPEN-LOOP GAIN

V

OUT

 = 

±

10 V

±

15 V

R

LOAD

 = 2 k

1

20

2

20

V/

µ

V

T

MIN

 to T

MAX

1

6

2

10

V/

µ

V

R

LOAD

 = 600 

1

15

2

15

V/

µ

V

T

MIN

 to T

MAX

1

5

2

7

V/

µ

V

@ 20 kHz

2

14000

20000

14000 20000

V/V

DYNAMIC PERFORMANCE

Gain Bandwidth Product

G = 1000

±

15 V

110

110

MHz

G = 1000

2

±

15 V

450

450

MHz

–3 dB Bandwidth

G = 10

±

15 V

8

8

MHz

Full Power Bandwidth

3

V

O

 = 20 V p-p,

R

LOAD

 = 1 k

±

15 V

280

280

kHz

Slew Rate

R

LOAD

 = 1 k

±

15 V

12.5

20

12.5

20

V/

µ

s

Settling Time to 0.0015%

10 V Step

±

15 V

800

1200

800

1200

ns

COMMON-MODE REJECTION

V

CM

 = CMVR

±

5 V, 

±

15 V

114

130

120

130

dB

T

MIN

 to T

MAX

110

120

114

120

dB

POWER SUPPLY REJECTION

V

S

 = 

±

5 V to 

±

18 V

114

130

120

130

dB

T

MIN

 to T

MAX

110

120

114

120

dB

INPUT VOLTAGE NOISE

f = 0. 1 Hz to 10 Hz

±

15 V

50

50

nV p-p

f = 10 Hz

±

15 V

1.7

1.7

2.5

nV/

Hz

f = 1 kHz

±

15 V

0.9

1.2

0.9

1.2

nV/

Hz

f = 10 Hz–1 MHz

±

15 V

1.0

1.3

1.0

1.2

µ

V rms

INPUT CURRENT NOISE

f = 1 kHz

±

15 V

2.0

2.0

pA/

Hz

INPUT COMMON-MODE

±

15 V

±

11

±

12

±

11

±

12

V

VOLTAGE RANGE

±

5 V

±

2.5

±

3

±

2.5

±

3

V

OUTPUT VOLTAGE SWING

R

LOAD

 = 2 k

±

15 V

±

12

±

13

±

12

±

13

V

R

LOAD

 = 600 

±

15 V

±

11

±

13

±

11

±

13

V

R

LOAD

 = 600 

±

5 V

±

2.5

±

3

±

2.5

±

3

V

Short-Circuit Current

±

5 V, 

±

15 V

80

80

mA

Output Current

4

±

5 V, 

±

15 V

30

50

30

50

mA

TOTAL HARMONIC DISTORTION

R

LOAD

 = 1 k

, C

N

 = 50 pF

±

15 V

–98

–90

–98

–90

dB

f = 250 kHz, 3 V rms

R

LOAD

 = 1 k

±

15 V

–120

–110

–120 –110

dB

f = 20 kHz, 3 V rms

INPUT CHARACTERISTICS

Input Resistance (Differential)

7.5

7.5

k

Input Resistance (Common Mode)

100

100

M

Input Capacitance (Differential)

5

20

20

pF

Input Capacitance (Common Mode)

5

5

pF

OUTPUT RESISTANCE

A

V

 = +1, f = 1 kHz

3

3

m

POWER SUPPLY

Operating Range

±

5

±

18

±

5

±

18

V

Quiescent Current

±

5 V, 

±

15 V

8.2

10.5

8.2

10.5

mA

NOTES

1

See standard military drawing for 883B specifications.

2

Specified using external decompensation capacitor, see Applications section.

3

Full Power Bandwidth = Slew Rate/2 

π

 V

PEAK

.

4

Output Current for |V

S

 – V

OUT

| >4 V, A

OL

 > 200 k

.

5

Differential input capacitance consists of 1.5 pF package capacitance and 18.5 pF from the input differential pair.

Specifications subject to change without notice.

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AD797

REV. C

–3–

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±

18 V

Internal Power Dissipation @ +25

°

C

2

Input Voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±

V

S

Differential Input Voltage

3

 . . . . . . . . . . . . . . . . . . . . . .

±

0.7 V

Output Short Circuit Duration  . . . . . . . Indefinite Within max

Internal Power Dissipation

Storage Temperature Range (Cerdip)  . . . . . . –65

°

C to +150

°

C

Storage Temperature Range (N, R Suffix)  . .  –65

°

C to +125

°

C

Operating Temperature Range

AD797A/B  . . . . . . . . . . . . . . . . . . . . . . . . . –40

°

C to +85

°

C

AD797S  . . . . . . . . . . . . . . . . . . . . . . . . . . –55

°

C to +125

°

C

Lead Temperature Range (Soldering 60 sec)  . . . . . . . +300

°

C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only, and functional

operation of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2

Internal Power Dissipation:

8-Pin SOIC = 0.9 Watts (T

A

–25

°

C)/

θ

JA

8-Pin Plastic DIP and Cerdip = 1.3 Watts – (T

A

–25

°

C)/

θ

JA

Thermal Characteristics

8-Pin Plastic DIP Package: 

θ

JA

 = 95

°

C/W

8-Pin Cerdip Package: 

θ

JA

 = 110

°

C/W

8-Pin Small Outline Package: 

θ

JA

 = 155

°

C/W

3

The AD797’s inputs are protected by back-to-back diodes. To achieve low noise,

internal current limiting resistors are not incorporated into the design of this

amplifier. If the differential input voltage exceeds 

±

0.7 V, the input current should

be limited to less than 25 mA by series protection resistors. Note, however, that this

will degrade the low noise performance of the device.

ESD SUSCEPTIBILITY

ESD (electrostatic discharge) sensitive device. Electrostatic

charges as high as 4000 volts, which readily accumulate on the

human body and on test equipment, can discharge without

detection. Although the AD797 features proprietary ESD pro-

tection circuitry, permanent damage may still occur on these

devices if they are subjected to high energy electrostatic dis-

charges. Therefore, proper ESD precautions are recommended

to avoid any performance degradation or loss of functionality.

METALIZATION PHOTO

Contact factory for latest dimensions.

Dimensions shown in inches and (mm).

NOTE

The AD797 has double layer metal. Only one layer is shown here for clarity.

ORDERING GUIDE

Temperature

Package

Package

Model

Range

Description

Option

AD797AN

–40

°

C to +85

°

C

8-Pin Plastic DIP

N-8

AD797BN

–40

°

C to +85

°

C

8-Pin Plastic DIP

N-8

AD797BR

–40

°

C to +85

°

C

8-Pin Plastic SOIC

SO-8

AD797BR-REEL

–40

°

C to +85

°

C

8-Pin Plastic SOIC

SO-8

AD797BR-REEL7

–40

°

C to +85

°

C

8-Pin Plastic SOIC

SO-8

AD797AR

–40

°

C to +85

°

C

8-Pin Plastic SOIC

SO-8

AD797AR-REEL

–40

°

C to +85

°

C

8-Pin Plastic SOIC

SO-8

AD797AR-REEL7

–40

°

C to +85

°

C

8-Pin Plastic SOIC

SO-8

5962-9313301MPA

–55

°

C to +125

°

C

8-Pin Cerdip

Q-8

background image

AD797–Typical Characteristics

–4–

REV. C

HORIZONTAL SCALE – 5 sec/DIV

VERTICAL SCALE – 0.01

µ

V/DIV

Figure 4. 0.1 Hz to 10 Hz Noise

–60

140

–40

100

120

80

60

40

20

0

–20

–2.0

–1.5

–1.0

–0.5

0.0

INPUT BIAS CURRENT – 

µ

A

TEMPERATURE – 

°

C

Figure 5. Input Bias Current vs. Temperature

140

140

100

60

–40

80

–60

120

120

100

80

60

40

20

0

–20

40

TEMPERATURE – 

°

C

SHORT CIRCUIT CURRENT – mA

SOURCE CURRENT

SINK CURRENT

Figure 6. Short Circuit Current vs. Temperature

20

0

0

20

15

5

5

10

10

15

INPUT COMMON-MODE RANGE – ±Volts 

SUPPLY VOLTAGE – ±Volts  

Figure 1. Common-Mode Voltage Range vs. Supply

OUTPUT VOLTAGE SWING – ±Volts 

20

0

0

20

15

5

5

10

10

15

SUPPLY VOLTAGE – ±Volts 

–V

OUT

+V

OUT

Figure 2. Output Voltage Swing vs. Supply

OUTPUT VOLTAGE SWING – Volts p-p

LOAD RESISTANCE – 

30

10

0

10

100

10k

1k

20

V   = ±5V

S

V   = ±15V

S

Figure 3. Output Voltage Swing vs. Load Resistance

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AD797

REV. C

–5–

20

5

0

15

10

SUPPLY VOLTAGE – ±Volts

11

6

9

7

8

10

+125°C

+25°C

–55°C

QUIESCENT SUPPLY CURRENT – mA

Figure 7. Quiescent Supply Current vs. Supply Voltage

12

0

0

±20

9

3

±5

6

±10

±15

SUPPLY VOLTAGE – Volts

OUTPUT VOLTAGE – Volts rms

 

FREQ = 1kHz

 

R

L

 = 600

 

G = +10

Figure 8. Output Voltage vs. Supply for 0.01% Distortion

1.0

0.0

10

0.6

0.2

2

0.4

0

0.8

8

6

4

0.0015%

0.01%

STEP SIZE – Volts

SETTLING TIME – 

µ

s

Figure 9. Settling Time vs. Step Size (

±

)

20

1M

80

40

10

60

1

120

100

100k

10k

1k

100

140

50

75

100

125

150

CMR

POWER SUPPLY REJECTION – dB

COMMON MODE REJECTION – dB

FREQUENCY – Hz

PSR

–SUPPLY

PSR

+SUPPLY

Figure 10. Power Supply and Common-Mode Rejection

vs. Frequency

–60

–100

–120

0.01

0.1

10

1.0

–80

R

L

 = 600

G = +10

FREQ = 10kHz

NOISE BW = 100kHz

V

S

= ±5V

= ±15V

V

S

OUTPUT LEVEL – Volts

THD + NOISE – dB

Figure 11. Total Harmonic Distortion (THD) + Noise vs.

Output Level

Figure 12. Large Signal Frequency Response

30

10

0

10k

100k

10M

1M

20

±

5V SUPPLIES

±

15V SUPPLIES

R

L

 = 600

background image

AD797–Typical Characteristics

–6–

REV. C

5

0

10M

3

1

100

2

10

4

1M

100k

10k

1k

FREQUENCY – Hz

INPUT VOLTAGE NOISE – nV/

Hz

Figure 13. Input Voltage Noise Spectral Density

120

0

100M

60

20

1k

40

100

100

80

10M

1M

100k

10k

FREQUENCY – Hz

OPEN-LOOP GAIN – dB

+100

+80

+60

+40

+20

0

PHASE MARGIN – DEGREES

PHASE MARGIN

GAIN

 WITHOUT 

R

S

*

WITH R

S

*

 WITHOUT 

R

S

*

WITH R

S

*

  *R

S

  = 100Ω

   SEE FIGURE 22

Figure 14. Open-Loop Gain & Phase vs. Frequency

–60

140

–40

100

120

80

60

40

20

0

–20

300

150

0

–150

–300

INPUT OFFSET CURRENT – nA

TEMPERATURE – 

°

C

OVER COMPENSATED

UNDER COMPENSATED

Figure 15. Input Offset Current vs. Temperature

–60

140

–40

100

120

80

60

40

20

0

–20

120

110

100

90

80

35

30

25

20

15

SLEW RATE – V/

µ

s

GAIN/BANDWIDTH PRODUCT – MHz (G = 1000)

TEMPERATURE – 

°

C

GAIN/BANDWIDTH PRODUCT

SLEW RATE

RISING EDGE 

SLEW RATE

FALLING EDGE 

Figure 16. Slew Rate & Gain/Bandwidth Product vs.

Temperature

100

10k

1k

160

100

120

140

LOAD RESISTANCE – Ohms

OPEN-LOOP GAIN – dB

Figure 17. Open-Loop Gain vs. Resistive Load

100

0.01

10

1M

10

0.1

100

1

10k

100k

1k

MAGNITUDE OF OUTPUT IMPEDANCE – Ohms

FREQUENCY – Hz

* SEE FIGURE 29

WITHOUT C

N

*

WITH C

N

*

Figure 18. Magnitude of Output Impedance vs. Frequency

background image

AD797

REV. C

–7–

20pF

1k

V

OUT

1k

V

IN

** SEE FIGURE 32

 AD797

**

2

7

3

4

6

**

–V

S

+V

S

Figure 19. Inverter

Connection

 *  VALUE OF SOURCE RESISTANCE – 

    SEE TEXT

** SEE FIGURE 32

100

R

S

*

V

OUT

V

IN

 AD797

**

2

7

3

4

6

**

–V

S

+V

S

600

Figure 22. Follower

Connection

See Figure 40 for settling time

test circuit.

10

90

100

0%

5V

1

µ

s

Figure 20. Inverter Large Signal

Pulse Response

10

90

100

0%

1

µ

s

5V

Figure 23. Follower Large Signal

Pulse Response

10

90

100

0%

500ns

5mV

Figure 25. 16-Bit Settling Time

Positive Input Pulse

10

90

100

0%

100ns

50mV

Figure 21. Inverter Small Signal

Pulse Response

10

90

100

0%

100ns

50mV

Figure 24. Follower Small Signal

Pulse Response

10

90

100

0%

500ns

5mV

Figure 26. 16-Bit Settling Time

Negative Input Pulse

background image

AD797

REV. C

–8–

This matching benefits not just dc precision but since it holds

up dynamically, both distortion and settling time are also

reduced. This single stage has a voltage gain of >5 

×

 10

6

 and

V

OS

 <80 

µ

V, while at the same time providing THD + noise of

less than –120 dB and true 16 bit settling in less than 800 ns.

The elimination of second stage noise effects has the additional

benefit of making the low noise of the AD797 (<0.9 nV/

Hz

)

extend to beyond 1 MHz. This means new levels of perfor-

mance for sampled data and imaging systems. All of this perfor-

mance as well as load drive in excess of 30 mA are made

possible by Analog Devices’ advanced Complementary Bipolar

(CB) process.

Another unique feature of this circuit is that the addition of a

single capacitor, C

N

 (Figure 28), enables cancellation of distor-

tion due to the output stage. This can best be explained by

referring to a simplified representation of the AD797 using ide-

alized blocks for the different circuit elements (Figure 29).

A single equation yields the open-loop transfer function of this

amplifier, solving it (at Node B) yields:

  

  

V

O

V

IN

=

gm

C

N

A

j

ω

– C

N

j

ω

C

C

A

j

ω

gm = the transconductance of Q1 and Q2

A = the gain of the output stage, (~1)

V

O

 = voltage at the output

V

IN

 = differential input voltage

When C

N

 is equal to C

C

 this gives the ideal single pole op amp

response:

  

V

O

V

IN

=

gm

j

ω

C

The terms in A, which include the properties of the output

stage such as output impedance and distortion, cancel by

simple subtraction, and therefore the distortion cancellation

does not affect the stability or frequency response of the ampli-

fier. With only 500 

µ

A of output stage bias the AD797 delivers

a 1 kHz sine wave into 600 

 at 7 V rms with only 1 ppm of

distortion.

I1

I2

+IN

Q1

Q2

I3

–IN

C

C

I4

OUT

C

N

C

B

CURRENT

MIRROR

1

A

A

Figure 29. AD797 Block Diagram

THEORY OF OPERATION

The new architecture of the AD797 was developed to overcome

inherent limitations in previous amplifier designs. Previous pre-

cision amplifiers used three stages to ensure high open-loop

gain, Figure 27b, at the expense of additional frequency com-

pensation components. Slew rate and settling performance are

usually compromised, and dynamic performance is not ad-

equate beyond audio frequencies. As can be seen in Figure 27b,

the first stage gain is rolled off at high frequencies by the com-

pensation network. Second stage noise and distortion will then

appear at the input and degrade performance. The AD797 on

the other hand, uses a single ultrahigh gain stage to achieve dc

as well as dynamic precision. As shown in the simplified sche-

matic (Figure 28), nodes A, B, and C all track in voltage forcing

the operating points of all pairs of devices in the signal path to

match. By exploiting the inherent matching of devices fabricated

on the same IC chip, high open-loop gain, CMRR, PSRR, and

low V

OS

 are all guaranteed by pairwise device matching (i.e.,

NPN to NPN & PNP to PNP), and not absolute parameters

such as beta and early voltage.

R1

C1

R

L

V

OUT

GAIN = gmR1 ≈  5 x 10

6

BUFFER

gm

a.

gm

R1

C1

R

L

V

OUT

GAIN = gmR1 *A2 *A3

R2

A2

A3

C2

BUFFER

b.

Figure 27. Model of AD797 vs. That of a Typical

Three-Stage Amplifier

R2

R3

+IN

Q1

Q2

I1

–IN

Q5

I7

Q6

C

C

I4

Q7

R1

Q3

Q4

Q12

I5

Q8

Q9

I6

Q11

Q10

OUT

V

CC

V

SS

C

N

C

A

B

Figure 28. AD797 Simplified Schematic

background image

AD797

REV. C

–9–

NOISE AND SOURCE IMPEDANCE CONSIDERATIONS

The AD797’s ultralow voltage noise of 0.9 nV/

Hz

 is achieved

with special input transistors running at nearly 1 mA of collector

current. It is important then to consider the total input referred

noise (e

N

total), which includes contributions from voltage noise

(e

N

), current noise (i

N

), and resistor noise (

4 kTr

S

).

e

N

total = [e

N

2

 + kTr

S

 + 4 (i

N

r

S

)

2

]

l/2

 

  Equation 1

where r

S

 = total input source resistance.

This equation is plotted for the AD797 in Figure 30. Since opti-

mum dc performance is obtained with matched source resis-

tances, this case is considered even though it is clear from

Equation 1 that eliminating the balancing source resistance will

lower the total noise by reducing the total r

S

 by a factor of two.

At very low source resistance (r

S

 <50 

), the amplifiers’ voltage

noise dominates. As source resistance increases the Johnson

noise of r

S

 dominates until at higher resistances (r

S

 >2 k

) the

current noise component is larger than the resistor noise.

100

1

0.1

10

10

100

1000

10000

SOURCE RESISTANCE – 

NOISE – nV/

Hz

TOTAL NOISE

RESISTOR

NOISE

ONLY

Figure 30. Noise vs. Source Resistance

The AD797 is the optimum choice for low noise performance

provided the source resistance is kept <1 k

. At higher values of

source resistance, optimum performance with respect to noise

alone is obtained with other amplifiers from Analog Devices (see

Table I).

Table I. Recommended Amplifiers for Different Source

Impedances

r

S

, ohms

Recommended Amplifier

0 to <1 k

AD797

1 k to <10 k

AD707, AD743/AD745, OP27/OP37, OP07

10 k to <100 k

AD705, AD743/AD745, OP07

>100 k

AD548, AD549, AD645, AD711, AD743/

AD745

LOW FREQUENCY NOISE

Analog Devices specifies low frequency noise as a peak to peak

(p-p) quantity in a 0.1 Hz to 10 Hz bandwidth. Several tech-

niques can be used to make this measurement. The usual tech-

nique involves amplifying, filtering, and measuring the amplifiers

noise for a predetermined test time. The noise bandwidth of the

filter is corrected for and the test time is carefully controlled

since the measurement time acts as an additional low frequency

roll-off.

The plot in Figure 4 was made using a slightly different tech-

nique. Here an FFT based instrument (Figure 31) is used to

generate a 10 Hz “brickwall” filter. A low frequency pole at

0.1 Hz is generated with an external ac coupling capacitor, the

instrument being dc coupled.

Several precautions are necessary to get optimum low frequency

noise performance:

1. Care must be used to account for the effects of r

S

, even a

10 

 resistor has 0.4 nV/

Hz

 of noise (an error of 9% when

root sum squared with 0.9 nV/

Hz

).

2. The test set up must be fully warmed up to prevent e

OS

 drift

from erroneously contributing to input noise.

3. Circuitry must be shielded from air currents. Heat flow out

of the package through its leads creates the opportunity for a

thermoelectric potential at every junction of different metals.

Selective heating and cooling of these by random air currents

will appear as 1/f noise and obscure the true device noise.

4. The results must be interpreted using valid statistical

techniques.

100k

1.5

µ

F

1

HP 3465

DYNAMIC SIGNAL

ANALYZER

(10Hz)

V

OUT

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

 AD797

**

2

7

3

4

6

**

–V

S

+V

S

Figure 31. Test Setup for Measuring 0.1 Hz to 10 Hz Noise

WIDEBAND NOISE

The AD797, due to its single stage design, has the property that

its noise is flat over frequencies from less than 10 Hz to beyond

1 MHz. This is not true of most dc precision amplifiers where

second stage noise contributes to input referred noise beyond

the audio frequency range. The AD797 offers new levels of per-

formance in wideband imaging applications. In sampled data

systems, where aliasing of out of band noise into the signal band

is a problem, the AD797 will out perform all previously avail-

able IC op amps.

background image

AD797

REV. C

–10–

BYPASSING CONSIDERATIONS

To take full advantage of the very wide bandwidth and dynamic

range capabilities of the AD797 requires some precautions.

First, multiple bypassing is recommended in any precision

application. A 1.0 

µ

F–4.7 

µ

F tantalum in parallel with 0.1 

µ

F

ceramic bypass capacitors are sufficient in most applications.

When driving heavy loads a larger demand is placed on the sup-

ply bypassing. In this case selective use of larger values of tanta-

lum capacitors and damping of their lead inductance with small

value (1.1 

 to 4.7 

) carbon resistors can be an improvement.

Figure 32 summarizes bypassing recommendations. The symbol

(**) is used throughout this data sheet to represent the parallel

combination of a 0.1 

µ

F and a 4.7 

µ

F capacitor.

V

S

0.1

µ

F

USE SHORT

LEAD LENGTHS

(<5mm)

KELVIN RETURN

LOAD

CURRENT

4.7 – 22.0

µ

F

USE SHORT

LEAD RETURNS

(<5mm)

OR

4.7

µ

F

V

S

1.1 – 4.7

0.1

µ

F

KELVIN RETURN

LOAD

CURRENT

Figure 32. Recommended Power Supply Bypassing

THE NONINVERTING CONFIGURATION

Ultralow noise requires very low values of r

BB

’ (the internal

parasitic resistance) for the input transistors (

). This im-

plies very little damping of input and output reactive interac-

tions. With the AD797, additional input series damping is

required for stability with direct input to output feedback. A

100 

 resistor in the inverting input (Figure 33) is sufficient;

the 100 

 balancing resistor (R2) is recommended, but is not

required for stability. The noise penalty is minimal (e

N

total

2.1 nV/

Hz

), which is usually insignificant. Best response

flatness is obtained with the addition of a small capacitor

(C

L

 < 33 pF) in parallel with the 100 

 resistor (Figure 34).

The input source resistance and capacitance will also affect the

response slightly and experimentation may be necessary for best

results.

R2

100

R1

100

V

OUT

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

V

IN

R

L

600

 AD797

**

2

7

3

4

6

**

–V

S

+V

S

Figure 33. Voltage Follower Connection

Low noise preamplification is usually done in the noninverting

mode (Figure 35). For lowest noise the equivalent resistance of

the feedback network should be as low as possible. The 30 mA

minimum drive current of the AD797 makes it easier to achieve

this. The feedback resistors can be made as low as possible with

due consideration to load drive and power consumption. Table

II gives some representative values for the AD797 as a low noise

follower. Operation on 5 volt supplies allows the use of a 100 

or less feedback network (R1 + R2). Since the AD797 shows

no unusual behavior when operating near its maximum rated

current, it is suitable for driving the AD600/AD602 (Figure 47)

while preserving their low noise performance.

Optimum flatness and stability at noise gains >1 sometimes

requires a small capacitor (C

L

) connected across the feedback

resistor (R1, Figure 35). Table II includes recommended values

of C

L

 for several gains. In general, when R2 is greater than

100 

 and C

L

 is greater than 33 pF, a 100 

 resistor should

be placed in series with C

L

. Source resistance matching is

assumed, and the AD797 should never be operated with unbal-

anced source resistance >200 k

/G.

R

S

*

C

S

*

100

 AD797

**

2

7

3

4

6

**

V

OUT

–V

S

+V

S

 * SEE TEXT

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

V

IN

600

C

L

Figure 34. Alternative Voltage Follower Connection

R2

R1

R

L

 AD797

**

2

7

3

4

6

**

V

OUT

–V

S

+V

S

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

V

IN

C

L

Figure 35. Low Noise Preamplifier

Table II. Values for Follower With Gain Circuit

Noise

Gain

R1

R2

C

L

(Excluding r

S

)

2

1  k

1 k

20 pF

3.0 nV/

Hz

2

300 

300 

10 pF

1.8 nV/

Hz

10

33.2 

300 

5 pF

1.2 nV/

Hz

20

16.5 

316 

1.0 nV/

Hz

>35

10 

(G–1) • 10 

0.98 nV/

Hz

The I-to-V converter is a special case of the follower configura-

tion. When the AD797 is used in an I-to-V converter, for in-

stance as a DAC buffer, the circuit of Figure 36 should be used.

The value of C

L

 depends on the DAC and again, if C

L

 is

background image

AD797

REV. C

–11–

600

100

20–120pF

 AD797

**

2

7

3

4

6

**

V

OUT

–V

S

+V

S

 * SEE TEXT

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

I

IN

R

S

*

C

S

*

R1

Figure 36. I-to-V Converter Connection

greater than 33 pF a 100 

 series resistor is required. A by-

passed balancing resistor (R

S

 and C

S

) can be included to mini-

mize dc errors.

THE INVERTING CONFIGURATION

The inverting configuration (Figure 37) presents a low input

impedance, R1, to the source. For this reason, the goals of both

low noise and input buffering are at odds with one another.

Nonetheless, the excellent dynamics of the AD797 will make it

the preferred choice in many inverting applications, and with care-

ful selection of feedback resistors the noise penalties will be mini-

mal. Some examples are presented in Table II and Figure 37.

R

L

C

L

V

IN

 AD797

**

2

7

3

4

6

**

V

OUT

–V

S

+V

S

 * SEE TEXT

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

R

S

*

R2

R1

Figure 37. Inverting Amplifier Connection

Table III. Values for Inverting Circuit

Noise

Gain

R1

R2

C

L

(Excluding r

S

)

–1

1 k

1 k

20 pF

3.0 nV/

Hz

–1

300 

300 

10 pF

1.8 nV/

Hz

–10

150 

1500 

5 pF

1.8 nV/

Hz

DRIVING CAPACITIVE LOADS

The capacitive load driving capabilities of the AD797 are dis-

played in Figure 38. At gains over 10 usually no special precau-

tions are necessary. If more drive is desirable the circuit in

Figure 39 should be used. Here a 5000 pF load can be driven

cleanly at any noise gain 

 2.

100nF

10nF

1pF

1

10

1k

100

1nF

100pF

10pF

CLOSED-LOOP GAIN

CAPACITIVE LOAD DRIVE CAPABILITY

Figure 38. Capacitive Load Drive Capability vs. Closed

Loop Gain

100

1k

C1

1k

20pF

33

V

IN

 AD797

**

2

7

3

4

6

**

V

OUT

–V

S

+V

S

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

200pF

Figure 39. Recommended Circuit for Driving a High

Capacitance Load

SETTLING TIME

The AD797 is unique among ultralow noise amplifiers in that it

settles to 16 bits (<150 

µ

V) in less than 800 ns. Measuring this

performance presents a challenge. A special test setup (Figure

40) was developed for this purpose. The input signal was ob-

tained from a resonant reed switch pulse generator, available

from Tektronix as calibration Fixture No. 067-0608-00. When

open, the switch is simply 50 

 to ground and settling is purely

a passive pulse decay and inherently flat. The low repetition rate

signal was captured on a digital oscilloscope after being ampli-

fied and clamped twice. The selection of plug-in for the oscillo-

scope was made for minimum overload recovery.

background image

AD797

REV. C

–12–

0.47µF

250Ω

0.47µF

4.26k

1kΩ

100Ω

1kΩ

2x

HP2835

(VIA LESS THAN 1FT

50    COAXIAL CABLE)

V

ERROR

 X 5

1kΩ

20pF

51pF

NOTE:

USE CIRCUIT

BOARD

WITH GROUND

PLANE

1kΩ

TEKTRONIX

CALIBRATION

FIXTURE

VIN

20pF

1M

TO TEKTRONIX

7A26 

OSCILLOSCOPE

PREAMP INPUT

SECTION

 A1

AD797

7

4

6

–VS

+VS

1µF

0.1µF

1µF

0.1µF

3

2

 A2

AD829

7

4

6

–VS

+VS

3

2

2x

HP2835

226

Figure 40. Settling Time Test Circuit

DISTORTION REDUCTION

The AD797 has distortion performance (THD < –120 dB, @

20 kHz, 3 V rms, R

L

 = 600 

) unequaled by most voltage

feedback amplifiers.

At higher gains and higher frequencies THD will increase due

to reduction in loop gain. However in contrast to most conven-

tional voltage feedback amplifiers the AD797 provides two effec-

tive means of reducing distortion, as gain and frequency are

increased; cancellation of the output stage’s distortion and gain

bandwidth enhancement by decompensation. By applying these

techniques gain bandwidth can be increased to 450 MHz at

G = 1000 and distortion can be held to –100 dB at 20 kHz for

G = 100.

The unique design of the AD797 provides for cancellation of the

output stage’s distortion (patent pending). To achieve this a ca-

pacitance equal to the effective compensation capacitance, usu-

ally 50 pF, is connected between Pin 8 and the output (C2 in

Figure 41). Use of this feature will improve distortion perfor-

mance when the closed loop gain is more than 10 or when fre-

quencies of interest are greater than 30 kHz.

Bandwidth enhancement via decompensation is achieved by

connecting a capacitor from Pin 8 to ground (C1 in Figure 41)

effectively subtracting from the value of the internal compensa-

tion capacitance (50 pF), yielding a smaller effective compensa-

tion capacitance and, therefore, a larger bandwidth. The

benefits of this begin at closed loop gains of 100 and up. A

maximum value of 

33 pF at gains of 1000 and up is recom-

mended. At a gain of 1000 the bandwidth is 450 kHz.

Table IV and Figure 42 summarize the performance of the

AD797 with distortion cancellation and decompensation.

R1

V

IN

R2

50pF

 AD797

2

8

3

6

a.

C1, SEE TABLE

C2 = 50pF – C1

R1

V

IN

R2

 AD797

2

8

3

6

C1

C2

b.

Figure 41. Recommended Connections for Distortion

Cancellation and Bandwidth Enhancement

Table IV. Recommended External Compensation

    A/B

              A                               B

R1

R2

C1

C2

3 dB

C1

C2 3 dB

(pF)

BW

(pF)

BW

G = 10

909 100

0

50

6 MHz

0

50 6 MHz

G = 100

1 k

10

0

50

1 MHz

15

33 1.5 MHz

G = 1000 10 k 10

0

50

110 kHz

33

15 450 kHz

–80

300k

–120

300

100

–110

–100

–90

100k

30k

10k

3k

1k

FREQUENCY – Hz

THD – dB

0.01

0.003

0.001

0.0003

0.0001

THD – %

NOISE LIMIT, G=1000

NOISE LIMIT, G=100

G=1000

R

L

=10k

G=1000

R

L

=600

G=10

R

L

=600

G=100

R

L

=600

Figure 42. Total Harmonic Distortion (THD) vs. Frequency

@ 3 V rms for Figure 41b

background image

AD797

REV. C

–13–

Differential Line Receiver

The differential receiver circuit of Figure 43 is useful for many

applications from audio to MRI imaging. It allows extraction of

a low level signal in the presence of common-mode noise. As

shown in Figure 44, the AD797 provides this function with only

9 nV/

Hz

 noise at the output. Figure 45 shows the AD797’s

20-bit THD performance over the audio band and 16-bit accu-

racy to 250 kHz.

20pF

USE POWER SUPPLY

BYPASSING SHOWN IN

FIGURE 32.

**

 AD797

1k

+V

S

**

**

–V

S

1k

2

3

6

7

4

8

1k

DIFFERENTIAL

INPUT

20pF

OUTPUT

50pF*

*OPTIONAL

1k

Figure 43. Differential Line Receiver

16

6

10M

12

8

100

10

10

14

1M

100k

10k

1k

FREQUENCY — Hz

OUTPUT VOLTAGE NOISE — nV/   Hz

Figure 44. Output Voltage Noise Spectral Density for

Differential Line Receiver

A General Purpose ATE/Instrumentation Input/Output

Driver

The ultralow noise and distortion of the AD797 may be com-

bined with the wide bandwidth, slew rate, and load drive of a

current feedback amplifier to yield a very wide dynamic range

general purpose driver. The circuit of Figure 46 combines the

AD797 with the AD811 in just such an application. Using the

–90

–130

300k

–120

300

100

–110

–100

100k

30k

10k

3k

1k

0.003

0.0003

0.001

THD – %

THD – dB

FREQUENCY – Hz

WITH 

OPTIONAL

50C

N

MEASUREMENT

LIMIT

WITHOUT

OPTIONAL

50pF C

N

0.0001

Figure 45. Total Harmonic Distortion (THD) vs. Frequency

for Differential Line Receiver

component values shown, this circuit is capable of better than

–90 dB THD with a 

±

5 V, 500 kHz output signal. The circuit is

therefore suitable for driving high resolution A/D converters and

as an output driver in automatic test equipment (ATE) systems.

Using a 100 kHz sine wave, the circuit will drive a 600 

 load to

a level of 7 V rms with less than –109 dB THD, and a 10 k

load at less than –117 dB THD.

1k

USE POWER SUPPLY

BYPASSING SHOWN IN

FIGURE 32.

**

INPUT

22pF

OUTPUT

–V

S

2k

649

649

R2

–V

S

 AD797

**

2

7

3

4

6

**

+V

S

 AD811

**

2

7

3

4

6

**

+V

S

2

Figure 46. A General Purpose ATE/lnstrumentation Input/

Output Driver

background image

AD797

REV. C

–14–

100M

1k

100

100

0

60

20

40

80

10M

1M

100k

10k

FREQUENCY – Hz

VOLTAGE NOISE – 

µ

Vrms (0.1Hz – Freq)

V

OUT

 – dB Re 1V/

µ

A

–80

–30

–50

–70

–60

–40

NOISE

V

OUT

Figure 49. Total Integrated Voltage Noise & V

OUT

 of

Amorphous Detector Preamp

Professional Audio Signal Processing—DAC Buffers

The low noise and low distortion of the AD797 make it an ideal

choice for professional audio signal processing. An ideal I-to-V

converter for a current output DAC would simply be a resistor

to ground, were it not for the fact that most DACs do not oper-

ate linearly with voltage on their output. Standard practice is to

operate an op amp as an I-to-V converter creating a virtual

ground at its inverting input. Normally, clock energy and cur-

rent steps must be absorbed by the op amp’s output stage.

However, in the configuration of Figure 50, Capacitor C

F

shunts high frequency energy to ground, while correctly repro-

ducing the desired output with extremely low THD and IMD.

C1

2000pF

C

F

82pF

3k

 AD797

**

2

7

3

4

6

**

–V

S

+V

S

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

100

AD1862

DAC

Figure 50. A Professional Audio DAC Buffer

Figure 51. Offset Null Configuration

Ultrasound/Sonar Imaging Preamp

The AD600 variable gain amplifier provides the time controlled

gain (TCG) function necessary for very wide dynamic range so-

nar and low frequency ultrasound applications. Under some cir-

cumstances, it is necessary to buffer the input of the AD600 to

preserve its low noise performance. To optimize dynamic range

this buffer should have at most 6 dB of gain. The combination

of low noise and low gain is difficult to achieve. The input

buffer circuit shown in Figure 47 provides 1 nV/

Hz

 noise per-

formance at a gain of two (dc to 1 MHz) by using 26.1 

 resistors

in its feedback path. Distortion is only –50 dBc @ 1 MHz at a

2 volt p-p output level and drops rapidly to better than

–70 dBc at an output level of 200 mV p-p.

26.1Ω

INPUT

7

4

3

2

AD797

**

**

AD600

**

**

6

26.1Ω

V

OUT

V

S

 = ±6Vdc

+V

S

–V

S

 * USE POWER SUPPLY

** BYPASSING SHOWN IN FIGURE 32.

Figure 47. An Ultrasound Preamplifier Circuit

Amorphous (Photodiode) Detector

Large area photodiodes C

S

 

 500 pF and certain image detec-

tors (amorphous Si), have optimum performance when used in

conjunction with amplifiers with very low voltage rather than

very low current noise. Figure 48 shows the AD797 used with

an amorphous Si (C

S

 = 1000 pF) detector. The response is ad-

justed for flatness using capacitor C

L

, while the noise is domi-

nated by voltage noise amplified by the ac noise gain. The 797’s

excellent input noise performance gives 27 

µ

V rms total noise in

a 1 MHz bandwidth, as shown by Figure 49.

50pF

C

S

I

S

1000pF

10k

 AD797

**

2

7

3

4

6

**

–V

S

+V

S

** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.

C

L

100

Figure 48. Amorphous Detector Preamp

background image

AD797

REV. C

–15–

AUDIO 

AMPLIFIERS

PRECISION

AD797

AD OP27

AD OP37

OP27

OP37

OP227 (Dual)

OP270 (Dual)

OP271 (Dual)

OP275 (Dual)

OP467 (Quad)

OP470 (Quad)

OP471 (Quad)

AD797

OP275

SSM2015

SSM2016

SSM2017

SSM2134

SSM2139

High Output

Current

AD797

OP50

FET INPUT

AD645

AD743

AD795

AD796 (Dual)

Faster

(Slew Rate    230 V/µs)

Fast

AD745

FAST

LOW

POWER

LOW V  

AD645

AD795

AD796 (Dual)

AD548

AD795

OP80

AD648 (Dual)

AD796 (Dual)

Lower V  

AD743

ELECTROMETER

AD711

AD712 (Dual)

OP249 (Dual)

AD713 (Quad)

Faster

AD744

OP42

OP44

AD746 (Dual)

Faster

(Slew Rate     8 V/µs)

OP282 (Dual)

OP482 (Quad)

Faster

AD745

Low

Power

OP80

AD549

General

Purpose

AD515A

AD545A

AD546

Lowest I

        60 fA Max

BIAS

N

N

OPERATIONAL AMPLIFIERS

LOW NOISE

FAST

(Slew Rate     45 V/µs)

OP61

OP467 (Quad)

AD829

AD840

AD844

AD846

AD848

AD849

AD5539

Ultrafast

(Slew Rate     1000 V/µs)

AD810

AD811

AD844

AD9610

AD9617

AD9618

ULTRALOW V

0.9 nV/   Hz

AD797

N

PRECISION

AD548

AD795

AD820

AD648 (Dual)

AD796 (Dual)

AD822 (Dual)

LOW VOLTAGE NOISE – V

N  

(V

N

     10 nV/  Hz @ 1 kHz)

≤ 

LOW CURRENT NOISE –  I

N

LOW INPUT BIAS CURRENT – I

BIAS

(I

N

     10 fA/   Hz @ 1 kHz, I

BIAS  

   100 pA)

background image

AD797

REV. C

–16–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Cerdip (Q) Package*

0.005 (0.13) MIN

0.055 (1.4) MAX

0.405 (10.29) MAX

0.150 

(3.81) 

MIN

0.200

 (5.08)

MAX

0.310 (7.87)

0.220 (5.59)

0.070 (1.78)

0.030 (0.76)

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.320 (8.13)

0.290 (7.37)

0   - 15   

0.015 (0.38)

0.008 (0.20)

0.100 (2.54)

BSC

SEATING PLANE

0.060 (1.52)

0.015 (0.38)

4

1

5

8

Plastic Mini-DIP

(N) Package

0.125 (3.18)

MIN

0.165 ± 0.01

(4.19 ± 0.25)

0.39 (9.91)

MAX

0.25

(6.35)

4

5

8

1

0.035 ± 0.01

(0.89 ± 0.25)

0.018 ± 0.003

(0.46 ± 0.08)

0.30 (7.62)

REF

0  - 15   

0.10

(2.54)

TYP

0.011 ± 0.003

(4.57 ± 0.76)

SEATING PLANE

0.31

(7.87)

0.18 ± 0.03

(4.57 ± 0.76)

0.033 

(0.84)

NOM

8-Pin SOIC (R) Package

0.181 (4.60)

0.205 (5.20)

0.020 (0.50)

0.045 (1.15)

0.007 (0.18)

0.015 (0.38)

0.053 (1.35)

0.069 (1.75)

0.004 (0.10)

0.010 (0.25)

1

4

5

8

0.188 (4.77)

0.198 (5.03)

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.200)

0.014 (0.36)

0.018 (0.46)

0.050 (1.27)

TYP

*See military data sheet for 883B specifications.

C1677–24–6/92

PRINTED IN U.S.A.


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