background image

KM416C1000B, KM416C1200B

CMOS  DRAM

KM416V1000B, KM416V1200B

This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory

cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-5,-6 or -7), power

consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-

before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This

1Mx16 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power

consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines. 

¡Ü

 

  Part Identification

    

     - KM416C1000B/B-L (5V, 4K Ref.)

     - KM416C1200B/B-L (5V, 1K Ref.)

     - KM416V1000B/B-L (3.3V, 4K Ref.)

     - KM416V1200B/B-L (3.3V, 1K Ref.)

¡Ü

 

  Fast Page Mode operation

¡Ü

 

  2 CAS Byte/Word Read/Write operation

¡Ü

 

  CAS-before-RAS refresh capability

¡Ü

 

  RAS-only and Hidden refresh capability

¡Ü

 

  Self-refresh capability (L-ver only)

¡Ü

 

  TTL(5V)/LVTTL(3.3V) compatible inputs and outputs 

¡Ü

 

  Early Write or output enable controlled write 

¡Ü

 

  JEDEC Standard pinout

¡Ü

 

  Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)

    400mil packages 

¡Ü

 

  Single +5V

¡¾

10% power supply (5V product) 

¡Ü

 

  Single +3.3V

¡¾

0.3V power supply (3.3V product) 

Control

Clocks

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Row Decoder

Column Decoder

Lower

Data out

Buffer

RAS

UCAS

LCAS

W

Vcc

Vss

DQ0

to

DQ7

A0-A11

(A0 - A9)

*1

A0 - A7

(A0 - A9)

*1

Memory Array

1,048,576 x16

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

1M x 16Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

¡Ü

 

  Refresh Cycles

Part

NO.

V

CC

Refresh

cycle

Refresh period

Normal

L-ver

C1000B

5V

4K

64ms

128ms

V1000B

3.3V

C1200B

5V

1K

16ms

V1200B

3.3V

¡Ü

 

  Perfomance Range

Speed

t

RAC

t

CAC

t

RC

t

PC

Remark

-5

50ns

15ns

90ns

35ns

5V/3.3V

-6

60ns

15ns

110ns

40ns

5V/3.3V

-7

70ns

20ns

 130ns

45ns

5V/3.3V

¡Ü

 

  Active Power Dissipation 

Speed

3.3V

5V

4K

1K

4K

1K

-5

396

576

605

880

-6

360

540

550

825

-7

324

504

495

770

Unit : mW

S

e

n

s

e

 A

m

p

s

 &

 I

/O

Upper

Data in

Buffer

Upper

Data out

Buffer

Lower

Data in

Buffer

DQ8

to

DQ15

OE

Note)

 *1 

: 1K Refresh

background image

KM416C1000B, KM416C1200B

CMOS  DRAM

KM416V1000B, KM416V1200B

V

CC

DQ0

DQ1

DQ2

DQ3

V

CC

DQ4

DQ5

DQ6

DQ7

N.C

N.C

N.C

W

RAS

*A11(N.C)

*A10(N.C)

A0

A1

A2

A3

V

CC

V

SS

DQ15

DQ14

DQ13

DQ12

V

SS

DQ11

DQ10

DQ9

DQ8

N.C

N.C

LCAS

UCAS

OE

A9

A8

A7

A6

A5

A4

V

SS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

PIN CONFIGURATION   (Top Views)

¡Ü

 

  KM416C/V10(2)00BT

Pin Name

Pin Function

A0 - A11

Address Inputs (4K Product)

A0 - A9

Address Inputs (1K Product)

DQ0 - 15

Data In/Out

V

SS

Ground

RAS

Row Address Strobe

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

W

Read/Write Input

OE

Data Output Enable

V

CC

Power(+5V)

Power(+3.3V)

N.C

No Connection

¡Û

¡Û

V

CC

DQ0

DQ1

DQ2

DQ3

V

CC

DQ4

DQ5

DQ6

DQ7

N.C

N.C

W

RAS

*A11(N.C)

*A10(N.C)

A0

A1

A2

A3

V

CC

V

SS

DQ15

DQ14

DQ13

DQ12

V

SS

DQ11

DQ10

DQ9

DQ8

N.C

LCAS

UCAS

OE

A9

A8

A7

A6

A5

A4

V

SS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

¡Ü

 

  KM416C/V10(2)00BJ

¡Û

¡Û

*A10 and A11 are N.C for KM416C/V1200B(5V/3.3V, 1K Ref. product)

J : 400mil 42 SOJ

T : 400mil 50(44) TSOP II

background image

KM416C1000B, KM416C1200B

CMOS  DRAM

KM416V1000B, KM416V1200B

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

  Parameter

Symbol

Rating

Units

3.3V

5V

Voltage on any pin relative to V

SS

V

IN,

V

OUT

 

-0.5  to  +4.6

-1.0  to  +7.0

V

Voltage on V

CC

 supply relative to V

SS

V

CC

 

-0.5  to  +4.6

-1.0  to  +7.0

V

Storage Temperature

Tstg

-55  to  +150

-55  to  +150

¡É

Power Dissipation

P

D

1

1

W

Short Circuit Output Current

I

OS

 

50

50

mA

RECOMMENDED OPERATING CONDITIONS 

(Voltage referenced to Vss, T

A

= 0 to 70

¡É

)

*1 : V

CC

+1.3V/15ns(3.3V), V

CC

+2.0V/20ns(5V), Pulse width is measured at V

CC

*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V

SS

  Parameter

Symbol

3.3V

5V

Units

Min

Typ

Max

Min

Typ

Max

Supply Voltage

V

CC

 

3.0

3.3

3.6

4.5

5.0

5.5

V

Ground

V

SS

 

0

0

0

0

0

0

V

Input High Voltage

V

IH

2.0

-

V

CC

+0.3

*1

2.4

-

V

CC

+1.0

*1

V

Input Low Voltage

V

IL

-0.3

*2

-

0.8

-1.0

*2

-

0.8

V

DC AND OPERATING CHARACTERISTICS 

(Recommended operating conditions unless otherwise noted.)

Max

  Parameter

Symbol

Min

Max

Units

3.3V

Input Leakage Current (Any input 0

¡Â

V

IN

¡Â

V

IN

+0.3V,

all other input pins not under test=0 Volt)

I

I(L)

-5

5

uA

Output Leakage Current 

(Data out is disabled, 0V

¡Â

V

OUT

¡Â

V

CC

)

I

O(L)

-5

5

uA

Output High Voltage Level(I

OH

=-2mA)

V

OH

2.4

-

V

Output Low Voltage Level(I

OL

=2mA)

V

OL

-

0.4

V

5V

Input Leakage Current (Any input 0

¡Â

V

IN

¡Â

V

IN

+0.5V,

all other input pins not under test=0 Volt)

I

I(L)

-5

5

uA

Output Leakage Current 

(Data out is disabled, 0V

¡Â

V

OUT

¡Â

V

CC

)

I

O(L)

-5

5

uA

Output High Voltage Level(I

OH

=-5mA)

V

OH

2.4

-

V

Output Low Voltage Level(I

OL

=4.2mA)

V

OL

-

0.4

V

background image

KM416C1000B, KM416C1200B

CMOS  DRAM

KM416V1000B, KM416V1200B

*Note :

I

CC1

, I

CC3

, I

CC4

 and I

CC6 

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

I

CC

 is specified as an average current. In I

CC1

, I

CC3

 and I

CC6,

 address can be changed maximum once while RAS=V

IL

. In I

CC4

,

address can be changed maximum once within one fast page mode cycle time, 

t

PC

.

DC AND OPERATING CHARACTERISTICS 

(Continued)

I

CC1

* : Operating Current (RAS and UCAS, LCAS cycling @

t

RC

=min.)

I

CC2

  : Standby Current (RAS=UCAS=LCAS=W=V

IH

)

I

CC3

* : RAS-only Refresh Current (UCAS=LCAS=V

IH

, RAS cycling @

t

RC

=min.)

I

CC4

* : Fast Page Mode Current (RAS=V

IL

, UCAS or LCAS, Address cycling @

t

PC

=min.)

I

CC5

  : Standby Current (RAS=UCAS=LCAS=W=V

CC

-0.2V)

I

CC6

* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @

t

RC

=min.)

I

CC7

  : Battery back-up current, Average power supply current, Battery back-up mode

          Input high voltage(V

IH

)=V

CC

-0.2V, Input low voltage(V

IL

)=0.2V, UCAS, LCAS=0.2V,

          Din=Don't care, T

RC

=31.25us(4K/L-ver), 125us(1K/L-ver),

          T

RAS

=T

RAS

min~300ns

I

CCS

  : Self Refresh Current 

          RAS=UCAS=LCAS=V

IL

, W=OE=A0 ~ A11=V

CC

-0.2V or 0.2V, 

          DQ0 ~ DQ15=V

CC

-0.2V,  0.2V or Open 

Symbol

Power

Speed

Max

Units

KM416V1000B

KM416V1200B

KM416C1000B

KM416C1200B

I

CC1

Don't care

-5

-6

-7

110

100

90

160

150

140

110

100

90

160

150

140

mA

mA

mA

I

CC2

Normal

L

Don't care

2

1

2

1

2

1

2

1

mA

mA

I

CC3

Don't care

-5

-6

-7

110

100

90

160

150

140

110

100

90

160

150

140

mA

mA

mA

I

CC4

Don't care

-5

-6

-7

100

90

80

100

90

80

100

90

80

100

90

80

mA

mA

mA

I

CC5

Normal

L

Don't care

1

200

1

200

1

200

1

200

mA

uA

I

CC6

Don't care

-5

-6

-7

110

100

90

160

150

140

110

100

90

160

150

140

mA

mA

mA

I

CC7

L

Don't care

400

300

450

350

uA

I

CCS

L

Don't care

200

200

250

250

uA

background image

KM416C1000B, KM416C1200B

CMOS  DRAM

KM416V1000B, KM416V1200B

CAPACITANCE

 (T

A

=25

¡É

, V

CC

=5V or 3.3V, f=1MHz)

  Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A11]

C

IN1

 

-

5

pF

Input capacitance [RAS, UCAS, LCAS, W, OE]

C

IN2

 

-

7

pF

Output capacitance [DQ0 - DQ15]

C

DQ

-

7

pF

Test condition (5V device) : V

CC

=5.0V

¡¾

10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V

Parameter

Symbol

-5

-6

-7

Units

Notes

Min

Max

Min

Max

Min

Max

Random read or write cycle time

t

RC

90

110

130

ns

Read-modify-write cycle time

t

RWC

133

155

185

ns

Access time from RAS 

t

RAC

50

60

70

ns

3,4,9

Access time from CAS 

t

CAC 

15

15

20

ns

3,4

Access time from column address

t

AA

25

30

35

ns

3,9

CAS to output in Low-Z

t

CLZ

0

0

0

ns

3

Output buffer turn-off delay

t

OFF

0

13

0

15

0

20

ns

5

Transition time (rise and fall)

t

T

3

50

3

50

3

50

ns

2

RAS precharge time

t

RP

30

40

50

ns

RAS pulse width

t

RAS

50

10K

60

10K

70

10K

ns

RAS hold time

t

RSH

13

15

20

ns

CAS hold time

t

CSH

50

60

70

ns

CAS pulse width

t

CAS

13

10K

15

10K

20

10K

ns

RAS to CAS delay time

t

RCD

20

37

20

45

20

50

ns

4

RAS to column address delay time

t

RAD

15

25

15

30

15

35

ns

9

CAS to RAS precharge time

t

CRP

5

5

5

ns

Row address set-up time

t

ASR

0

0

0

ns

Row address hold time

t

RAH

10

10

10

ns

Column address set-up time

t

ASC

0

0

0

ns

10

Column address hold time 

t

CAH

10

10

15

ns

10

Column address to RAS lead time

t

RAL

25

30

35

ns

Read command set-up time

t

RCS

0

0

0

ns

Read command hold time referenced to CAS

t

RCH

0

0

0

ns

7

Read command hold time referenced to RAS

t

RRH

0

0

0

ns

7

Write command hold time

t

WCH

10

10

15

ns

Write command pulse width

t

WP

10

10

15

ns

Write command to RAS lead time

t

RWL

15

15

20

ns

Write command to CAS lead time

t

CWL

13

15

20

ns

AC CHARACTERISTICS 

(0

¡É¡Â

T

A

¡Â

70

¡É

, See note 1,2)

Test condition (3.3V device) : V

CC

=3.3V

¡¾

0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

background image

KM416C1000B, KM416C1200B

CMOS  DRAM

KM416V1000B, KM416V1200B

AC CHARACTERISTICS 

(Continued)

Parameter

Symbol

-5

-6

-7

Units

Notes

Min

Max

Min

Max

Min

Max

Data set-up time

t

DS

0

0

0

ns

8,16

Data hold time

t

DH

10

10

15

ns

8,16

Refresh period (1K, Normal) 

t

REF

16

16

16

ms

Refresh period (4K, Normal) 

t

REF

64

64

64

ms

Refresh period (L-ver)

t

REF

128

128

128

ms

Write command set-up time

t

WCS

0

0

0

ns

6

CAS to W delay time

t

CWD

36

40

50

ns

6,12

RAS to W delay time

t

RWD

73

85

95

ns

6

Column address to W delay time

t

AWD

48

55

60

ns

6

CAS precharge to W delay time

t

CPWD

53

60

65

ns

6

CAS set-up time (CAS -before-RAS refresh)

t

CSR

5

5

5

ns

14

CAS hlod time (CAS -before-RAS refresh)

t

CHR

10

10

15

ns

15

RAS to CAS precharge time

t

RPC

5

5

5

ns

CAS precharge time (CBR counter test cycle)

t

CPT

20

20

25

ns

Access time from CAS precharge

t

CPA

30

35

40

ns

3

Fast Page mode cycle time

t

PC

35

40

45

ns

Fast Page read-modify-write cycle time

t

PRWC

76

80

95

ns

CAS precharge time (Fast Page cycle)

t

CP

10

10

10

ns

11

RAS pulse width (Fast Page cycle)

t

RASP

50

200K

60

200K

70

200K

ns

RAS hold time from CAS precharge

t

RHCP

30

35

40

ns

OE access time

t

OEA

13

15

20

ns

3

OE to data delay

t

OED

13

15

20

ns

Output buffer turn off delay time from OE

t

OEZ

0

13

0

15

0

20

ns

OE command hold time

t

OEH

13

15

20

ns

RAS pulse width (C-B-R  self refresh)

t

RASS

100

100

100

us

17

RAS precharge time (C-B-R self refresh)

t

RPS

90

110

130

ns

17

CAS hold time (C-B-R self refresh)

t

CHS

-50

-50

-50

ns

17

background image

KM416C1000B, KM416C1200B

CMOS  DRAM

KM416V1000B, KM416V1200B

NOTES

An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is

achieved.

Input voltage levels are Vih/Vil. V

IH

(min) and V

IL

(max) are reference levels for measuring timing of input signals. 

Transition times are measured between V

IH

(min) and V

IL

(max) and are assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.

Operation within the 

t

RCD

(max) limit insures that 

t

RAC

(max) can be met. 

t

RCD

(max) is specified as a reference point only. 

If 

t

RCD

 is greater than the specified 

t

RCD

(max) limit, then access time is controlled exclusively by 

t

CAC

.

This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V

oh

 or V

ol

.

t

WCS

t

RWD

t

CWD

,  

t

AWD  

and  

t

CPWD

 are non restrictive operating parameters. They are included in the data sheet as electrical

characteristics only. If 

t

WCS

¡Ã

t

WCS

(min), the cycles is an early write cycle and the data output will remain high impedance for

the duration of the cycle. If 

t

CWD

¡Ã

t

CWD

(min), 

t

RWD

¡Ã

t

RWD

(min), 

t

AWD

¡Ã

t

AWD

(min) and 

t

CPWD

¡Ã

t

CPWD

(min), then the cycle is a

read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above condi-

tions is satisfied, the condition of the data out is indeterminate.

Either 

t

RCH

 or 

t

RRH

 must be satisfied for a read cycle.

These parameters are referenced to the CAS leading edge in ealy write cycles and to the W falling edge in OE controlled write

cycle and read-modify-write cycles.

Operation within the 

t

RAD

(max) limit insures that 

t

RAC

(max) can be met. 

t

RAD

(max) is specified as a reference point only. If

t

RAD

 is greater than the specified 

t

RAD

(max) limit, then access time is controlled by 

t

AA

.

KM416C/V10(2)00B/BL Truth Table

RAS

LCAS

UCAS

W

OE

DQ0 - DQ7

DQ8-DQ15

STATE

H

X

X

X

X

Hi-Z

Hi-Z

Standby

L

H

H

X

X

Hi-Z

Hi-Z

Refresh

L

L

H

H

L

DQ-OUT

Hi-Z

Byte Read

L

H

L

H

L

Hi-Z

DQ-OUT

Byte Read

L

L

L

H

L

DQ-OUT

DQ-OUT

Word Read

L

L

H

L

H

DQ-IN

-

Byte Write

L

H

L

L

H

-

DQ-IN

Byte Write

L

L

L

L

H

DQ-IN

DQ-IN

Word Write

L

L

L

H

H

Hi-Z

Hi-Z

-

7.

6.

5.

9.

8.

3.

2.

1.

4.

background image

KM416C1000B, KM416C1200B

CMOS  DRAM

KM416V1000B, KM416V1200B

t

ASC

t

CAH

 are referenced to the earlier CAS rising edge.

t

CP

 is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.

t

CWD

 is referenced to the later CAS falling edge at word read-modify-write cycle.

t

CWL

 is specified from W falling edge to the earlier CAS rising edge.

t

CSR

 is referenced to earlier CAS falling low before RAS transition low.

t

CHR

 is referenced to the later CAS rising high after RAS transition low.

t

CSR

t

CHR

RAS

LCAS

UCAS

16.

15.

14.

11.

13.

12.

17.

t

DS, 

t

DH 

 is independently specified for lower byte D

IN

(0-7), upper byte D

IN

(8-15) 

4096(4K Ref.)/1024(1K Ref.) of burst refresh must be executed within 16ms before and after self-refresh in order to meet

refresh specification (L-version).

10.