background image

 

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Members of the Texas Instruments

SCOPE

 Family of Testability Products

D

Members of the Texas Instruments

Widebus

 Family

D

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

D

UBT  

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup Resistors

D

B-Port Outputs of ABTH182504A Devices

Have Equivalent 25-

 Series Resistors, So

No External Resistors Are Required

D

State-of-the-Art 

EPIC-

ΙΙ

 BiCMOS Design

D

One Boundary-Scan Cell Per I/O

Architecture Improves Scan Efficiency

D

SCOPE 

 Instruction Set

–  IEEE Standard 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

–  Parallel-Signature Analysis at Inputs

–  Pseudo-Random Pattern Generation

From Outputs

–  Sample Inputs/Toggle Outputs

–  Binary Count From Outputs

–  Device Identification

–  Even-Parity Opcodes

D

Packaged in 64-Pin Plastic Thin Quad Flat

(PM) Packages Using 0.5-mm

Center-to-Center Spacings and 68-Pin

Ceramic Quad Flat (HV) Packages Using

25-mil Center-to-Center Spacings

 

B5

B6

B7

GND

B8

B9

B10

V

CC

NC

B11

B12

B13

B14

GND

B15

B16

B17

A4

A5

A6

GND

A7

A8

A9

A10

NC

V

CC

A11

A12

A13

GND

A14

A15

A16

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

V

NC

TMS

CLKBA

A3

A2

A1

GND

OEBA

LEBA

TDO

NC

TCK

LEAB

OEAB

A19

GND

A20

CLKENAB

CLKAB

TDI

A17

CLKENBA

B1

GND

B20

B19

B18

GND

B2

B4

28 29 30 31 32 33 34

8 7

6

5

4

9

3

1 68 67

2

35 36 37 38 39

66 65

27

64 63 62 61

40 41 42 43

SN54ABTH18504A, SN54ABTH182504A . . . HV PACKAGE

(TOP VIEW)

CC

NC – No internal connection

CC

V

A18

B3

Copyright 

©

 1996, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, UBT, and EPIC-

ΙΙ

B are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

18 19

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

20

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

21 22 23 24

63 62 61 60 59

64

58

56 55 54

57

25 26 27 28 29

53 52

17

51 50 49

30 31 32

A1

GND

LEBA

TDO

A3

A2

OEBA

V

CLKENBA

B1

B2

B3

TMS

CLKBA

GND

B4

A19

GND

CLKENAB

CLKAB

A17

A18

A20

TDI

LEAB

OEAB

B20

B19

V

TCK

GND

B18

A4

A5

A6

GND

A7

A8

A9

A10

V

CC

A11

A12

A13

GND

A14

A15

A16

B5

B6

B7

GND

B8

B9

B10

V

CC

B11

B12

B13

B14

GND

B15

B16

B17

CC

CC

SN74ABTH18504A, SN74ABTH182504A . . . PM PACKAGE

(TOP VIEW)

description

The ’ABTH18504A and ’ABTH182504A scan test devices with 20-bit universal bus transceivers are members

of the Texas Instruments SCOPE

 testability integrated-circuit family. This family of devices supports IEEE

Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to

the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type

flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the

TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the

boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the

SCOPE

 universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the

device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while

CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and

CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs

are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to

A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE

 universal bus transceivers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry

performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

description (continued)

Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data

output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing

functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation

(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin

architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A

PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count

addressing scheme is useful.

Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.

The B-port outputs of ’ABTH182504A, which are designed to source or sink up to 12 mA, include 25-

 series

resistors to reduce overshoot and undershoot.

The SN54ABTH18504A and SN54ABTH182504A are characterized for operation over the full military

temperature range of –55

°

C to 125

°

C. The SN74ABTH18504A and SN74ABTH182504A are characterized for

operation from –40

°

C to 85

°

C.

FUNCTION TABLE†

(normal mode, each register)

INPUTS

OUTPUT

OEAB

LEAB

CLKENAB

CLKAB

A

B

L

L

L

L

X

B0‡

L

L

L

L

L

L

L

L

H

H

L

L

H

X

X

B0‡

L

H

X

X

L

L

L

H

X

X

H

H

H

X

X

X

X

Z

† A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,

LEBA, CLKENBA, and CLKBA.

‡ Output level before the indicated steady-state input conditions were

established

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

functional block diagram

A1

1D

C1

1D

C1

1D

C1

1D

C1

Boundary-Control

Register

Bypass Register

Identification

Register

Boundary-Scan Register

Instruction

Register

TAP

Controller

CLKENAB

LEAB

OEAB

CLKENBA

LEBA

OEBA

TDI

TMS

TCK

B1

TDO

VCC

VCC

1 of 20 Channels

CLKAB

CLKBA

53

58

22

27

23

28

54

59

55

60

62

24

56

26

VCC

VCC

Pin numbers shown are for the PM package.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Terminal Functions

TERMINAL NAME

DESCRIPTION

A1–A20

Normal-function A-bus I/O ports. See function table for normal-mode logic.

B1–B20

Normal-function B-bus I/O ports. See function table for normal-mode logic.

CLKAB, CLKBA

Normal-function clock inputs. See function table for normal-mode logic.

CLKENAB, CLKENBA

Normal-function clock enables. See function table for normal-mode logic.

GND

Ground

LEAB, LEBA

Normal-function latch enables. See function table for normal-mode logic.

OEAB, OEBA

Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal

forces the terminal to a high level if left unconnected.

TCK

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are

synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting

data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left

unconnected.

TDO

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting

data through the instruction register or selected data register.

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through

its TAP controller states. An internal pullup forces TMS to a high level if left unconnected.

VCC

Supply voltage

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard

1149.1-1990. All test instructions, test data, and test control signals are passed along this serial-test bus. The

TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the

synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip

control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and

output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully

one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan

architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the

device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit

boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H

TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.

The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller

proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in

the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive

TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and

one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset

and is disabled so that the normal logic function of the device is performed. The instruction register is reset to

an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data

registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more

than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected

or if a board defect causes it to be open circuited.

For the ’ABTH18504A and ’ABTH182504A, the instruction register is reset to the binary value 10000001, which

selects the IDCODE instruction. Bits 47–46 in the boundary-scan register are reset to logic 1, ensuring that

these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked

the outputs would be at high-impedance state). Reset values of other bits in the boundary-scan register should

be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the

PSA test operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test

operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.

Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test

operations selected by the boundary-control register are performed while the TAP controller is in the

Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits

either of these states on the next TCK cycle. These states allow the selection of either data-register scan or

instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the

Capture-DR state, the selected data register can capture a data value as specified by the current instruction.

Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the

Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the

first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic

level present in the least-significant bit of the selected data register.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Shift-DR (continued)

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.

The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during

the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).

The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return

to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling

edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain

indefinitely. The Pause-DR state can suspend and resume data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such update occurs

on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In

the Capture-IR state, the instruction register captures its current status value. This capture operation occurs

on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’ABTH18504A and

’ABTH182504A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and

on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to

the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK

cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs

during the TCK cycle, in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to

Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to

return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the

first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain

indefinitely. The Pause-IR state can suspend and resume instruction-register scan operations without loss

of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the

Update-IR state.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

register overview

With the exception of the bypass and device-identification registers, any test register can be thought of as a

serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that

they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,

Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current

instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted

out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or

Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information

contained in the instruction includes the mode of operation (either normal mode, in which the device performs

its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation

to be performed, which of the four data registers is to be selected for inclusion in the scan path during

data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 3 lists the instructions supported by the ’ABTH18504A and ’ABTH182504A. The even-parity feature

specified for SCOPE

 devices is supported in these devices. Bit 7 of the instruction opcode is the parity bit.

Any instructions that are defined for SCOPE

 devices but are not supported by these devices default to

BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted

out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value

that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated

and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the

binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDO

TDI

Bit 7

Parity

(MSB)

Bit 0

(LSB)

Figure 2. Instruction Register Order of Scan

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

10

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 DALLAS, TEXAS 75265

data register description

boundary-scan register

The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each

normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and

output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins,

and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at

the device input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The

contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or

in Test-Logic-Reset, BSCs 47–46 are reset to logic 1, ensuring that these cells, which control A-port and B-port

outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at high-impedance state).

Reset values of other BSCs should be considered indeterminate.

The BSR order of scan is from TDI through bits 47–0 to TDO. Table 1 shows the BSR bits and their associated

device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

47

OEAB

39

A20-I/O

19

B20-I/O

46

OEBA

38

A19-I/O

18

B19-I/O

45

CLKAB

37

A18-I/O

17

B18-I/O

44

CLKBA

36

A17-I/O

16

B17-I/O

43

CLKENAB

35

A16-I/O

15

B16-I/O

42

CLKENBA

34

A15-I/O

14

B15-I/O

41

LEAB

33

A14-I/O

13

B14-I/O

40

LEBA

32

A13-I/O

12

B13-I/O

––

––

31

A12-I/O

11

B12-I/O

––

––

30

A11-I/O

10

B11-I/O

––

––

29

A10-I/O

9

B10-I/O

––

––

28

A9-I/O

8

B9-I/O

––

––

27

A8-I/O

7

B8-I/O

––

––

26

A7-I/O

6

B7-I/O

––

––

25

A6-I/O

5

B6-I/O

––

––

24

A5-I/O

4

B5-I/O

––

––

23

A4-I/O

3

B4-I/O

––

––

22

A3-I/O

2

B3-I/O

––

––

21

A2-I/O

1

B2-I/O

––

––

20

A1-I/O

0

B1-I/O

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boundary-control register

The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run

(RUNT) instruction to implement additional test operations not included in the basic SCOPE

 instruction set.

Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that

are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is

reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.

Bit 0

(LSB)

TDO

TDI

Bit 1

Bit 2

(MSB)

Figure 3. Boundary-Control Register Order of Scan

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,

reducing the number of bits per test pattern that must be applied to complete a test operation. During

Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.

Bit 0

TDO

TDI

Figure 4. Bypass Register Order of Scan

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device-identification register

The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,

part number, and version of this device.

For the ’ABTH18504A , the binary value 00000000000000101000000000101111 (0002802F, hex) is captured

(during Capture-DR state) in the IDR to identify this device as Texas Instruments SN54/74ABTH18504A.

For the ’ABTH182504A , the binary value 00000000000000101100000000101111 (0002C02F, hex) is captured

(during Capture-DR state) in the IDR to identify this device as Texas Instruments SN54/74ABTH182504A.

The IDR order of scan is from TDI through bits 31–0 to TDO. Table 2 shows the IDR bits and their significance.

Table 2. Device-Identification Register Configuration

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

31

VERSION3

27

PARTNUMBER15

11

MANUFACTURER10†

30

VERSION2

26

PARTNUMBER14

10

MANUFACTURER09†

29

VERSION1

25

PARTNUMBER13

9

MANUFACTURER08†

28

VERSION0

24

PARTNUMBER12

8

MANUFACTURER07†

––

––

23

PARTNUMBER11

7

MANUFACTURER06†

––

––

22

PARTNUMBER10

6

MANUFACTURER05†

––

––

21

PARTNUMBER09

5

MANUFACTURER04†

––

––

20

PARTNUMBER08

4

MANUFACTURER03†

––

––

19

PARTNUMBER07

3

MANUFACTURER02†

––

––

18

PARTNUMBER06

2

MANUFACTURER01†

––

––

17

PARTNUMBER05

1

MANUFACTURER00†

––

––

16

PARTNUMBER04

0

LOGIC1†

––

––

15

PARTNUMBER03

––

––

––

––

14

PARTNUMBER02

––

––

––

––

13

PARTNUMBER01

––

––

––

––

12

PARTNUMBER00

––

––

† Note that for TI products, bits 11–0 of the device-identification register always contain the binary value 000000101111

(02F, hex).

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instruction-register opcode description

The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of

each instruction.

Table 3. Instruction-Register Opcodes

BINARY CODE†

BIT 7

 BIT 0

MSB 

 LSB

SCOPE OPCODE

DESCRIPTION

SELECTED

DATA REGISTER

MODE

00000000

EXTEST

Boundary scan

Boundary scan

Test

10000001

IDCODE

Identification read

Device identification

Normal

10000010

SAMPLE/PRELOAD

Sample boundary

Boundary scan

Normal

00000011

BYPASS‡

Bypass scan

Bypass

Normal

10000100

BYPASS‡

Bypass scan

Bypass

Normal

00000101

BYPASS‡

Bypass scan

Bypass

Normal

00000110

HIGHZ

Control boundary to high impedance

Bypass

Modified test

10000111

CLAMP

Control boundary to 1/0

Bypass

Test

10001000

BYPASS‡

Bypass scan

Bypass

Normal

00001001

RUNT

Boundary run test

Bypass

Test

00001010

READBN

Boundary read

Boundary scan

Normal

10001011

READBT

Boundary read

Boundary scan

Test

00001100

CELLTST

Boundary self test

Boundary scan

Normal

10001101

TOPHIP

Boundary toggle outputs

Bypass

Test

10001110

SCANCN

Boundary-control register scan

Boundary control

Normal

00001111

SCANCT

Boundary-control register scan

Boundary control

Test

All others

BYPASS

Bypass scan

Bypass

Normal

† Bit 7 is used to maintain even parity in the 8-bit instruction.

‡ The BYPASS instruction is executed in lieu of a SCOPE

 instruction that is not supported in the ’ABTH18504A or ’ABTH182504A.

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST instruction. The BSR is selected in the

scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has

been scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at

the device pins, except for output-enables, is passed through the BSCs to the normal on-chip logic. For I/O pins,

the operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 47–46

of the BSR). When a given output enable is active (logic 0), the associated I/O pins operate in the output mode.

Otherwise, the I/O pins operate in the input mode. The device operates in the test mode.

identification read

This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the

scan path. The device operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is

selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured

in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs

associated with I/O pins in the output mode. The device operates in the normal mode.

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bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in the normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device

input pins remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O

BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode.

boundary-run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during

Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),

PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up

(PSA/COUNT).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This

instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.

In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and

shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising

edge of TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device I/O pins on

each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at

the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This

operation must be performed before a RUNT operation to specify which test operation is to be executed.

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boundary-control register opcode description

The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed

while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation

of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 

 BIT 0

MSB 

 LSB

DESCRIPTION

X00

Sample inputs/toggle outputs (TOPSIP)

X01

Pseudo-random pattern generation/40-bit mode (PRPG)

X10

Parallel-signature analysis /40-bit mode (PSA)

011

Simultaneous PSA and PRPG /20-bit mode (PSA/PRPG)

111

Simultaneous PSA and binary count up /20-bit mode (PSA/COUNT)

While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,

the output-enable BSCs (bits 47–46 of the BSR) control the drive state (active or high impedance) of the selected

device output pins. These BCR instructions are valid only when the device is operating in one direction of data

flow (that is, OEAB 

 OEBA). Otherwise, the bypass instruction is operated.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the

associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode

BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated

device I/O pins on each falling edge of TCK.

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pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge

of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each

falling edge of TCK. Figures 5 and 6 show the 40-bit linear-feedback shift-register algorithms through which the

patterns are generated. An initial seed value should be scanned into the BSR before performing this operation.

A seed value of all zeroes does not produce additional patterns.

=

B8-I/O

B7-I/O

B6-I/O

B5-I/O

B4-I/O

B3-I/O

B2-I/O

B1-I/O

B10-I/O

A7-I/O

A6-I/O

A5-I/O

A4-I/O

A3-I/O

A2-I/O

A1-I/O

A8-I/O

A10-I/O

A17-I/O

A16-I/O

A15-I/O

A14-I/O

A13-I/O

A12-I/O

A11-I/O

A18-I/O

A20-I/O

B18-I/O

B17-I/O

B16-I/O

B15-I/O

B14-I/O

B13-I/O

B12-I/O

B11-I/O

B20-I/O

B9-I/O

A9-I/O

A19-I/O

B19-I/O

Figure 5. 40-Bit PRPG Configuration (OEAB = 0, OEBA = 1)

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=

A8-I/O

A7-I/O

A6-I/O

A5-I/O

A4-I/O

A3-I/O

A2-I/O

A1-I/O

A10-I/O

B7-I/O

B6-I/O

B5-I/O

B4-I/O

B3-I/O

B2-I/O

B1-I/O

B8-I/O

B10-I/O

B17-I/O

B16-I/O

B15-I/O

B14-I/O

B13-I/O

B12-I/O

B11-I/O

B18-I/O

B20-I/O

A18-I/O

A17-I/O

A16-I/O

A15-I/O

A14-I/O

A13-I/O

A12-I/O

A11-I/O

A20-I/O

A9-I/O

B9-I/O

B19-I/O

A19-I/O

Figure 6. 40-Bit PRPG Configuration (OEAB = 1, OEBA = 0)

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parallel-signature analysis (PSA)

Data appearing at the selected device input-mode I/O pins is compressed into a 40-bit parallel signature in the

shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the

selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8

show the 40-bit linear-feedback shift-register algorithms through which the signature is generated. An initial

seed value should be scanned into the BSR before performing this operation.

B8-I/O

B7-I/O

B6-I/O

B5-I/O

B4-I/O

B3-I/O

B2-I/O

B1-I/O

B10-I/O

A7-I/O

A6-I/O

A5-I/O

A4-I/O

A3-I/O

A2-I/O

A1-I/O

A8-I/O

A10-I/O

A17-I/O

A16-I/O

A15-I/O

A14-I/O

A13-I/O

A12-I/O

A11-I/O

A18-I/O

A20-I/O

B18-I/O

B17-I/O

B16-I/O

B15-I/O

B14-I/O

B13-I/O

B12-I/O

B11-I/O

B20-I/O

B9-I/O

A9-I/O

A19-I/O

B19-I/O

=

=

Figure 7. 40-Bit PSA Configuration (OEAB = 0, OEBA = 1)

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A8-I/O

A7-I/O

A6-I/O

A5-I/O

A4-I/O

A3-I/O

A2-I/O

A1-I/O

A10-I/O

B7-I/O

B6-I/O

B5-I/O

B4-I/O

B3-I/O

B2-I/O

B1-I/O

B8-I/O

B10-I/O

B17-I/O

B16-I/O

B15-I/O

B14-I/O

B13-I/O

B12-I/O

B11-I/O

B18-I/O

B20-I/O

A18-I/O

A17-I/O

A16-I/O

A15-I/O

A14-I/O

A13-I/O

A12-I/O

A11-I/O

A20-I/O

A9-I/O

B9-I/O

B19-I/O

A19-I/O

=

=

Figure 8. 40-Bit PSA Configuration (OEAB = 1, OEBA = 0)

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simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the

shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, a 20-bit

pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on each

rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling

edge of TCK. Figures 9 and 10 show the 20-bit linear-feedback shift-register algorithms through which the

signature and patterns are generated. An initial seed value should be scanned into the BSR before performing

this operation. A seed value of all zeroes does not produce additional patterns.

B8-I/O

B7-I/O

B6-I/O

B5-I/O

B4-I/O

B3-I/O

B2-I/O

B1-I/O

B10-I/O

A7-I/O

A6-I/O

A5-I/O

A4-I/O

A3-I/O

A2-I/O

A1-I/O

A8-I/O

A10-I/O

A17-I/O

A16-I/O

A15-I/O

A14-I/O

A13-I/O

A12-I/O

A11-I/O

A18-I/O

A20-I/O

B18-I/O

B17-I/O

B16-I/O

B15-I/O

B14-I/O

B13-I/O

B12-I/O

B11-I/O

B20-I/O

B9-I/O

A9-I/O

A19-I/O

B19-I/O

=

=

Figure 9. 20-Bit PSA/PRPG Configuration (OEAB = 0, OEBA = 1)

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A8-I/O

A7-I/O

A6-I/O

A5-I/O

A4-I/O

A3-I/O

A2-I/O

A1-I/O

A10-I/O

A9-I/O

=

=

A18-I/O

A17-I/O

A16-I/O

A15-I/O

A14-I/O

A13-I/O

A12-I/O

A11-I/O

A20-I/O

A19-I/O

B7-I/O

B6-I/O

B5-I/O

B4-I/O

B3-I/O

B2-I/O

B1-I/O

B8-I/O

B10-I/O

B9-I/O

B17-I/O

B16-I/O

B15-I/O

B14-I/O

B13-I/O

B12-I/O

B11-I/O

B18-I/O

B20-I/O

B19-I/O

Figure 10. 20-Bit PSA/PRPG Configuration (OEAB = 1, OEBA = 0)

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simultaneous PSA and binary count up (PSA/COUNT)

Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the

shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, a 20-bit

binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on each

rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling

edge of TCK. Figures 11 and 12 show the 20-bit linear-feedback shift-register algorithms through which the

signature is generated. An initial seed value should be scanned into the BSR before performing this operation.

B8-I/O

B7-I/O

B6-I/O

B5-I/O

B4-I/O

B3-I/O

B2-I/O

B1-I/O

B10-I/O

A7-I/O

A6-I/O

A5-I/O

A4-I/O

A3-I/O

A2-I/O

A1-I/O

A8-I/O

A10-I/O

A17-I/O

A16-I/O

A15-I/O

A14-I/O

A13-I/O

A12-I/O

A11-I/O

A18-I/O

A20-I/O

B18-I/O

B17-I/O

B16-I/O

B15-I/O

B14-I/O

B13-I/O

B12-I/O

B11-I/O

B20-I/O

B9-I/O

A9-I/O

A19-I/O

B19-I/O

=

=

MSB

LSB

Figure 11. 20-Bit PSA/COUNT Configuration (OEAB = 0, OEBA = 1)

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A8-I/O

A7-I/O

A6-I/O

A5-I/O

A4-I/O

A3-I/O

A2-I/O

A1-I/O

A10-I/O

A9-I/O

=

=

A18-I/O

A17-I/O

A16-I/O

A15-I/O

A14-I/O

A13-I/O

A12-I/O

A11-I/O

A20-I/O

A19-I/O

B7-I/O

B6-I/O

B5-I/O

B4-I/O

B3-I/O

B2-I/O

B1-I/O

B8-I/O

B10-I/O

B9-I/O

B17-I/O

B16-I/O

B15-I/O

B14-I/O

B13-I/O

B12-I/O

B11-I/O

B18-I/O

B20-I/O

B19-I/O

MSB

LSB

Figure 12. 20-Bit PSA/COUNT Configuration (OEAB = 1, OEBA = 0)

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timing description

All test operations of the ’ABTH18504A and ’ABTH182504A are synchronous to the TCK signal. Data on the

TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and

normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as

shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge

to TCK.

A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the

Test-Logic-Reset state and is advanced through its states, to perform one instruction-register scan and one

data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used

to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 details the

operation of the test circuitry during each TCK cycle.

Table 5. Explanation of Timing Example

TCK

CYCLE(S)

TAP STATE

AFTER TCK

DESCRIPTION

1

Test-Logic-Reset

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward

the desired state.

2

Run-Test/Idle

3

Select-DR-Scan

4

Select-IR-Scan

5

Capture-IR

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the

Capture-IR state.

6

Shift-IR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP

on the rising edge of TCK as the TAP controller advances to the next state.

7–13

Shift-IR

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value

11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned

out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next

TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

14

Exit1-IR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

15

Update-IR

The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.

16

Select-DR-Scan

17

Capture-DR

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the

Capture-DR state.

18

Shift-DR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP

on the rising edge of TCK as the TAP controller advances to the next state.

19–20

Shift-DR

The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

21

Exit1-DR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

22

Update-DR

In general, the selected data register is updated with the new data on the falling edge of TCK.

23

Select-DR-Scan

24

Select-IR-Scan

25

Test-Logic-Reset

Test operation completed

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ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

T

est-Logic-Reset

Run-T

est/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Update-IR

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Update-DR

Select-DR-Scan

Select-IR-Scan

T

est-Logic-Reset

TCK

TMS

TDI

TDO

ÎÎ

ÎÎ

TAP

Controller

State

3-State (TDO) or Don’t Care (TDI)

Figure 13. Timing Example

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

: except I/O ports (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

I/O ports (see Note 1) 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high state or power-off state, V

O

 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . 

Current into any output in the low state, I

O

: SN54ABTH18504A 96 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN54ABTH182504A (A port or TDO) 

96 mA

. . . . . . . . . . . . . . . . . 

SN54ABTH182504A (B port) 

30 mA

. . . . . . . . . . . . . . . . . . . . . . . . 

SN74ABTH18504A 128 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ABTH182504A (A port or TDO) 

128 mA

. . . . . . . . . . . . . . . . 

SN74ABTH182504A (B port) 

30 mA

. . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK 

(V

< 0) 

–18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK 

(V

< 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 576 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through GND 

1152 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Maximum power dissipation at T

A

 = 55

°

C (in still air) (see Note 2):PM package 

1 W

. . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150

°

C and a board trace length of 75 mils.

For more information, refer to the 

Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data

Book, literature number SCBD002.

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recommended operating conditions

SN54ABTH18504A

SN74ABTH18504A

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High-level output current

–24

–32

mA

IOL

Low-level output current

48

64

mA

t/

v

Input transition rise or fall rate

10

10

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

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electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABTH18504A

SN74ABTH18504A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

–1.2

–1.2

V

VCC = 4.5 V,

IOH = –3 mA

2.5

2.5

2.5

VOH

VCC = 5 V,

IOH = –3 mA

3

3

3

V

VOH

VCC = 4 5 V

IOH = –24 mA

2

2

V

VCC = 4.5 V

IOH = – 32 mA

2*

2

VOL

VCC = 4 5 V

IOL = 48 mA

0.55

0.55

V

VOL

VCC = 4.5 V

IOL = 64 mA

0.55*

0.55

V

II

CLK,  CLKEN,

LE, TCK

VCC = 0 to 5.5 V,

VI = VCC or GND

±

1

±

1

±

1

µ

A

I

A or B ports

VCC = 5.5 V, VI = VCC or GND

±

20

±

20

±

20

µ

IIH

OE, TDI, TMS

VCC = 5.5 V,

VI = VCC

10

10

10

µ

A

IIL

OE, TDI, TMS

VCC = 5.5 V,

VI = GND

–40

–150

–40

–150

–40

–150

µ

A

I

A or B ports

VCC = 4 5 V

VI = 0.8 V

75

220

500

75

500

µ

A

II(hold)‡

A or B ports

VCC = 4.5 V

VI = 2 V

–75

– 180

–500

–75

–500

µ

A

IOZH

TDO

VCC = 2.1 V to 5.5 V,

VO = 2.7 V, OE = 2 V

10

10

10

µ

A

IOZL

TDO

VCC = 2.1 V to 5.5 V,

VO = 0.5 V, OE = 2 V

–10

–10

–10

µ

A

IOZPU

TDO

VCC = 0 to 2.1 V,

VO = 2.7 V or 0.5 V, OE = 0.8 V

±

50

±

50

µ

A

IOZPD

TDO

VCC = 2.1 V to 0,

VO = 2.7 V or 0.5 V, OE = 0.8 V

±

50

±

50

µ

A

Ioff

VCC = 0, VI or VO 

≤ 

4.5 V

±

100

±

100

µ

A

ICEX

Outputs high

VCC = 5.5 V,

VO = 5.5 V

50

50

50

µ

A

IO§

VCC = 5.5 V,

VO = 2.5 V

–50

–110

–200

–50

–200

–50

–200

mA

Outputs high

VCC = 5.5 V,

1.6

2.2

2.2

2.2

ICC

Outputs low

VCC = 5.5 V,

IO = 0,

A or B ports

19

27

27

27

mA

ICC

Outputs

disabled

VI = VCC or

GND

A or B  orts

0.9

2

2

2

mA

ICC¶

VCC = 5.5 V, One input at 3.4 V,

Other inputs at VCC or GND

1.5

1.5

1.5

mA

Ci

Control inputs

VI = 2.5 V or 0.5 V

5

pF

Cio

A or B ports

VO = 2.5 V or 0.5 V

10

pF

Co

TDO

VO = 2.5 V or 0.5 V

8

pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.

† All typical values are at VCC = 5 V.

‡ The parameter II(hold) includes the off-state output leakage current.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

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timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)

SN54ABTH18504A

SN74ABTH18504A

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

CLKAB or CLKBA

0

100

0

100

MHz

t

Pulse duration

CLKAB or CLKBA high or low

4.5

4.5

ns

tw

Pulse duration

LEAB or LEBA

CLK high or low

3.5

3.5

ns

A before CLKAB

 or B before CLKBA

3.5

3.5

t

Setup time

A before LEAB

or B before LEBA

CLK high

3.5

3.5

ns

tsu

Setup time

A before LEAB

 or B before LEBA

CLK low

2

2

ns

CLKEN before CLK

4

4

A after CLKAB

 or B after CLKBA

0.5

0.5

th

Hold time

A after LEAB

 or B after LEBA

CLK high or low

4

4

ns

CLKEN after CLK

0.5

0.5

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

SN54ABTH18504A

SN74ABTH18504A

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

TCK

0

50

0

50

MHz

tw

Pulse duration

TCK high or low

8

8

ns

A, B, CLK, LE, or OE before TCK

6

6

tsu

Setup time

TDI before TCK

4.5

4.5

ns

TMS before TCK

3

3

A, B, CLK, LE, or OE after TCK

1.5

1.5

th

Hold time

TDI after TCK

1

1

ns

TMS after TCK

1.5

1.5

td

Delay time

Power up to TCK

50

50

ns

tr

Rise time

VCC power up

1

1

µ

s

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

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switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

SN54ABTH18504A

SN74ABTH18504A

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fmax

CLKAB or

CLKBA

100

130

100

100

MHz

tPLH

A or B

B or A

1.5

3.1

5

1.5

6

1.5

5.5

ns

tPHL

A or B

B or A

1.5

3.6

5

1.5

6

1.5

5.5

ns

tPLH

CLKAB or

B or A

1.5

3.7

5

1.5

6

1.5

5.5

ns

tPHL

CLKBA

B or A

1.5

3.8

5

1.5

6

1.5

5.5

ns

tPLH

LEAB or LEBA

B or A

1.5

3.9

5.5

1.5

6.5

1.5

6

ns

tPHL

LEAB or LEBA

B or A

1.5

3.6

5.5

1.5

6.5

1.5

6

ns

tPZH

OEAB or OEBA

B or A

1.5

4.6

5.8

1.5

7.5

1.5

7

ns

tPZL

OEAB or OEBA

B or A

1.5

4.8

5.8

1.5

7.5

1.5

7

ns

tPHZ

OEAB or OEBA

B or A

3

7.1

8.4

3

9.9

3

9.6

ns

tPLZ

OEAB or OEBA

B or A

2

5

6.3

2

8.9

2

7.2

ns

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

SN54ABTH18504A

SN74ABTH18504A

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fmax

TCK

50

90

50

50

MHz

tPLH

TCK

A or B

2.5

7.4

11

2.5

14.5

2.5

13.1

ns

tPHL

TCK

A or B

2.5

7.6

10.8

2.5

14

2.5

12.4

ns

tPLH

TCK

TDO

2

3.8

5.1

2

7

2

5.6

ns

tPHL

TCK

TDO

2

4

5.1

2

7

2

5.6

ns

tPZH

TCK

A or B

4

8

11.5

4

14.5

4

13.4

ns

tPZL

TCK

A or B

4

8

11.8

4

15

4

13.6

ns

tPZH

TCK

TDO

2

3.9

5.7

2

7.5

2

6.6

ns

tPZL

TCK

TDO

2

4.2

6.2

2

8

2

6.9

ns

tPHZ

TCK

A or B

4

10.8

13

4

18

4

15

ns

tPLZ

TCK

A or B

3

9.1

13.3

3

17.5

3

15

ns

tPHZ

TCK

TDO

3

5.3

6.8

3

8

3

7.2

ns

tPLZ

TCK

TDO

2.5

4.2

5.5

2.5

8

2.5

6.3

ns

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

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recommended operating conditions

SN54ABTH182504A

SN74ABTH182504A

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High level output current

A port, TDO

–24

–32

mA

IOH

High-level output current

B port

–12

–12

mA

IOL

Low level output current

A port, TDO

48

64

mA

IOL

Low-level output current

B port

12

12

mA

t/

v

Input transition rise or fall rate

10

10

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

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electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABTH182504A

SN74ABTH182504A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

–1.2

–1.2

V

VCC = 4.5 V,

IOH = –3 mA

2.5

2.5

2.5

A port TDO

VCC = 5 V,

IOH = –3 mA

3

3

3

A port, TDO

VCC = 4 5 V

IOH = –24 mA

2

2

VOH

VCC = 4.5 V

IOH = –32 mA

2*

2

V

VOH

VCC = 4.5 V,

IOH = –1 mA

3.35

3.3

3.35

V

B port

VCC = 5 V,

IOH = –1 mA

3.85

3.8

3.85

B port

VCC = 4 5 V

IOH = –3 mA

3.1

3

3.1

VCC = 4.5 V

IOH = –12 mA

2.6*

2.6

A port TDO

VCC = 4 5 V

IOL = 48 mA

0.55

0.55

VOL

A port, TDO

VCC = 4.5 V

IOL = 64 mA

0.55*

0.55

V

VOL

B port

VCC = 4 5 V

IOL = 8 mA

0.8

0.8

0.65

V

B port

VCC = 4.5 V

IOL = 12 mA

0.8*

0.8

II

CLK, CLKEN,

LE, TCK

VCC = 0 to 5.5 V,

VI = VCC or GND

±

1

±

1

±

1

µ

A

II

A or B ports

VCC = 5.5 V,

VI = VCC or GND

±

20

±

20

±

20

µ

A

IIH

OE, TDI, TMS

VCC = 5.5 V,

VI = VCC

10

10

10

µ

A

IIL

OE, TDI, TMS

VCC = 5.5 V,

VI = GND

–40

–150

–40

–150

–40

–150

µ

A

I

A or B ports

VCC = 4 5 V

VI = 0.8 V

75

220

500

75

500

µ

A

II(hold)‡

A or B ports

VCC = 4.5 V

VI = 2 V

–75

–180

–500

–75

–500

µ

A

IOZH

TDO

VCC = 2.1 V to 5.5 V,

VO = 2.7 V, OE = 2 V

10

10

10

µ

A

IOZL

TDO

VCC = 2.1 V to 5.5 V,

VO = 0.5 V, OE = 2 V

–10

–10

–10

µ

A

IOZPU

TDO

VCC = 0 to 2.1 V,

VO = 2.7 V or 0.5 V,

OE = 0.8 V

±

50

±

50

µ

A

IOZPD

TDO

VCC = 2.1 V to 0,

VO = 2.7 V or 0.5 V,

OE = 0.8 V

±

50

±

50

µ

A

Ioff

VCC = 0, VI or VO 

≤ 

4.5 V

±

100

±

100

µ

A

ICEX

Outputs high

VCC = 5.5 V,

VO = 5.5 V

50

50

50

µ

A

IO§

A port, TDO

VCC = 5.5 V,

VO = 2.5 V

–50

–110

–200

–50

–200

–50

–200

mA

IO§

B port

VCC = 5.5 V,

VO = 2.5 V

–25

–55

–100

–25

–100

–25

–100

mA

Outputs high

VCC = 5.5 V,

1.4

2.2

2.2

2.2

ICC

Outputs low

VCC = 5.5 V,

IO = 0,

A or B ports

25

30

30

30

mA

ICC

Outputs

disabled

VI = VCC or

GND

A or B  orts

0.9

2

2

2

mA

* On products compliant to MIL-PRF-38535, this parameter does not apply.

† All typical values are at VCC = 5 V.

‡ The parameter II(hold) includes the off-state output leakage current.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

32

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABTH182504A

SN74ABTH182504A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

ICC‡

VCC= 5.5 V,

One input at 3.4 V,

Other inputs at VCC or GND

1.5

1.5

1.5

mA

Ci

Control inputs

VI = 2.5 V or 0.5 V

5

pF

Cio

A or B ports

VO = 2.5 V or 0.5 V

10

pF

Co

TDO

VO = 2.5 V or 0.5 V

8

pF

† All typical values are at VCC = 5 V.

‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)

SN54ABTH182504A

SN74ABTH182504A

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

CLKAB or CLKBA

0

100

0

100

MHz

t

Pulse duration

CLKAB or CLKBA high or low

4.5

4.5

ns

tw

Pulse duration

LEAB or LEBA

CLK high or low

3.5

3.5

ns

A before CLKAB

 or B before CLKBA

3.5

3.5

t

Setup time

A before LEAB

 or

CLK high

3.5

3.5

ns

tsu

Setup time

A before LEAB

 or

B before LEBA

CLK low

2

2

ns

CLKEN before CLK

4

4

A after CLKAB

 or B after CLKBA

0.5

0.5

th

Hold time

A after LEAB

 or B after LEBA

CLK high or low

4

4

ns

CLKEN after CLK

0.5

0.5

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

SN54ABTH182504A

SN74ABTH182504A

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

TCK

0

50

0

50

MHz

tw

Pulse duration

TCK high or low

8

8

ns

A, B, CLK, LE, or OE before TCK

6

6

tsu

Setup time

TDI before TCK

4.5

4.5

ns

TMS before TCK

3

3

A, B, CLK, LE, or OE after TCK

1.5

1.5

th

Hold time

TDI after TCK

1

1

ns

TMS after TCK

1.5

1.5

td

Delay time

Power up to TCK

50

50

ns

tr

Rise time

VCC power up

1

1

µ

s

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

33

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

SN54ABTH182504A

SN74ABTH182504A

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fmax

CLKAB or

CLKBA

100

130

100

100

MHz

tPLH

A

B

1.5

3.5

5

1.5

6

1.5

5.5

ns

tPHL

A

B

1.5

4.1

5.6

1.5

6.4

1.5

6.2

ns

tPLH

B

A

1.5

3.2

5

1.5

6

1.5

5.5

ns

tPHL

B

A

1.5

3.4

5

1.5

6

1.5

5.5

ns

tPLH

CLKAB

B

1.5

3.9

5.4

1.5

6.2

1.5

6.1

ns

tPHL

CLKAB

B

1.5

4.2

5.8

1.5

6.4

1.5

6.2

ns

tPLH

CLKBA

A

1.5

4

5

1.5

6

1.5

5.5

ns

tPHL

CLKBA

A

1.5

4.2

5

1.5

6

1.5

5.5

ns

tPLH

LEAB

B

1.5

4.1

5.6

1.5

6.5

1.5

6.3

ns

tPHL

LEAB

B

1.5

4.1

5.6

1.5

6.5

1.5

6.2

ns

tPLH

LEBA

A

1.5

4.1

5.5

1.5

6.5

1.5

6

ns

tPHL

LEBA

A

1.5

3.9

5.5

1.5

6.5

1.5

6

ns

tPZH

OEAB or OEBA

B or A

1.5

4.5

5.8

1.5

7.5

1.5

7

ns

tPZL

OEAB or OEBA

B or A

1.5

4.5

5.8

1.5

7.5

1.5

7

ns

tPHZ

OEAB or OEBA

B or A

3

5.5

8.4

3

9.9

3

9.6

ns

tPLZ

OEAB or OEBA

B or A

2

4.6

6.3

2

8.9

2

7.2

ns

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

SN54ABTH182504A

SN74ABTH182504A

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fmax

TCK

50

90

50

50

MHz

tPLH

TCK

A or B

2.5

6.8

11

2.5

14.5

2.5

13.1

ns

tPHL

TCK

A or B

2.5

7.2

10.8

2.5

14

2.5

12.4

ns

tPLH

TCK

TDO

2

3.6

5.1

2

7

2

5.6

ns

tPHL

TCK

TDO

2

3.8

5.1

2

7

2

5.6

ns

tPZH

TCK

A or B

4

7.8

11.5

4

14.5

4

13.4

ns

tPZL

TCK

A or B

4

7.8

11.8

4

15

4

13.6

ns

tPZH

TCK

TDO

2

3.7

5.7

2

7.5

2

6.6

ns

tPZL

TCK

TDO

2

3.9

6.2

2

8

2

6.9

ns

tPHZ

TCK

A or B

4

8.6

13

4

18

4

15

ns

tPLZ

TCK

A or B

3

7.9

13.3

3

17.5

3

15

ns

tPHZ

TCK

TDO

3

5.2

6.8

3

8

3

7.2

ns

tPLZ

TCK

TDO

2.5

4

5.5

2.5

8

2.5

6.3

ns

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A

SCAN TEST DEVICES WITH

20-BIT UNIVERSAL BUS TRANSCEIVERS

 

SCBS165C – AUGUST 1993 – REVISED JULY 1996

34

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

th

tsu

From Output

  Under Test

CL = 50 pF

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

1.5 V

tw

Input

(see Note A)

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

[

 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

Figure 14. Load Circuit and Voltage Waveforms

background image

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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Copyright 

©

 1998, Texas Instruments Incorporated