background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

3.3-V Supply Operation

D

10-Bit-Resolution A/D Converter

D

11 Analog Input Channels

D

Three Built-In Self-Test Modes

D

Inherent Sample and Hold

D

Total Unadjusted Error . . .

±

1 LSB Max

D

On-Chip System Clock

D

End-of-Conversion (EOC) Output

D

Pin Compatible With TLC1543

D

CMOS Technology

     

description

The TLV1543C and TLV1543M are CMOS 10-bit,

switched-capacitor, successive-approximation,

analog-to-digital converters. These devices have

three inputs and a 3-state output [chip select (CS),

input-output clock (I/O CLOCK), address input

(ADDRESS), and data output (DATA OUT)] that

provide a direct 4-wire interface to the serial port

of a host processor. The devices allow high-speed

data transfers from the host.

In addition to a high-speed A /D converter and

versatile control capability, these devices have an

on-chip 14-channel multiplexer that can select

any one of 11 analog inputs or any one of three

internal self-test voltages. The sample-and-hold

function is automatic. At the end of A /D conversion, the end-of-conversion (EOC) output goes high to indicate

that conversion is complete. The converter incorporated in the devices features differential high-impedance

reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and

supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air

temperature range.

The TLV1543C is characterized for operation from 0

°

C to 70

°

C. The TLV1543M is characterized for operation

over the full military temperature range of – 55

°

C to 125

°

C.

AVAILABLE OPTIONS

PACKAGE

TA

SMALL

OUTLINE

(DB)

SMALL

OUTLINE

(DW)

CHIP CARRIER

(FK)

CERAMIC DIP

(J)

PLASTIC DIP

(N)

PLASTIC CHIP 

CARRIER

(FN)

0

°

C to 70

°

C

TLV1543CDB

TLV1543CDW

TLV1543CN

TLV1543CFN

– 55

°

C to 125

°

C

TLV1543MFK

TLV1543MJ

Copyright 

©

 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

 

1

2

3

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

A0

A1

A2

A3

A4

A5

A6

A7

A8

GND

V

CC

EOC

I/O CLOCK

ADDRESS 

DATA OUT

CS

REF +

REF –

A10

A9

DB, DW, FK, J, OR N PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

I/O CLOCK

ADDRESS

DATA OUT

CS

REF +

A3

A4

A5

A6

A7

FN PACKAGE

(TOP VIEW)

A2

A1

A0

A10

REF –

EOC

A8

GND

A9

CC

V

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

functional block diagram

14-Channel

Analog

Multiplexer

Sample and

Hold

10-Bit

Analog-to-Digital

Converter

(switched capacitors)

Self-Test

Reference

Output

Data

Register

10-to-1 Data

Selector and

Driver

System Clock,

Control Logic,

and I/O

Counters

Input Address

Register

4

10

10

4

REF +

REF –

DATA

OUT

ADDRESS

I/O CLOCK

CS

3

EOC

1

2

3

4

5

6

7

8

9

11

12

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

14

13

16

19

17

18

15

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 k

Ω 

TYP

Ci = 60 pF TYP

(equivalent input

capacitance)

5 M

Ω 

TYP

A0 – A10

A0 – A10

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

ADDRESS

17

I

Serial address. A 4-bit serial address selects the desired analog input or test voltage that is to be converted

next. The address data is presented with the MSB first and is shifted in on the first four rising edges of I/O

CLOCK. After the four address bits have been read into the address register, ADDRESS is ignored for the

remainder of the current conversion period.

A0 – A10

1– 9, 11,

12

I

Analog signal. The 11 analog inputs are applied to A0 – A10 and are internally multiplexed. The driving source

impedance should be less than or equal to 1 k

.

CS

15

I

Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,

ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges

of the internal system clock.

DATA OUT

16

O

The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS

is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance

state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The

next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next most significant

bit, and the remaining bits are shifted out in order with the LSB appearing on the ninth falling edge of I/O

CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial

interface data transfers of more than ten clocks produce zeroes as the unused LSBs.

EOC

19

O

End of conversion. EOC goes from a high- to a low- logic level on the trailing edge of the tenth I/O CLOCK

and remains low until the conversion is complete and data are ready for transfer.

GND

10

I

The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are

with respect to GND.

I/O CLOCK

18

I

Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following four functions:

1) It clocks the four input address bits into the address register on the first four rising edges of I/O

CLOCK with the multiplex address available after the fourth rising edge.

2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins

charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK.

3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.

4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

REF +

14

I

The upper reference voltage value (nominally VCC) is applied to REF +. The maximum input voltage range

is determined by the difference between the voltage applied to REF + and the voltage applied to the REF –

terminal.

REF –

13

I

The lower reference voltage value (nominally ground) is applied to REF –.

VCC

20

I

Positive supply voltage

detailed description

With chip select (CS) inactive (high), the ADDRESS and  I/O CLOCK inputs are initially disabled and DATA OUT

is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins

with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.

The host then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK.

During this transfer, the host serial interface also receives the previous conversion result from DATA OUT. I/O

CLOCK receives an input sequence that is between 10 and 16 clocks long from the host. The first four I/O clocks

load the address register with the 4-bit address on ADDRESS selecting the desired analog channel and the next

six clocks providing the control timing for sampling the analog input.

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

detailed description (continued)

There are six basic serial interface timing modes that can be used with the device. These modes are determined

by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with

a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer

and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between

conversion cycles, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with

an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with a

16-clock transfer and CS active (low) continuously.

The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and

mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the 16th clock falling edge in mode 6.

The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are

transmitted to the host through DATA OUT. The number of serial clock pulses used also depends on the mode

of operation, but a minimum of ten clock pulses is required for conversion to begin. On the 10th clock falling

edge, the EOC output goes low and returns to the high logic level when conversion is complete and the result

can be read by the host. On the 10th clock falling edge, the internal logic takes DATA OUT low to ensure that

the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.

Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that

can be used, and the timing edge on which the MSB of the previous conversion appears at the output.

Table 1. Mode Operation

MODES

CS

NO. OF

I/O CLOCKS

MSB AT DATA OUT†

TIMING

DIAGRAM

Mode 1

High between conversion cycles

10

CS falling edge

Figure 9

Fast Modes

Mode 2

Low continuously

10

EOC rising edge

Figure 10

Fast Modes

Mode 3

High between conversion cycles

11 to 16‡

CS falling edge

Figure 11

Mode 4

Low continuously

16‡

EOC rising edge

Figure 12

Slow Modes

Mode 5

High between conversion cycles

11 to 16‡

CS falling edge

Figure 13

Slow Modes

Mode 6

Low continuously

16‡

16th clock falling edge

Figure 14

† These edges also initiate serial-interface communication.

‡ No more than 16 clocks should be used.

fast modes

The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is

completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not

begin until the falling edge of the 10th I/O CLOCK.

mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The

falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge

of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.

Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling

edges of the internal system clock.

mode 2: fast mode, CS active (low) continuously, 10-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After

the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then

begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous

conversion to appear immediately on this output.

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks

long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time

plus two falling edges of the internal system clock.

mode 4: fast mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of

EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the

previous conversion to appear immediately on this output.

slow modes

In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow

mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must

occur before the conversion period is complete; otherwise, the device loses synchronization with the host serial

interface, and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must

occur within 9.5

µ

s after the tenth I/O clock falling edge.

mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks

long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time

plus two falling edges of the internal system clock.

mode 6: slow mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of

the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the

MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next

16-clock transfer initiated by the serial interface.

address bits

The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal

(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address

selects one of 14 inputs (11 analog inputs or 3 internal test inputs).

analog inputs and test modes

The 11 analog inputs and the 3 internal test inputs are selected by the 14-channel multiplexer according to the

input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce

input-to-input noise injection resulting from channel switching.

Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six

I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are

applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Table 2. Analog-Channel-Select Address

ANALOG INPUT

SELECTED

VALUE SHIFTED INTO

ADDRESS INPUT

SELECTED

BINARY

HEX

A0

0000

0

A1

0001

1

A2

0010

2

A3

0011

3

A4

0100

4

A5

0101

5

A6

0110

6

A7

0111

7

A8

1000

8

A9

1001

9

A10

1010

A

Table 3. Test-Mode-Select Address

INTERNAL SELF-TEST

VOLTAGE SELECTED†

VALUE SHIFTED INTO

ADDRESS INPUT

OUTPUT RESULT (HEX)‡

VOLTAGE SELECTED†

BINARY

HEX

(

)

V

ref

)

– V

ref–

1011

B

200

ref

)

ref–

2

1011

B

200

Vref –

1100

C

000

Vref +

1101

D

3FF

† Vref+ is the voltage applied to the REF+ input,  and Vref– is the voltage applied to the REF–

input.

‡ The output results shown are the ideal values and vary with the reference stability and with

internal offsets.

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by

examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the

conversion process, the analog input is sampled by closing the S

C

 switch and all S

T

 switches simultaneously.

This action charges all the capacitors to the input voltage.

In the next phase of the conversion process, all S

T

 and S

C

 switches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –)

voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and

the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks

at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF –. If the voltage at the summing

node is greater than the trip point of the threshold detector (approximately one-half the V

CC

 voltage), a bit 0 is

placed in the output register and the 512-weight capacitor is switched to REF –. If the voltage at the summing

node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight

capacitor remains connected to REF + through the remainder of the successive-approximation process. The

process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all

bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the

capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

converter and analog input (continued)

SC

Threshold

Detector

Node 512

REF –

REF+

ST

512

VI

To Output

Latches

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF –

ST

1

1

2

4

8

16

128

256

Figure 1. Simplified Model of the Successive-Approximation System

chip-select operation

The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.

A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device

returns to the initial state (the contents of the output data register remain at the previous conversion result).

Exercise care to prevent CS from being taken low close to completion of conversion because the output data

can be corrupted.

reference voltage inputs

There are two reference inputs used with these devices: REF + and REF –. These voltage values establish the

upper and lower limits of the analog input to produce a full-scale and zero-scale reading respectively. The values

of REF +, REF –, and the analog input should not exceed the positive supply or be lower than GND consistent

with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal

to or higher than REF + and at zero when the input signal is equal to or lower than REF –.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 (see Note 1): TLV1543C 

– 0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

TLV1543M 

– 0.5 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (any input) 

– 0.3 V to V

CC

 + 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 

– 0.3 V to V

CC

 + 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Positive reference voltage, V

ref +

 

V

CC

 + 0.1 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Negative reference voltage, V

ref –

 – 0.1 

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Peak input current (any input) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Peak total input current (all inputs) 

±

30 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

: TLV1543C 

0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

TLV1543M – 55

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

  – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 

260

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to digital ground with REF – and GND wired together (unless otherwise noted).

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage VCC

TLV1543C

3

3.3

5.5

V

Supply voltage, VCC

TLV1543M

3

3.3

3.6

V

Positive reference voltage, Vref + (see Note 2)

VCC

V

Negative reference voltage, Vref – (see Note 2)

0

V

Differential reference voltage, Vref + – Vref – (see Note 2)

2.5

VCC

VCC + 0.2

V

Analog input voltage (see Note 2)

0

VCC

V

High level control input voltage VIH

TLV1543C

VCC = 3 V to 5.5 V

2

V

High-level control input voltage, VIH

TLV1543M

VCC = 3 V to 3.6 V

2

V

Low level control input voltage VIL

TLV1543C

VCC = 3 V to 5.5 V

0.6

V

Low-level control input voltage, VIL

TLV1543M

VCC = 3 V to 3.6 V

0.8

V

Setup time, address bits at data input before I/O CLOCK

, tsu(A) (see Figure 4)

100

ns

Hold time, address bits after I/O CLOCK

, th(A) (see Figure 4)

0

ns

Hold time, CS low after last I/O CLOCK

, th(CS)

0

ns

Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3)

1.425

µ

s

Clock frequency at I/O CLOCK (see Note 4)

TLC1543C

0

1.1

MHz

Clock frequency at I/O CLOCK (see Note 4)

TLC1543M

0

2.1

MHz

Pulse duration, I/O CLOCK high, twH(I/O)

190

ns

Pulse duration, I/O CLOCK low, twL(I/O)

190

ns

Transition time, I/O CLOCK, tt(I/O) (see Note 5)

1

µ

s

Transition time, ADDRESS and CS, tt(CS)

10

µ

s

Operating free air temperature TA

TLV1543C

0

70

°

C

Operating free-air temperature, TA

TLV1543M

– 55

125

°

C

NOTES:

2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + – Vref – ); however,

the electrical specifications are no longer applicable.

3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS

 before responding to control input signals. No attempt should be made to clock in an address until the minimum CS

setup time has elapsed.

4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (

 2 V), at least one I/O clock rising edge (

 2 V) must occur within

9.5 

µ

s.

5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of

normal room temperature, the devices function with input clock transition time as slow as 1 

µ

s for remote data-acquisition

applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, 

V

CC

 = V

ref+

 = 3 V to 5.5 V, I/O

 

CLOCK frequency = 1.1 MHz for the TLV1543C, 

V

CC

 = V

ref+

 = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

TLV1543C

VCC = 3 V,

IOH = – 1.6 mA

2.4

V

VOH High level output voltage

TLV1543C

VCC = 3 V to 5.5 V, IOH = 20 

µ

A

VCC – 0.1

V

VOH High-level output voltage

TLV1543M

VCC = 3 V,

IOH = – 1.6 mA

2.4

V

TLV1543M

VCC = 3 V to 3.6 V, IOH = 20 

µ

A

VCC – 0.1

V

TLV1543C

VCC = 3 V,

IOL = 1.6 mA

0.4

V

VOL Low level output voltage

TLV1543C

VCC = 3 V to 5.5 V, IOL = 20 

µ

A

0.1

V

VOL Low-level output voltage

TLV1543M

VCC = 3 V,

IOL = 1.6 mA

0.4

V

TLV1543M

VCC = 3 V to 3.6 V, IOL = 20 

µ

A

0.1

V

IOZ

Off state (high impedance state) output current

VO = VCC,

CS at VCC

10

µ

A

IOZ

Off-state (high-impedance-state) output current

VO = 0,

CS at VCC

– 10

µ

A

IIH

High-level input current

VI = VCC

0.005

2.5

µ

A

IIL

Low-level input current

VI = 0

– 0.005

– 2.5

µ

A

ICC

Operating supply current

CS at 0 V

0.8

2.5

mA

Selected channel leakage current

Selected channel at VCC, 

Unselected channel at 0 V

1

µ

A

Selected channel leakage current

Selected channel at 0 V, 

Unselected channel at VCC

– 1

µ

A

Maximum static analog reference current into REF +

Vref + = VCC,

Vref – = GND

10

µ

A

Input capacitance Analog inputs

TLV1543C

7

55

pF

Ci

Input capacitance, Analog inputs

TLV1543M

7

pF

Ci

Input capacitance Control inputs

TLV1543C

5

15

pF

Input capacitance, Control inputs

TLV1543M

5

pF

† All typical values are at VCC = 5 V, TA = 25

°

C.

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range, 

V

CC

 = V

ref+

 = 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C,

V

CC

 = V

ref+

 = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

Linearity error (see Note 6)

±

1

LSB

Zero error (see Note 7)

See Note 2

±

1

LSB

Full-scale error (see Note 7)

See Note 2

±

1

LSB

Total unadjusted error (see Note 8)

±

1

LSB

ADDRESS = 1011

512

Self-test output code (see Table 3 and Note 9)

ADDRESS = 1100

0

ADDRESS = 1101

1023

tconv

Conversion time

See Figures 9 – 14

21

µ

s

tc

Total cycle time (access, sample, and conversion)

See Figures 9 – 14

and Note 10

21

+10 I/O

CLOCK

periods

µ

s

tacq

Channel acquisition time (sample)

See Figures 9 – 14

and Note 10

  6

I/O

CLOCK

periods

tv

Valid time, DATA OUT remains valid after I/O CLOCK

See Figure 6

10

ns

td(I/O-DATA)

Delay time, I/O CLOCK

 to DATA OUT valid

See Figure 6

240

ns

td(I/O-EOC)

Delay time, tenth I/O CLOCK

 to EOC

See Figure 7

70

240

ns

td(EOC-DATA) Delay time, EOC

 to DATA OUT (MSB)

See Figure 8

100

ns

tPZH, tPZL

Enable time, CS

 to DATA OUT (MSB driven)

See Figure 3

1.3

µ

s

tPHZ, tPLZ

Disable time, CS

 to DATA OUT (high impedance)

See Figure 3

150

ns

tr(EOC)

Rise time, EOC

See Figure 8

300

ns

tf(EOC)

Fall time, EOC

See Figure 7

300

ns

tr(bus)

Rise time, data bus

See Figure 6

300

ns

tf(bus)

Fall time, data bus

See Figure 6

300

ns

td(I/O-CS)

Delay time, tenth I/O CLOCK

 to CS

 to abort conversion

(see Note 11)

9

µ

s

† All typical values are at TA = 25

°

C.

NOTES:

2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied

to REF – convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + – Vref – ); however,

the electrical specifications are no longer applicable.

6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the

difference between 1111111111 and the converted output for full-scale input voltage.

8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.

9. Both the input address and the output codes are expressed in positive logic.

10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6).

11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock

(1.425 

µ

s) after the transition.

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

11

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

EOC

CL = 50 pF

12 k

DATA OUT

Test Point

VCC

RL = 2.18 k

CL = 100 pF

12 k

Test Point

VCC

RL = 2.18 k

Figure 2. Load Circuits

CS

DATA

OUT

2.4 V

0.4 V

90%

10%

tPZH, tPZL

tPHZ, tPLZ

VIL

2 V

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

ADDRESS

th(A)

VIL

2 V

I/O CLOCK

Address

Valid

tsu(A)

VIL

Figure 4. ADDRESS Setup Voltage Waveforms

Last

Clock

CS

VIL

2 V

VIL

tsu(CS)

VIL

I/O CLOCK

th(CS)

First

Clock

Figure 5. CS and I/O CLOCK Voltage Waveforms

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

12

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

0.4 V

2.4 V

0.4 V

2.4 V

2 V

VIL

I/O CLOCK

DATA OUT

tt(I/O)

VIL

2 V

tr(bus), tf(bus)

td(I/O-DATA)

tv

I/O CLOCK Period

tt(I/O)

VIL

Figure 6. DATA OUT and I/O CLOCK Voltage Waveforms

10th

Clock

VIL

2.4 V

0.4 V

tf(EOC)

td(I/O-EOC)

I/O CLOCK

EOC

Figure 7. I/O CLOCK and EOC Voltage Waveforms

0.4 V

2.4 V

EOC

td(EOC-DATA)

Valid MSB

DATA OUT

0.4 V

2.4 V

tr(EOC)

Figure 8. EOC and DATA OUT Voltage Waveforms

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

13

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Hi-Z State

1

2

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

EOC

(see Note A)

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS

 before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup

time has elapsed.

Figure 9. Timing for 10-Clock Transfer Using CS

ÎÎÎ

ÎÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Low Level

1

2

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

EOC

Initialize

(see Note A)

Must be High on Power Up

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS

 before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup

time has elapsed.

Figure 10. Timing for 10-Clock Transfer Not Using CS

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

14

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system

clock after CS

 before responding to control input signals. No attempt should be made to clock in an address until the minimum CS

setup time has elapsed.

B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of

the internal system clock.

ÎÎÎ

ÎÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

1

2

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

EOC

Initialize

ÏÏÏ

ÏÏÏ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

Low

Level

Hi-Z

See Note B

11

16

(see Note A)

(see Note A)

Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)

ÎÎÎ

ÎÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Low Level

1

2

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

EOC

Initialize

Must be High on Power Up

14

15

16

See Note B

(see Note A)

ÎÎÎ

ÎÎÎ

NOTES: A. The first I/O CLOCK must occur after the rising edge of EOC.

B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of

the internal system clock.

Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

15

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system

clock after CS

 before responding to control input signals. No attempt should be made to clock in an address until the minimum

chip CS setup time has elapsed.

B. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial

interface synchronization.

ÎÎÎ

ÎÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

1

2

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

EOC

Initialize

11

ÏÏÏ

ÏÏÏ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

Hi-Z State

16

See Note B

ÏÏÏ

ÏÏÏ

Low

Level

(see Note A)

Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎÎ

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

1

2

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

EOC

Must be High on Power Up

14

15

16

See Note B

See Note A

Low Level

Access Cycle B

(see Note A)

Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)

NOTES: A. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial

interface synchronization.

B. The I/O CLOCK sequence is exactly 16 clock pulses long.

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

16

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

1000000000

0111111111

0000000010

0000000001

0000000000

1111111110

0

0.0096

2.4528

2.4576

2.4624

Digital Output Code

1000000001

1111111101

1111111111

4.9056

4.9104

4.9152

512

511

2

1

0

1022

Step

513

1021

1023

0.0024

VI – Analog Input Voltage – V

VZ T = VZS + 1/2 LSB

VZS

See Notes A and B

4.9080

0.0048

VF T = VFS – 1/2 LSB

VFS

NOTES: A. This curve is based on the assumption that Vref + and Vref – have been adjusted so that the voltage at the transition from digital

0 to 1 (VZ T) is 0.0024 V and the transition to full scale (VF T) is 4.908 V. 1 LSB = 4.8 mV.

B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS)

is the step whose nominal midstep value equals zero.

Figure 15. Ideal Conversion Characteristics

Processor

Control

Circuit

Analog

Inputs

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

I/O CLOCK

CS

ADDRESS

DATA OUT

EOC

REF +

REF –

GND

TLV1543

To Source

Ground

3-V DC Regulated

1

2

3

4

5

6

7

8

9

11

12

15

18

17

16

19

14

13

10

Figure 16. Serial Interface

background image

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

 

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

17

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

simplified analog input analysis

Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to V

S

within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

V

C

 = V

S

 1– e

– t

c

/R

t

C

i

(        

)

(1)

where

R

t

 = R

s

 + r

i

The final voltage to 1/2 LSB is given by

(2)

V

C

 (1/2 LSB) = V

S

 – (V

S

/2048)

Equating equation 1 to equation 2 and solving for time t

c

 gives

V

S

  – (V

S

/2048) = V

S

  1– e

(        

)

(3)

– t

c

/R

t

C

i

and

t

c

 (1/2 LSB) = R

t

 

×

 C

i

 

×

 ln(2048)

(4)

Therefore, with the values given the time for the analog input signal to settle is

(5)

t

c

 (1/2 LSB) = (R

s

 + 1 k

×

 60 pF 

×

 ln(2048)

This time must be less than the converter sample time shown in the timing diagrams.

Rs

ri

VS

VC

50 pF MAX

1 k

 MAX

Driving Source†

TLV1543

Ci

VI

VI = Input Voltage at A0 – A10

VS = External Driving Source Voltage

Rs = Source Resistance

ri = Input Resistance

Ci = Input Capacitance

† Driving source requirements:

Noise and distortion for the source must be equivalent to the

resolution of the converter.

Rs must be real at the input frequency.

Figure 17. Equivalent Input Circuit Including the Driving Source

background image

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

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