background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Maximum Throughput  . . . 200 KSPS

D

Built-In Conversion Clock

D

INL/DNL: 

±

1 LSB Max, SINAD: 72 dB,

 f

i

 = 20 kHz, SFDR: 85 dB, f

i

 = 20 kHz

D

SPI/DSP-Compatible Serial Interfaces With

SCLK up to 20 MHz

D

Single Supply 2.7 Vdc to 5.5 Vdc

D

Rail-to-Rail Analog Input With 500 kHz BW

D

Three Options Available:

–  TLV2541 – Single Channel Input

–  TLV2542 – Dual Channels With

Autosweep

–  TLV2545 – Single Channel With

Pseudo-Differential Input

D

Optimized DSP Mode – Requires FS Only

D

Low Power With Autopower Down

–  Operating Current : 1 mA at 2.7 V, 1.5 mA

at 5 V

Autopower Down: 2 

µ

A at 2.7 V, 5 

µ

at 5 V

D

Small 8-Pin MSOP and SOIC Packages

     

PACKAGE TOP VIEW

TLV2541

1

2

3

4

8

7

6

5

CS

V

REF

GND

AIN

SDO

FS

V

DD

SCLK

1

2

3

4

8

7

6

5

CS/FS

V

REF

GND

AIN0

SDO

SCLK

V

DD

AIN1

TLV2542

1

2

3

4

8

7

6

5

CS/FS

V

REF

GND

AIN(+)

SDO

SCLK

V

DD

AIN(–)

TLV2545

description

The TLV2541/2542/2545 are a family of high performance, 12-bit, low power, miniature 3.6 

µ

s, CMOS

analog-to-digital converters (ADC). The TLV254x family operates from a single 2.7 V to 5.5 V. Devices are

available with single, dual, or single pseudo-differential inputs. The TLV2541 has a 3-state output chip select

(CS), serial output clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial

port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS)

is used to indicate the start of a serial data frame. The TLV2542/45 have a shared CS/FS terminal.

TLV2541/2/5 are designed to operate with very low power consumption. The power saving feature is further

enhanced with an autopower-down mode. This product family features a high-speed serial link to modern host

processors with SCLK up to 20 MHz. TLV254x family uses the built in oscillator as conversion clock, providing

a 3.6 

µ

s conversion time.

AVAILABLE OPTIONS

PACKAGED DEVICES

TA

8-MSOP

(DGK)

8-SOIC

(D)

TLV2541CDGK

0

°

C to 70

°

C

TLV2542CDGK

TLV2545CDGK

TLV2541IDGK

TLV2541ID

– 40

°

C to 85

°

C

TLV2542IDGK

TLV2542ID

TLV2545IDGK

TLV2545ID

Copyright 

©

 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

SLAS245 –MARCH 2000

2

POST OFFICE BOX 655303 

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functional block diagram

S/H

SDO

REF

LOW POWER

SAR ADC

VDD

OSC

Conversion

Clock

CONTROL

LOGIC

Mux

S/H

LOW POWER

12-BIT

SAR ADC

OSC

Conversion

Clock

CONTROL

LOGIC

AIN

SCLK

CS

FS

REF

AIN0

AIN1

SCLK

CS/FS

SDO

VDD

GND

GND

TLV2541

TLV2542

S/H

LOW POWER

12-BIT

SAR ADC

OSC

Conversion

Clock

CONTROL

LOGIC

REF

AIN (+)

AIN (–)

SCLK

CS/FS

SDO

VDD

GND

TLV2545

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Terminal Functions

TLV2541

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AIN

4

I

Analog input channel

CS

1

I

Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.

CS can be used as the FS pin when a dedicated serial port is used. If TLV2541 is attached to a dedicated DSP serial

port, this terminal can be grounded.

FS

7

I

DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used.

GND

3

I

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

SCLK

5

I

Output serial clock. This terminal receives the serial SCLK from the host processor.

SDO

8

O

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge.

The output format is MSB first.

When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge

and output data is valid on the falling edge of SCLK.

When FS is used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the falling edge of

FS or the falling edge of CS (whichever happens first). Output data is valid on the falling edge of SCLK. (This is

typically used with an active FS from a DSP).

VDD

6

I

Positive supply voltage

VREF

2

I

External reference input

TLV2542/45

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AIN0 /AIN(+)

4

I

Analog input channel 0. (positive input for TLV2545)

AIN1/AIN (–)

5

I

Analog input channel 1 (inverted input for TLV2545)

CS/FS

1

I

Chip select/frame sync. A high-to-low transition on the CS/FS removes SDO from 3-state within a maximum delay

time.

GND

3

I

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

SCLK

7

I

Output serial clock. This terminal receives the serial SCLK from the host processor.

SDO

8

O

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS/FS is

high and presents output data after the CS/FS falling edge until the LSB is presented. The output format is MSB

first. SDO returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.

VDD

6

I

Positive supply voltage

VREF

2

I

External reference input

detailed description

The TLV2541/2/5 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1

shows a simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process

starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is

balanced, the conversion is complete and the ADC output code is generated.

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

SLAS245 –MARCH 2000

4

POST OFFICE BOX 655303 

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detailed description (continued)

GND/AIN(–)

ADC Code

AIN

Charge

Redistribution

DAC

Control

Logic

_

+

Figure 1. Simplified SAR Circuit

serial interface

OUTPUT DATA FORMAT

MSB

LSB

D15–D4

D3–D0

Conversion result (OD11–OD0)

Don’t care

The output data format is binary (unipolar straight binary).

binary

Zero scale code = 000h, Vcode = GND

Full scale code = FFFh, Vcode = VREFP – 1 LSB

pseudo-differential inputs

The TLV2545 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a

maximum input ripple of 

±

0.2 V. This is normally used for ground noise rejection.

control and timing

start of the cycle

TLV2541

D

When FS is not used ( FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle. Output

data changes on the rising edge of SCLK. This is typically used for a microcontroller with SPI interface,

although it can also be used for a DSP. The microcontroller SPI interface should be programmed for

CPOL=0 (serial clock referenced to ground) and CPHA=1 (data is valid on the falling edge of serial clock).

D

When FS is used ( FS is an active signal from a DSP), the falling edge of FS is the start of the cycle. Output

data changes on the rising edge of SCLK. This is typically used for a TMS320 DSP. If the TLV2541 is

attached to a dedicated DSP serial port. CS terminal can be grounded.

TLV2542/5

The CS and FS inputs are accessed via the same pin (pin 1) on the TLV2542 and TLV2545. The cycle is started

by the falling edge transition provided by either a CS (interfacing with SPI microcontroller) signal or FS

(interfacing with TMS320 DSP) signal. Timing for the TLV2545 is much like the TLV2541, with the exception of

the CS/FS line.

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

5

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detailed description (continued)

TLV2542 channel MUX reset cycle

The TLV2542 uses CS/FS to reset the AIN multiplexer. A short active CS/FS cycle (4 to 7 SCLKs) resets the

MUX to AIN0. If the CS/FS cycle is sufficient to complete the conversion (16 SCLKs plus maximum conversion

time), the MUX toggles to the next channel (see Figure 4 for timing).

sampling

The converter sample time is 12 SCLKs in duration, beginning on the 5

th

 SCLK received after the converter has

received an active CS or FS signal (CS/FS for the TLV2542/5).

conversion

The TLV2541 completes conversion in the following manner. The conversion is started after the 16th SCLK

edge. The conversion takes 3.5 

µ

s plus 0.1 

µ

s overhead. Enough time (for conversion) should be allowed before

a rising CS/FS edge so that no conversion is terminated prematurely.

TLV2542 input channel selection is toggled on each rising CS /FS edge. The MUX channel can be reset to AIN0

via CS /FS as described in the earlier section and in Figure 5. The input is sampled for 12 SCLKs, converted,

and the result is presented on SDO during the next cycle. Care should also be taken to allow enough time

between samples to avoid prematurely terminating the conversion, which occurs on a rising CS /FS transition

if the conversion is not complete.

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

SLAS245 –MARCH 2000

6

POST OFFICE BOX 655303 

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timing diagrams/conversion cycles

DSP Interface

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SCLK

1

2

3

4

5

6

12

13

14

15

16

1

CS

FS

OD9

OD8

OD11

OD10

OD7

OD6

OD0

SDO

t(sample)

tc

t(powerdown)

Figure 2. TLV2541 DSP Mode/FS Active

µ

P Interface

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SCLK

1

2

3

4

5

6

12

13

14

15

16

1

CS

FS

OD8

OD7

OD6

OD5

OD0

SDO

t(sample)

tc

t(powerdown)

7

OD10

OD11

OD9

Figure 3. TLV2541 Microcontroller Mode/FS (SPI, CPOL = 0, CPHA = 1)

SCLK

2

3

4

5

1

12

16

CS/FS

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎ

SDO

t(powerdown)

tc

1

4

16

12

4

1

OD11

OD0

t(sample)

>8 SCLKs, MUX Toggles to AIN1

AIN0 Result

tc

<8 SCLKs, MUX

Resets to AIN0

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

t(sample)

Figure 4. TLV2542 Timing

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

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timing diagrams/conversion cycles (continued)

OD8

SCLK

1

2

3

4

5

6

12

13

14

15

16

CS/FS

OD7

OD6

OD5

OD0

ÎÎÎÎÎ

ÎÎÎÎÎ

SDO

t(sample)

tc

t(powerdown)

7

OD9

1

OD10

OD9

OD11

OD10

OD11

Figure 5. TLV2545 Timing

use CS as FS input

When interfacing the TLV2541 with the TMS320 DSP, the FSR signal from the DSP may be connected to the

CS input if this is the only device on the serial port. This will save one output terminal from the DSP. (Output data

changes on the falling edge of SCLK. Default for TLV2542 and TLV2545).

SCLK and conversion speed

The minimum onboard oscillator frequency for the TLV2541/2/5 is 4 MHz, and it takes 14 conversion clocks to

complete the conversion. This leads to a 3.5

µ

s conversion time plus 0.1 

µ

s overhead. These devices can

operate with an SCLK up to 20 MHz for the supply voltage range specified. The total conversion time is

14

×

(1/f

osc

). For a 20 MHz SCLK, the minimum total cycle time is given by: 14

×

 (1/4M) +16

×

 (1/20M)+ 0.1 

µ

s}

= 4.4 

µ

s for the TLV254x devices. This is the minimum cycle time for an active CS or CS/FS signal. If violated,

the conversion will terminate, invalidating the next data output cycle.

reference voltage

An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of

the analog inputs to produce a full-scale reading. The value of V

REF

 and the analog input should not exceed

the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital

output is at full scale when the input signal is equal to or higher than V

REF

 and at zero when the input signal

is equal to or lower than GND.

powerdown and powerup initialization

Autopower down is built in to the devices in order to reduce power consumption. The wake-up time is fast

enough to provide power down between each cycle. The power-down state is initiated at the end of conversion

and wakes up upon a falling edge on CS or FS.

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

SLAS245 –MARCH 2000

8

POST OFFICE BOX 655303 

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, GND to V

DD

  

–0.3 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Analog input voltage range 

–0.3 V to V

DD 

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Reference input voltage  

V

DD 

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Digital input voltage range 

–0.3 V to V

DD

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating

 

virtual junction temperature range, T

J

  – 40

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

: C  0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

I –40

°

C to 85

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg 

  – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 

260

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VDD

2.7

3.3

5.5

V

Positive external reference voltage input, VREFP (see Note 1)

2

VDD

V

Analog input voltage (see Note 1)

0

VDD

V

High level control input voltage, VIH

2.1

V

Low-level control input voltage, VIL

0.6

V

Setup time, CS falling edge (2541) or CS/FS falling edge (2542/45)

VDD = REF = 5 V

40

ns

,

g

g (

)

g

g (

)

before first SCLK falling edge, tsu(CSL-SCLKL)

VDD = REF = 2.7 V

70

ns

Hold time, CS rising edge after SCLK falling edge, th(SCLKL-CSH)

5

ns

Delay time, delay from CS falling edge to FS rising edge (td(CSL-FSH)

0.5

7

SCLKs

Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL)

0.35

SCLKs

Hold time, FS hold high after SCLK falling edge, th(SCLKL-FSL)

0.65

SCLKs

Pulse width CS high time, twH(CS)

100

ns

Pulse width FS high time, twH(FS)

0.75

SCLKs

SCLK cycle time, VDD = 3.6–2.7 V, tc(SCLK)

67

10000

ns

SCLK cycle time, VDD = 5.5–4.5 V, tc(SCLK)

50

10000

ns

Pulse width low time, twL(SCLK)

0.4

0.6

SCLK

Pulse width high time, twH(SCLK)

0.4

0.6

SCLK

Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of

conversion time, tc)

0.1

µ

s

Active CS/FS cycle time to reset internal MUX to AIN0, reset cycle

TLV2542 only

4

7

SCLKs

Operating free-air temperature TA

TLV2541/2/5C

0

70

°

C

O erating free-air tem erature, TA

TLV2541/2/5I

–40

85

°

C

NOTES:

1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that

applied to GND convert as all zeros(000000000000).

2. This is the time required for the clock input signal to fall from VIH max or to rise from VILmax to VIHmin. In the vicinity of normal room

temperature, the devices function with input clock transition time as slow as 1 

µ

s for remote data-acquisition applications where the

sensor and A/D converter are placed several feet away from the controlling microprocessor.

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics 

over recommended operating free-air temperature range,

V

DD

 = V

REF

 = 2.7 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at  3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VO

High level output voltage

VDD = 5.5 V, IOH = –0.2 mA at 30 pF load

2.4

V

VOH

High-level output voltage

VDD = 2.7 V, IOH = -20 

µ

A at 30 pF load

VDD–0.2

V

VO

Low level output voltage

VDD = 5.5 V, IOL = 0.8 mA at 30 pF load

0.4

V

VOL

Low-level output voltage

VDD = 2.7 V, IOL = 20 

µ

A at 30 pF load

0.1

V

IO

Off-state output current

VO = VDD

CS

VDD

1

2.5

µ

A

IOZ

(high-impedance-state)

VO = 0

CS = VDD

–1

–2.5

µ

A

IIH

High-level input current

VI = VDD

0.005

2.5

µ

A

IIL

Low-level input current

VI = 0 V

–0.005

2.5

µ

A

ICC

Operating supply current

CS at 0 V

VDD = 4.5 V ~ 5.5 V

1.3

1.5

mA

ICC

Operating supply current

CS at 0 V,

VDD = 2.7 V ~ 3.3 V

0.85

0.95

mA

Autopower-down current (0.5 

µ

s inactive)

For all digital inputs,

0

 VI 

 0.3 V or VI 

 VDD– 0.3 V,

SCLK = 0, VDD = 4.5 V to 5.5 V,  Ext ref

5

µ

A

ICC(

O

)

VDD = 2.7 V to 3.3 V,    Ext ref

2

ICC(AUTOPWDN)

Autopower-down current (5 

µ

s inactive)

For all digital inputs,

0

 VI 

 0.3 V or VI 

 VDD– 0.3 V,

SCLK = 0, VDD = 4.5 V to 5.5 V,  Ext ref

1

µ

A

VDD = 2.7 V to 3.3 V

1

Selected analog input channel leakage

Selected channel at VDD

1

µ

A

g

g

current

Selected channel at 0 V

–1

µ

A

C

Input capacitance

Analog inputs

20

45

50

pF

Ci

Input capacitance

Control Inputs

5

25

pF

Input on resistance

VDD = 5.5 V

500

Input on resistance

VDD = 2.7 V

600

Delay time, delay from CS falling edge to

VDD = REF = 5.5 V, 30 pF load

40

ns

y

,

y

g

g

SDO valid, td(CSL-SDOV)

VDD = REF = 2.7 V, 30 pF load

70

ns

Delay time, delay from FS falling edge to

VDD = REF = 5.5 V, 30 pF load

1

ns

y

,

y

g

g

SDO valid, td(FSL-SDOV)

VDD = REF = 2.7 V, 30 pF load

1

ns

Delay time, delay from SCLK rising edge

VDD = REF = 5.5 V, 30 pF load

11

ns

y

,

y

g

g

to SDO valid, td(SCLKH-SDOV)

VDD = REF = 2.7 V, 30 pF load

21

ns

Delay time, delay from 17th SCLK rising

VDD = REF = 5.5 V, 30 pF load

30

ns

y

,

y

g

edge to SDO 3-state, td(SCLK17H-SDOZ) VDD = REF = 2.7 V, 30 pF load

60

ns

tc

Conversion time

Conversion clock = internal oscillator

2.1

2.6

3.5

µ

s

t(sample)

Sampling time

See Note 3

300

ns

Autopower down

Action time

ICC start to decrease

0.5

SCLK

Autopower down

Wakeup time

ICC down to MIN [ICC(AUTOPWDN)]

1

2

ms

Autopower down

0.5

SCLK

† All typical values are at VDD = 5 V, TA = 25

°

C.

NOTE 3: Minimal t(sample) is given by 0.9 

×

 50 pF 

×

 (RS + 0.6 kW), where RS is the source output impedance.

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TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

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ac specifications (f

i

 = 20 kHz)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SINAD

Signal to noise ratio +distortion

200 KSPS,  VDD = VREF = 5.5 V

70

72

dB

SINAD

Signal-to-noise ratio +distortion

150 KSPS,  VDD = VREF = 2.7 V

68

71

dB

THD

Total harmonic distortion

200 KSPS,  VDD = VREF = 5.5 V

–84

–80

dB

THD

Total harmonic distortion

150 KSPS,  VDD = VREF = 2.7 V

–84

–80

dB

ENOB

Effective number of bits

200 KSPS,  VDD = VREF = 5.5 V

11.8

Bits

ENOB

Effective number of bits

150 KSPS,  VDD = VREF = 2.7 V

11.6

Bits

SFDR

Spurious free dynamic range

200 KSPS,  VDD = VREF = 5.5 V

–84

–80

dB

SFDR

Spurious free dynamic range

150 KSPS,  VDD = VREF = 2.7 V

–84

–80

dB

Analog Input

Full power bandwidth, –3 dB

1

MHz

Full-power bandwidth, –1 dB

500

kHz

external reference specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference input voltage

VDD = =2.7  V ~ 5.5 V

VDD

V

VDD = 5 5 V

CS = 1,

SCLK = 0

100

M

Reference input impedance

VDD = 5.5 V

CS = 0,

SCLK = 20 MHz

20

25

k

Reference input impedance

VDD = 2 7 V

CS = 1,

SCLK = 0

100

M

VDD = 2.7 V

CS = 0,

SCLK = 20 MHz

20

25

k

Reference current

VDD = VREF = 5.5 V,

CS = 0,

SCLK = 20 MHz

100

400

µ

A

Reference current

VDD = VREF =2.7 V,

CS = 0,

SCLK = 20 MHz

50

200

µ

A

VDD = VREF = 5 5 V

CS = 1,

SCLK = 0

5

15

Reference input capacitance

VDD = VREF = 5.5 V

CS = 0,

SCLK = 20 MHz

20

45

50

pF

Reference input capacitance

VDD = VREF =2 7 V

CS = 1,

SCLK = 0

5

15

pF

VDD = VREF =2.7 V

CS = 0,

SCLK = 20 MHz

20

45

50

VREF

Reference voltage

VDD = =2.7  V – 5.5 V

VDD

V

dc specification, 

V

DD

 = V

REF

 = 2.7 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

INL

Integral linearity error (see Note 5)

±

0.6

±

1

LSB

DNL

Differential linearity error

See Note 4

±

0.5

±

1

LSB

EO

Offset error (see Note 6)

See Note 4

TLV2541/42

±

1.5

LSB

EO

Offset error (see Note 6)

See Note 4

TLV2545

±

2.5

LSB

EG

Gain error (see Note 6)

See Note 4

TLV2541/42

±

2

LSB

EG

Gain  error (see Note 6)

See Note 4

TLV2545

±

5

LSB

Et

Total unadjusted error (see Note 7)

See Note 4

TLV2541/42

±

2

LSB

Et

Total unadjusted error (see Note 7)

See Note 4

TLV2545

±

5

LSB

NOTES:

4. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that

applied to REFM convert as all zeros (0000000000).

5. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage.

7. Total unadjusted error comprises linearity, zero, and full-scale errors.

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TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

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PARAMETER MEASUREMENT INFORMATION

ÎÎÎÎÎ

ÎÎÎÎÎ

16

OD0

SCLK

VIH

CS

OD11

SDO

t(sample)

tc

4

12

twL(SCLK)

OD8

ÎÎÎÎÎ

ÎÎÎÎÎ

1

2

VIL

tsu(CSL-SCLKL)

twH(SCLK)

th(EOC-CSH)

tWH(CS)

t(powerdown)

FS

th(SCLKL-FSL)

tsu(FSH-SCLKL)

twh(FS)

td(CSL-FSH)

td(CSL-SDOV)

td(SCLKH-SDOV)

td(SCLK17H-SDOZ)

Figure 6. Critical Timing TLV2541 (FS is active)

OD10

OD0

SCLK

1

SDO

t(sample)

tc

4

16

12

OD9

2

CS

td(SCLKH-SDOV)

td(CSL-SDOV)

td(SCLK17H-SDOZ)

OD11

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

t(powerdown)

tsu(CSL–SCLKL)

th(EOC–CSH)

Figure 7. Critical Timing TLV2541 (FS = 1)

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TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

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PARAMETER MEASUREMENT INFORMATION

ÎÎÎÎ

ÎÎÎÎ

SCLK

1

CS/FS

SDO

t(sample)

tc

td(SCLK17H-SDOZ)

1

1

12

16

4

t(Reset Cycle)

MUX = AIN0

OD11

OD0

ÎÎÎÎÎ

ÎÎÎÎÎ

OD11

td(CSL-SDOV)

th(EOC-CSH)

td(CSLKH-SDOV)

td(CSL-SDOV)

Figure 8. Critical Timing TLV2542 Reset Cycle

OD11

OD0

SCLK

VIH

SDO

t(sample)

tc

4

16

12

twL(SCLK)

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

1

2

VIL

twH(SCLK)

th(EOC-CSH)

t(powerdown)

CS/FS

th(SCLKL-FSL)

tsu(FSH-SCLKL)

td(CSL-SDOV)

td(SCLKH-SDOV)

td(SCLK17H-SDOZ)

OD8

twh(FS)

Figure 9. Critical Timing TLV2545 Power-Down Cycle

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

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TYPICAL CHARACTERISTICS

Figure 10

0.6

–40

25

INL

 – Integral Nonlinearity – LSB

t – Temperature –   C

INTEGRAL NONLINEARITY

vs

TEMPERATURE

0.7

90

0.65

°

VDD = REF = 2.7 V

150 KSPS

Figure 11

0.5

–40

25

INL

 – Integral Nonlinearity – LSB

t – Temperature –   C

INTEGRAL NONLINEARITY

vs

TEMPERATURE

0.6

90

0.55

°

VDD = REF = 5.5 V

200 KSPS

Figure 12

0.3

0.2

0

–40

25

DNL

 – Differential Nonlinearity – LSB

0.4

0.5

t – Temperature –   C

DIFFERENTIAL NONLINEARITY

vs

TEMPERATURE

0.6

90

0.1

°

VDD = REF = 2.7 V

150 KSPS

Figure 13

0.3

0.25

–40

25

t – Temperature –   C

DIFFERENTIAL NONLINEARITY

vs

TEMPERATURE

0.35

90

°

VDD = REF = 5.5 V

200 KSPS

DNL

 – Differential Nonlinearity – LSB

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

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TYPICAL CHARACTERISTICS

Figure 14

0.3

0.2

0

–40

25

Offset Error – LSB

0.4

0.5

t – Temperature –   C

OFFSET ERROR

vs

TEMPERATURE

90

0.1

°

VDD = REF = 2.7 V

150 KSPS

Figure 15

0.85

0.8

–40

25

Gain Error – LSB

0.9

t – Temperature –   C

GAIN ERROR

vs

TEMPERATURE

90

°

VDD = REF = 5.5 V

200 KSPS

1.4

1.2

–40

25

Supply Current – mA

1.5

t – Temperature –   C

SUPPLY CURRENT

vs

TEMPERATURE

90

°

VDD = REF = 5.5 V

200 KSPS

1.3

Figure 16

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TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

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TYPICAL CHARACTERISTICS

–0.5

–1

1

INL

 – Integral Nonlinearity – LSB

0

0.5

Digital Output Codes

Fast Fourier Transform (FFT) PLOT

1

4095

VDD = REF = 2.7 V

150 KSPS

Figure 17

–0.5

–1

1

DNL

 – Differential Nonlinearity –LSB

0

0.5

Digital Output Codes

Fast Fourier Transform (FFT) PLOT

1

4095

VDD = REF = 2.7 V

150 KSPS

Figure 18

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

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TYPICAL CHARACTERISTICS

–0.5

–1

1

INL

 – Integral Nonlinearity – LSB

0

0.5

Digital Output Codes

INTEGRAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODES

1

4095

VDD = REF = 5.5 V

200 KSPS

Figure 19

–0.5

–1

1

DNL

 – Differential Nonlinearity –LSB

0

0.5

Digital Output Codes

DIFFERENTIAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODES

1

4095

VDD = REF = 5.5 V

200 KSPS

Figure 20

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

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TYPICAL CHARACTERISTICS

–60

–80

0

20

40

60

80

100

Magnitude – dB

–40

–20

f – Input Frequency – KHz

2048 POINTS FAST FOURIER TRANSFORM (FFT)

0

–120

–140

–100

VDD = REF = 2.7 V

150 KSPS

fi = 20 kHz

Figure 21

–60

–80

0

20

40

60

80

100

Magnitude – dB

–40

–20

f – Input Frequency – KHz

2048 POINTS FAST FOURIER TRANSFORM (FFT)

0

–120

–140

–100

VDD = REF = 5.5 V

200 KSPS

fi = 20 kHz

Figure 22

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

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TYPICAL CHARACTERISTICS

Figure 23

71

69

65

0

40

SINAD – dB

73

75

f – Input Frequency – KHz

SINAD

vs

FREQUENCY

60

67

10

20

30

50

70

80

VDD = REF = 2.7 V

150 KSPS

Figure 24

71

69

65

0

40

SINAD – dB

73

75

f – Input Frequency – KHz

SINAD

vs

FREQUENCY

60

67

20

80

VDD = REF = 5.5 V

200 KSPS

100

Figure 25

11.6

11.4

11

0

40

ENOB – Bits

11.8

12

f – Input Frequency – KHz

ENOB

vs

FREQUENCY

60

11.2

10

20

30

50

70

80

VDD = REF = 5.5 V

200 KSPS

Figure 26

11.6

11.4

11

0

40

ENOB – Bits

11.8

12

f – Input Frequency – KHz

ENOB

vs

FREQUENCY

60

11.2

20

80

VDD = REF = 5.5 V

200 KSPS

11.9

11.7

11.5

11.3

11.1

100

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

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TYPICAL CHARACTERISTICS

Figure 27

–79

–81

–85

0

40

THD – dB

–77

–75

f – Input Frequency – KHz

THD

vs

FREQUENCY

60

–83

20

80

VDD = REF = 2.7 V

150 KSPS

–76

–78

–80

–82

–84

70

50

30

10

Figure 28

–78

–82

–90

0

40

THD – dB

–74

–70

f – Input Frequency – KHz

THD

vs

FREQUENCY

60

–86

20

80

–72

–76

–80

–84

–88

100

VDD = REF = 5.5 V

200 KSPS

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

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TYPICAL CHARACTERISTICS

100000000000

011111111111

000000000010

000000000001

000000000000

111111111110

0

0.0024

2.4564

2.4576

2.4588

Digital Output Code

100000000001

111111111101

111111111111

4.9128

4.9140

4.9152

2048

2047

2

1

0

4094

Step

2049

4093

4095

0.0006

VI – Analog Input Voltage – V

VZT =VZS + 1/2 LSB

VZS

See Notes A and B

4.9134

0.0012

VFT = VFS – 1/2 LSB

VFS

VFS Nom

NOTES: A. This curve is based on the assumption that Vref+ and Vref– have been adjusted so that the voltage at the transition from digital 0 to

1 (VZT) is 0.0006 V, and the transition to full scale (VFT) is 4.9134 V, 1 LSB = 1.2 mV.

B. The full scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is

the step whose nominal midstep value equals zero.

Figure 29. Ideal 12-Bit ADC Conversion Characteristics

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TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

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APPLICATION INFORMATION

FS

TLV2541

TMS320 DSP

XF

RXD

SCLK

Ain

10 k

VDD

SDO

SCLK

VDD

GND

10 k

CS

EXT

Reference

VREF

CS/FSD

TLV2542/5

TMS320 DSP

XF

RXD

SCLK

AIN 0/AIN (+)†

10 k

VDD

SDO

SCLK

VDD

GND

10 k

EXT

Reference

VREF

AIN 1/AIN (–)†

† For TLV2545 only

Figure 30. Typical Interface to a TMS320 DSP

simplified analog input analysis

Using the equivalent circuit in Figure 31, the time required to charge the analog input capacitance from 0 to Vs

within 1/2 LSB can be derived as follows.

The capacitance charging voltage is given by:

Vc

+

Vs

ǒ

1

–EXP

ǒ

–tch

Rt

 

Ci

Ǔ

Ǔ

Where:

Rt = Rs + Zi

tch = Charge time

(1)

The input impedance Zi is 0.5 k

 at 5 V, and is higher (~ 0.6 k

) at 2.7 V. The final voltage to 1/2 LSB is given

by:

Vc (1

ń

2

LSB)

+

Vs–

ǒ

Vs

8192

Ǔ

(2)

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TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

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APPLICATION INFORMATION

simplified analog input analysis (continued)

Equating equation 1 to equation 2 and solving for cycle time t

c

 gives:

Vs

*

ǒ

Vs

8192

Ǔ

+

Vs

ǒ

1

*

EXP

ǒ

*

tch

Rt

 

Ci

Ǔ

Ǔ

(3)

and time to change to 1/2 LSB (equal to minimum sampling time) is:

tch (1

ń

2

LSB)

+

Rt

 

Ci

 

In(8192)

+

Min[t(sample)]

Where:

In(8192) = 9.011

Therefore, with the values given, the time for the analog input signal to settle is:

tch (1

ń

2

LSB)

+

(Rs

)

0.5

k

W

)

 

Ci

 

In(8192)

(4)

This time must be less than the converter sample time shown in the timing diagrams. This is 12

×

 SCLKs.

t

(

sample)

+

12

 

1

f (SCLK)

w

Min

ƪ

t

(

sample)

ƫ

+

tch

ǒ

1

2

LSB

Ǔ

(5)

Therefore the maximum SCLK frequency is:

max

ƪ

f

ǒ

SCLK

Ǔ

ƫ

+

12

tch

ǒ

1

ń

2

LSB

Ǔ +

12

[In(8192)

 

Rt

 

Ci]

(6)

maximum conversion throughput

For a supply voltage of 5 V, if the source impedance is less than 1 k

, and the ADC analog input capacitance

Ci is less than 50 pF, this equates to a minimum sampling time tch 

ǒ

1

2

LSB

Ǔ

 of 0.676 

µ

s (

t

µ

s). Since the

sampling time requires 12 SCLKs, the fastest SCLK frequency is 12/tch

ǒ

1

2

LSB

Ǔ

 = 18 MHz for R

s

 

 1 k

.

The minimal total cycle time, t

(cycle)

, is given as:

t

(

cycle)

+

t

(

sample)

)

tc

)

t

(

overhead)

+

16

Max

ƪ

f (SCLK)

ƫ

)

3.5

m

s

)

0.1

m

s

+

4.5

m

s

This is equivalent to a maximum throughput, max[fs] of 222 KSPS.

The throughput can be even higher with a smaller source impedance. When source impedance is 100 

, the

minimum sampling time becomes:

tch (1

ń

2

LSB)

+

Rt

 

Ci

 

In(8192)

+

0.27

m

s

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TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

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APPLICATION INFORMATION

maximum conversion throughput (continued)

The maximum SCLK frequency possible is 12/tch 

ǒ

1

2

LSB

Ǔ

 = 44 MHz. Then a 20 MHz clock (maximum SCLK

frequency allowed for the internal comparator can be used. The minimum total cycle time is then reduced to:

t

(

cycle)

+

t

(

sample)

)

t

c

)

t

(

overhead)

+

16

max

ƪ

f (SCLK)

ƫ

)

3.5

m

s

)

0.1

m

s

+

4.4

m

s

The maximum throughput is 1/4.4 

µ

s = 227 KSPS for this case.

Ci

VI = Input Voltage at AIN

VS= External Driving Source Voltage

RS= Source Resistance

ri   = Input Resistance (Mux On Resistance)

Ci  = Input Capacitance

VC = Capacitance Charging Voltage

_

+

Driving Source Requirements:

Data Converter

VS

RS

Driving Source

ri

Vi

VC

ts AMP

NOTE: Noise and distortion must for the source be equivalent to the resolution of the converter.

Rs must be real at the input frequency.

Figure 31. Equivalent Input Circuit Including the Driving Source

power down calculations

Total power consumption at different conversion rate f

s

, (f

s

 

 MAX [f

s

]) can be calculated by:

V

DD

 

×

 i(AVERAGE) = V

DD

 [(f

S

/MAX [f

s

]) 

×

 i(ON) + (1–f

s

/MAX [f

s

]) 

×

 i(OFF)]

If V

DD

 = 2.7 V for TLV2541, and the sampling rate f

s

 = 10 kHz, the maximum sampling rate f

(SMAX)

 = 200 kHz

then i(ON) = ~1 mA operating current

and i(OFF) = ~2 

µ

A autopower-down current

so V

DD

 

×

 i(AVERAGE) = 2.7 

×

 (0.05 

×

 1000 

µ

A + 0.95 

×

 2 

µ

A)

 = (2.7 

×

 51.9) 

µ

W

 = 140 

µ

W

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

 

SLAS245 –MARCH 2000

24

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL DATA

DGK (R-PDSO-G8)   

PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

0,15 NOM

Gage Plane

4073329/B 04/98

4,98

0,25

5

3,05

4,78

2,95

8

4

3,05

2,95

1

0,38

1,07 MAX

Seating Plane

0,65

M

0,25

0

°

– 6

°

0,10

0,15

0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-187

background image

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

25

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**)    

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

4040047 / D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A  MIN

A  MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0

°

– 8

°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

background image

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 2000, Texas Instruments Incorporated