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CDC339

CLOCK DRIVER

WITH 3-STATE OUTPUTS

 

SCAS331 – DECEMBER 1992 – REVISED MARCH 1994

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Low Output Skew, Low Pulse Skew for

Clock-Distribution and Clock-Generation

Applications

D

TTL-Compatible Inputs and Outputs

D

Distributes One Clock Input to Eight

Outputs

–  Four Same-Frequency Outputs

–  Four Half-Frequency Outputs

D

Distributed V

CC

 and Ground Pins Reduce

Switching Noise

D

High-Drive Outputs (– 48-mA I

OH

,

48-mA I

OL

)

D

State-of-the-Art E

PIC-

ΙΙ

B

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages

     

description

The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring

synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The

four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch

at one-half the frequency of CLK.

When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the

Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the

low level. When OE is high, the outputs are in the high-impedance state.

The CDC339 is characterized for operation from – 40

°

C to 85

°

C.

FUNCTION TABLE

INPUTS

OUTPUTS

OE

CLR

CLK

Y1–Y4

Q1– Q4

H

X

X

Z

Z

L

L

L

L

L

L

L

H

H

L

L

H

L

L

Q0†

L

H

H

Q0†

† The level of the Q outputs before the

indicated steady-state input conditions were

established.

Copyright 

©

 1994, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC-

ΙΙ

B is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Y3

GND

Y4

V

CC

OE

CLR

V

CC

Q4

GND

Q3

Y2

GND

Y1

V

CC

CLK

GND

V

CC

Q1

GND

Q2

DB OR DW PACKAGE

(TOP VIEW)

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CDC339

CLOCK DRIVER

WITH 3-STATE OUTPUTS

 

SCAS331 – DECEMBER 1992 – REVISED MARCH 1994

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

logic diagram (positive logic)

EN

5

16

CLK

R

6

T

Y1

18

Y2

20

Y3

1

Y4

3

T

Y1

18

Q1

13

Q2

11

Q3

10

Q4

8

OE

CLR

Y2

20

Y3

1

Y4

3

Q1

13

Q2

11

Q3

10

Q4

8

R

16

CLK

CLR

OE

5

6

† This symbol is in accordance with ANSI/IEEE Std 91-1984 

and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

 – 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

 – 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the disabled or power-off state, V

O

 

 – 0.5 V to 5.5 V

. . . . . . . . . . . . . . . 

Current into any output in the low state, I

O

 

 96 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK 

(V

< 0) 

 –18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK 

(V

< 0) 

 – 50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Maximum power dissipation at T

A

 = 55

°

C (in still air) (see Note 2): DB package 

 0.6 W

. . . . . . . . . . . . . . . . . . 

DW package 

 1.6 W

. . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

   

– 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150

°

C and a board trace length of 750 mils.

For more information, refer to the 

Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology

Data Book, literature number SCBD002B.

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CDC339

CLOCK DRIVER

WITH 3-STATE OUTPUTS

 

SCAS331 – DECEMBER 1992 – REVISED MARCH 1994

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

MIN

MAX

UNIT

VCC

Supply voltage

4.75

5.25

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

VI

Input voltage

0

VCC

V

IOH

High-level output current

– 48

mA

IOL

Low-level output current

48

mA

fclock

Input clock frequency

80

MHz

TA

Operating free-air temperature

– 40

85

°

C

NOTE 3: Unused pins (input or I/O) must be held high or low.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIK

VCC = 4.75 V,

II = –18 mA

–1.2

V

VOH

VCC = 4.75 V,

IOH = – 48 mA

2

V

VOL

VCC = 4.75 V,

IOL = 48 mA

0.5

V

IIH

VCC = 5.25 V,

VI = 2.7 V

50

µ

A

IIL

VCC = 5.25 V,

VI = 0.5 V

– 50

µ

A

IOZ

VCC = 5.25 V,

VO = 2.7 V or 0.5 V

±

50

µ

A

IO‡

VCC = 5.25 V,

VO = 2.5 V

– 50

– 180

mA

V

5 25 V

I

0

Outputs high

70

ICC

VCC = 5.25 V,

IO = 0,

VI = VCC or GND

Outputs low

85

mA

VI = VCC or GND

Outputs disabled

70

Ci

VI = 2.5 V or 0.5 V

3

pF

Co

VO = 2.5 V or 0.5 V

8

pF

† All typical values are at VCC = 5 V, TA = 25

°

C.

‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

fclock

Clock frequency

80

MHz

CLR low

4

tw

Pulse duration

CLK low

4

ns

CLK high

4

tsu

Setup time

CLR inactive before CLK

2

ns

Clock duty cycle

40%

60%

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CDC339

CLOCK DRIVER

WITH 3-STATE OUTPUTS

 

SCAS331 – DECEMBER 1992 – REVISED MARCH 1994

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (see Figures 1 and 2)

12

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN

TYP†

MAX

UNIT

fmax

80

MHz

tPLH

CLK

Any Y or Q

3

9

ns

tPHL

CLK

Any Y or Q

3

9

ns

tPHL

CLR

Any Q

4

9

ns

tPZH

OE

Any Y or Q

2

7

ns

tPZL

OE

Any Y or Q

3

7

ns

tPHZ

OE

Any Y or Q

2

7

ns

tPLZ

OE

Any Y or Q

2

7

ns

Y

0.75

tsk(o)

CLK

Q

0.9

ns

( )

Y

 and Q

0.9

tr

0.9

ns

tf

0.7

ns

† All typical values are at VCC = 5 V, TA = 25

°

C.

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CDC339

CLOCK DRIVER

WITH 3-STATE OUTPUTS

 

SCAS331 – DECEMBER 1992 – REVISED MARCH 1994

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

th

tsu

From Output

 Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

TEST

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

S1

Open

7 V

Open

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 7 V

(see Note C)

Output

Waveform 2

S1 at Open

(see Note C)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

 0 V

3 V

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

VOLTAGE WAVEFORMS

VOLTAGE WAVEFORMS

VOLTAGE WAVEFORMS

tPLH

tPHL

Output

1.5 V

1.5 V

3 V

0 V

1.5 V

VOH

VOL

Input

0.8 V

2 V

tr

0.8 V

2 V

tf

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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CDC339

CLOCK DRIVER

WITH 3-STATE OUTPUTS

 

SCAS331 – DECEMBER 1992 – REVISED MARCH 1994

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

 

CLK

tPLH1

Y1

tPLH9

Y2

tPLH2

tPLH10

Y3

tPLH3

tPLH11

Y4

tPLH4

tPLH12

Q1

tPLH5

Q2

tPLH6

Q3

tPLH7

Q4

tPLH8

NOTES: A. Output skew, tsk(o), from CLK

 to Y

, is calculated as the greater of the difference between the fastest and slowest of

tPLHn (n = 1, 2, 3, 4) or tPLHn (n = 9, 10, 11, 12).

B. Output skew, tsk(o), from CLK

 to Q

, is calculated as the greater of the difference between the fastest and slowest of

tPLHn (n = 5, 6, 7, 8).

C. Output skew, tsk(o), from CLK

 to Y

 and Q

, is calculated as the greater of the difference between the fastest and slowest of

tPLHn  (n  =  1,  2,  . . . ,  8).

Figure 2. Skew Waveforms and Calculations

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

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Copyright 

©

 1998, Texas Instruments Incorporated