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SN74CBT3253

DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER

 

 

SCDS018I – MAY 1995 – REVISED MAY 1998

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Functionally Equivalent to QS3253

D

5-

 Switch Connection Between Two Ports

D

TTL-Compatible Input Levels

D

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB, DBQ), Thin Very Small-Outline (DGV),

and Thin Shrink Small-Outline (PW)

Packages

description

The SN74CBT3253 is a dual 1-of-4 high-speed

TTL-compatible FET multiplexer/demultiplexer.

The low on-state resistance of the switch allows

connections to be made with minimal propagation

delay.

1OE, 2OE, S0, and S1 select the appropriate

B output for the A-input data.

The SN74CBT3253 is characterized for operation

from –40

°

C to 85

°

C.

FUNCTION TABLE

(each multiplexer/demultiplexer)

INPUTS

FUNCTION

OE

S1

S0

FUNCTION

L

L

L

A port = B1 port

L

L

H

A port = B2 port

L

H

L

A port = B3 port

L

H

H

A port = B4 port

H

X

X

Disconnect

Copyright 

©

 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1OE

S1

1B4

1B3

1B2

1B1

1A

GND

V

CC

2OE

S0

2B4

2B3

2B2

2B1

2A

D, DB, DBQ, DGV, OR PW PACKAGE

(TOP VIEW)

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SN74CBT3253

DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER

 

 

SCDS018I – MAY 1995 – REVISED MAY 1998

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

2B1

1B1

2A

1A

S0

S1

1OE

2OE

1B2

1B3

1B4

2B2

2B3

2B4

7

9

14

2

1

15

6

5

4

3

10

11

12

13

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous channel current 

128 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

(V

I/O 

< 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA

 (see Note 2): D package 

113

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DB package 

131

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DBQ package 

139

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DGV package 

180

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

PW package 

149

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

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SN74CBT3253

DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER

 

 

SCDS018I – MAY 1995 – REVISED MAY 1998

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

MIN

MAX

UNIT

VCC

Supply voltage

4

5.5

V

VIH

High-level control input voltage

2

V

VIL

Low-level control input voltage

0.8

V

TA

Operating free-air temperature

–40

85

°

C

NOTE  3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

V

II

VCC = 5 V,

VI = 5.5 V or GND

±

1

µ

A

ICC

VCC = 5.5 V,

IO = 0,

VI = VCC or GND

3

µ

A

ICC‡

Control inputs

VCC = 5.5 V,

One input at 3.4 V,

Other inputs at VCC or GND

2.5

mA

Ci

Control inputs

VI = 3 V or 0

3.5

pF

Ci (OFF)

A port

VO = 3 V or 0

OE

V

10

pF

Cio(OFF)

B port

VO = 3 V or 0,

OE = VCC

4

pF

§

VCC = 4 V,

TYP at VCC = 4 V

VI  = 2.4 V,

II = 15 mA

ron§

VI = 0

II = 64 mA

5

7

on

VCC = 4.5 V

VI  = 0

II = 30 mA

5

7

VI  = 2.4 V,

II = 15 mA

10

15

† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25

°

C.

‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

§ Measured by the voltage drop between the A and the B terminals at the indicated current through the switch.  On-state resistance is determined

by the lower voltage of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4 V

VCC = 5 V

±

 0.5 V

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

tpd¶

A or B

B or A

0.35

0.25

ns

tpd

S

A or B

6.6

1.6

6.2

ns

t

S

A or B

7.1

1.3

6.3

ns

ten

OE

A or B

7.3

1.4

6.4

ns

tdi

S

A or B

7.9

1.1

7.4

ns

tdis

OE

A or B

7.3

2.3

7

ns

¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when

driven by an ideal voltage source (zero output impedance).

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SN74CBT3253

DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER

 

 

SCDS018I – MAY 1995 – REVISED MAY 1998

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VOH

VOL

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

tPLH

tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

VOH

VOL

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

0 V

Input

3 V

3.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf 

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

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Copyright 

©

 1998, Texas Instruments Incorporated