background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

CMOS Rail-To-Rail Input/Output

D

Input Bias Current . . . 2.5 pA

D

Low Supply Current . . . 600 

µ

A/Channel

D

Ultra-Low Power Shutdown Mode

I

DD(SHDN)

. . .  350 nA/ch at 3 V

I

DD(SHDN)

. . .  1000 nA/ch at 5 V

D

Gain-Bandwidth Product . . . 2.8 MHz

D

High Output Drive Capability

–  

±

10 mA at 180 mV

–  

±

35 mA at 500 mV

D

Input Offset Voltage . . . 250 

µ

V (typ)

D

Supply Voltage Range . . . 2.7 V to 6 V

D

Ultra Small Packaging

–  5 or 6 Pin SOT-23 (TLV2470/1)

–  8 or 10 Pin MSOP (TLV2472/3)

     

description

The TLV247x is a family of CMOS rail-to-rail input/output operational amplifiers that establishes a new

performance point for supply current versus ac performance. These devices consume just 600 

µ

A/channel

while offering 2.8 MHz of gain-bandwidth product. Along with increased ac performance, the amplifier provides

high output drive capability, solving a major shortcoming of older micropower operational amplifiers. The

TLV247x can swing to within 180 mV of each supply rail while driving a 10-mA load. For non-RRO applications,

the TLV247x can supply 

±

35 mA at 500 mV off the rail. Both the inputs and outputs swing rail-to-rail for increased

dynamic range in low-voltage applications. This performance makes the TLV247x family ideal for sensor

interface,  portable medical equipment, and other data acquisition circuits.

FAMILY PACKAGE TABLE

DEVICE

NUMBER OF

PACKAGE TYPES

SHUTDOWN

UNIVERSAL EVM

DEVICE

CHANNELS

PDIP

SOIC

SOT-23

TSSOP

MSOP

SHUTDOWN

BOARD

TLV2470

1

8

8

6

Yes

TLV2471

1

8

8

5

TLV2472

2

8

8

8

Refer to the EVM

Selection Guide

TLV2473

2

14

14

10

Yes

Selection Guide

(Lit# SLOU060)

TLV2474

4

14

14

14

(Lit# SLOU060)

TLV2475

4

16

16

16

Yes

A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS†

DEVICE

VDD

(V)

VIO

(

µ

V)

BW

(MHz)

SLEW RATE

(V/

µ

s)

IDD (per channel)

(

µ

A)

OUTPUT

DRIVE

RAIL-TO-RAIL

TLV247X

2.7 – 6.0

250

2.8

1.5

600

±

35 mA

I/O

TLV245X

2.7 – 6.0

20

0.22

0.11

23

±

10 mA

I/O

TLV246X

2.7 – 6.0

150

6.4

1.6

550

±

90 mA

I/O

TLV277X

2.5 – 6.0

360

5.1

10.5

1000

±

10 mA

O

† All specifications measured at 5 V.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright 

©

 2000, Texas Instruments Incorporated

3

2

4

6

(TOP VIEW)

1

OUT

GND

IN+

VDD

IN –

TLV2470

DBV PACKAGE

5

SHDN

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TLV2470 and TLV2471 AVAILABLE OPTIONS

PACKAGED DEVICES

TA

SMALL OUTLINE

SOT-23

PLASTIC DIP

(D)†

(DBV)†

SYMBOL

(P)

0

°

C to 70

°

C

TLV2470CD

TLV2471CD

TLV2470CDBV

TLV2471CDBV

VAUC

VAVC

TLV2470CP

TLV2471CP

– 40

°

C to 125

°

C

TLV2470ID

TLV2471ID

TLV2470IDBV

TLV2471IDBV

VAUI

VAVI

TLV2470IP

TLV2471IP

– 40

°

C to 125

°

C

TLV2470AID

TLV2471AID

TLV2470AIP

TLV2471AIP

† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number

(e.g., TLV2470CDR).

TLV2472 AND TLV2473 AVAILABLE OPTIONS

PACKAGED DEVICES

TA

SMALL

OUTLINE

MSOP

MSOP

PLASTIC

DIP

PLASTIC

DIP

OUTLINE

(D)†

(DGN)†

SYMBOL‡

(DGQ)†

SYMBOL‡

DIP

(N)

DIP

(P)

0

°

C to 70

°

C

TLV2472CD

TLV2473CD

TLV2472CDGN

xxTIABU

TLV2473CDGQ

xxTIABW

TLV2473CN

TLV2472CP

40

°

C to 125

°

C

TLV2472ID

TLV2473ID

TLV2472IDGN

xxTIABV

TLV2473IDGQ

xxTIABX

TLV2473IN

TLV2472IP

– 40

°

C to 125

°

C

TLV2472AID

TLV2473AID

TLV2473AIN

TLV2472AIP

† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2472CDR).

‡ xx represents the device date code.

TLV2474 and TLV2475 AVAILABLE OPTIONS

PACKAGED DEVICES

TA

SMALL OUTLINE

(D)†

PLASTIC DIP

(N)

TSSOP

(PWP)†

0

°

C to 70

°

C

TLV2474CD

TLV2475CD

TLV2474CN

TLV2475CN

TLV2474CPWP

TLV2475CPWP

– 40

°

C to 125

°

C

TLV2474ID

TLV2475ID

TLV2474IN

TLV2475IN

TLV2474IPWP

TLV2475IPWP

– 40

°

C to 125

°

C

TLV2474AID

TLV2475AID

TLV2474AIN

TLV2475AIN

TLV2474AIPWP

TLV2475AIPWP

† This package is available taped and reeled. To order this packaging option, add an R

suffix to the part number (e.g., TLV2474CDR).

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TLV247x PACKAGE PINOUTS

1

2

3

5

6

7

8

16

15

14

13

12

11

10

9

1OUT

1IN –

1IN+

V

DD

2IN+

2IN –

2OUT

1/2SHDN

4OUT

4IN –

4IN+

GND

3IN +

3IN–

3OUT

3/4SHDN

(TOP VIEW)

TLV2475

D, N, OR PWP PACKAGE

1

2

3

4

5

10

9

8

7

6

1OUT

1IN –

1IN+

GND

1SHDN

V

DD

2OUT

2IN –

2IN+

2SHDN

3

2

4

5

(TOP VIEW)

1

OUT

GND

IN+

VDD

IN –

1

2

3

5

6

7

14

13

12

11

10

9

8

1OUT

1IN –

1IN+

GND

NC

1SHDN

NC

V

DD

2OUT

2IN –

2IN+

NC

2SHDN

NC

(TOP VIEW)

TLV2471

DBV PACKAGE

3

2

4

6

(TOP VIEW)

1

OUT

GND

IN+

VDD

IN –

TLV2470

DBV PACKAGE

5

SHDN

1

2

3

4

8

7

6

5

NC

IN –

IN +

GND

SHDN

V

DD

OUT

NC

TLV2470

D OR P PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

NC

IN –

IN +

GND

NC

V

DD

OUT

NC

TLV2471

D OR P PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

1OUT

1IN –

1IN +

GND

V

DD

2OUT

2IN –

2IN+

TLV2472

D, DGN, OR P PACKAGE

(TOP VIEW)

TLV2473

DGQ PACKAGE

(TOP VIEW)

TLV2473

D OR N PACKAGE

1

2

3

5

6

7

14

13

12

11

10

9

8

1OUT

1IN –

1IN+

V

DD

2IN+

2IN –

2OUT

4OUT

4IN –

4IN+

GND

3IN+

3IN –

3OUT

(TOP VIEW)

TLV2474

D, N, OR PWP PACKAGE

NC – No internal connection

description (continued)

Three members of the family (TLV2470/3/5) offer a shutdown terminal for conserving battery life in portable

applications. During shutdown, the outputs are placed in a high-impedance state and the amplifier consumes

only 350 nA/channel. The family is fully specified at 3 V and 5 V across an expanded industrial temperature

range (– 40

°

C to 125

°

C). The singles and duals are available in the SOT23 and MSOP packages, while the

quads are available in TSSOP. The TLV2470 offers an amplifier with shutdown functionality all in a 6-pin SOT23

package, making it perfect for high density power-sensitive circuits.

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

DD

 (see Note 1) 

7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Differential input voltage, V

ID

 

 

±

V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous total power dissipation 

See Dissipation Rating Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

: C suffix 

0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

I suffix 

– 40

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Maximum junction temperature, T

J

 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

  – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 

260

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltage values, except differential voltages, are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

θ

JC

(

°

C/W)

θ

JA

(

°

C/W)

TA 

 25

°

C

POWER RATING

D (8)

38.3

176

710 mW

D (14)

26.9

122.3

1022 mW

D (16)

25.7

114.7

1090 mW

DBV (5)

55

324.1

385 mW

DBV (6)

55

294.3

425 mW

DGN (8)

4.7

52.7

2.37 W

DGQ (10)

4.7

52.3

2.39 W

N (14, 16)

32

78

1600 mW

P (8)

41

104

1200 mW

PWP (14)

2.07

30.7

4.07 W

PWP (16)

2.07

29.7

4.21 W

recommended operating conditions

MIN

MAX

UNIT

Supply voltage VDD

Single supply

2.7

6

V

Supply voltage, VDD

Split supply

±

1.35

±

3

V

Common-mode input voltage range, VICR

–0.2

VDD+0.2

V

Operating free air temperature TA

C-suffix

0

70

°

C

Operating free-air temperature, TA

I-suffix

– 40

125

°

C

Shutdown on/off voltage level‡

VIH

2

V

Shutdown on/off voltage level‡

VIL

0.8

V

‡ Relative to GND

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, V

DD

 = 3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

V

V

/2

TLV247x

25

°

C

250

2200

VIO

Input offset voltage

V

V

/2

TLV247x

Full range

2400

µ

V

VIO

Input offset voltage

V

V

/2

TLV247xA

25

°

C

250

1600

µ

V

V

V

/2

TLV247xA

Full range

1800

α

VIO

Temperature coefficient of input

VDD = VDD/2

0 4

µ

V/

°

C

α

VIO

offset voltage

VDD = VDD/2

VIC = 0, 

0.4

µ

V/

°

C

IC

0,

VO = 0,

R

50

25

°

C

1.5

50

IIO

Input offset current

RS = 50 

TLV247xC

Full range

100

TLV247xI

Full range

300

pA

25

°

C

2

50

pA

IIB

Input bias current

TLV247xC

Full range

100

TLV247xI

Full range

300

IOH = 2 5 mA

25

°

C

2.85

2.94

VOH

High level output voltage

VIC = VDD/2

IOH = – 2.5 mA

Full range

2.8

V

VOH

High-level output voltage

VIC = VDD/2

IOH = 10 mA

25

°

C

2.6

2.74

V

IOH = – 10 mA

Full range

2.5

IOL = 2 5 mA

25

°

C

0.07

0.15

VOL

Low level output voltage

VIC = VDD/2

IOL = 2.5 mA

Full range

0.2

V

VOL

Low-level output voltage

VIC = VDD/2

IOL = 10 mA

25

°

C

0.2

0.35

V

IOL = 10 mA

Full range

0.4

Sourcing

25

°

C

30

Sourcing

Full range

20

S

i

25

°

C

62

Sourcing,

Outside of rails‡

TLV247xC

Full range

60

IOS

Short circuit output current

Outside of rails‡

TLV247xI

Full range

59

mA

IOS

Short-circuit output current

Sinking

25

°

C

30

mA

Sinking

Full range

20

Si ki

25

°

C

62

Sinking,

Outside of rails‡

TLV247xC

Full range

60

Outside of rails‡

TLV247xI

Full range

59

IO

Output current

VO = 0.5 V from rail

25

°

C

±

22

mA

AVD

Large-signal differential voltage 

VO(PP) = 1 V

R

10 k

25

°

C

90

116

dB

AVD

g

g

g

amplification

VO(PP) = 1 V,

RL = 10 k

Full range

88

dB

ri(d)

Differential input resistance

25

°

C

1012

CIC

Common-mode input 

capacitance

f = 10 kHz

25

°

C

19.3

pF

zo

Closed-loop output impedance

f = 10 kHz,

AV = 10

25

°

C

2

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

‡ Depending on package dissipation rating

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, V

DD

 = 3 V (unless otherwise noted)

(continued)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

V

0 t 3 V

25

°

C

61

78

VIC = 0 to 3 V,

RS = 50

TLV247xC

Full range

59

CMRR

Common mode rejection ratio

RS = 50

TLV247xI

Full range

58

dB

CMRR

Common-mode rejection ratio

VIC = –0.2 to 3.2 V,

25

°

C

62

78

dB

VIC =  0.2 to 3.2 V,

RS = 50

,

TLV247xC

Full range

60

Outside of rails

TLV247xI

Full range

59

VDD =  2.7 V to 6 V,

VIC = VDD /2,

25

°

C

74

90

kSVR

Supply voltage rejection ratio

DD

,

No load

IC

DD

,

Full range

66

dB

kSVR

y

g

j

(

VDD  /

VIO)

VDD =  3 V to 5 V,

VIC = VDD /2,

25

°

C

77

92

dB

DD

,

No load

IC

DD

,

Full range

68

IDD

Supply current (per channel)

VO = 1 5 V

No load

25

°

C

550

750

µ

A

IDD

Supply current (per channel)

VO = 1.5 V,

No load

Full range

800

µ

A

Supply current in shutdown

25

°

C

350

1500

IDD(SHDN)

Su

ly current in shutdown

mode (TLV2470, TLV2473,

SHDN = 0 V

TLV247xC

Full range

2000

nA

(

)

TLV2475) (per channel)

TLV247xI

Full range

4000

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

operating characteristics at specified free-air temperature, V

DD

 = 3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

SR

Slew rate at unity gain

VO(PP) = 0.8 V,

CL = 150 pF,

25

°

C

1.1

1.4

V/

µ

s

SR

Slew rate at unity gain

O(PP)

,

RL = 10 k

L

,

Full range

0.6

V/

µ

s

V

Equivalent input noise voltage

f = 100 Hz

25

°

C

28

nV/

Hz

Vn

Equivalent input noise voltage

f = 1 kHz

25

°

C

15

nV/

Hz

In

Equivalent input noise current

f = 1 kHz

25

°

C

0.405

pA /

Hz

VO(PP) = 2 V,

AV = 1

0.02%

THD + N

Total harmonic distortion plus noise

VO(PP) = 2 V,

RL = 10 k

,

AV = 10

25

°

C

0.1%

f = 1 kHz

AV = 100

0.5%

t(on)

Amplifier turnon time

RL OPEN‡

25

°

C

5

µ

s

t(off)

Amplifier turnoff time

RL = OPEN‡

25

°

C

250

ns

Gain-bandwidth product

f = 10 kHz,

RL = 600 

25

°

C

2.8

MHz

V(STEP)PP = 2 V,

AV = –1,

0.1%

1.5

t

Settling time

V

,

CL = 10 pF,

RL = 10 k

0.01%

25

°

C

3.9

µ

s

ts

Settling time

V(STEP)PP = 2 V,

AV = –1,

0.1%

25

°

C

1.6

µ

s

V

,

CL = 56 pF,

RL = 10 k

0.01%

4

φ

m

Phase margin

RL = 10 k

,

CL = 1000 pF

25

°

C

61

°

Gain margin

RL = 10 k

,

CL = 1000 pF

25

°

C

15

dB

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

‡ Depending on package dissipation rating

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, V

DD

 = 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

V

V

/2

TLV247x

25

°

C

250

2200

VIO

Input offset voltage

V

V

/2

TLV247x

Full range

2400

µ

V

VIO

Input offset voltage

V

V

/2

TLV247xA

25

°

C

250

1600

µ

V

V

V

/2

TLV247xA

Full range

2000

α

VIO

Temperature coefficient of input

V

V

/2

0 4

µ

V/

°

C

α

VIO

offset voltage

VDD = VDD/2

VIC 0 VO 0

0.4

µ

V/

°

C

VIC = 0,   VO = 0,

RS = 50

25

°

C

1.7

50

IIO

Input offset current

RS = 50 

TLV247xC

Full range

100

TLV247xI

Full range

300

pA

25

°

C

2.5

50

pA

IIB

Input bias current

TLV247xC

Full range

100

TLV247xI

Full range

300

IOH = 2 5 mA

25

°

C

4.85

4.96

VOH

High level output voltage

VIC = VDD/2

IOH = – 2.5 mA

Full range

4.8

V

VOH

High-level output voltage

VIC = VDD/2

IOH = 10 mA

25

°

C

4.72

4.82

V

IOH = – 10 mA

Full range

4.65

IOL = 2 5 mA

25

°

C

0.07

0.15

VOL

Low level output voltage

VIC = VDD/2

IOL = 2.5 mA

Full range

0.2

V

VOL

Low-level output voltage

VIC = VDD/2

IOL = 10 mA

25

°

C

0.178

0.28

V

IOL = 10 mA

Full range

0.35

Sourcing

25

°

C

90

Sourcing

Full range

60

S

i

25

°

C

63

Sourcing,

Outside of rails‡

TLV247xC

Full range

61

IOS

Short circuit output current

Outside of rails‡

TLV247xI

Full range

58

mA

IOS

Short-circuit output current

Sinking

25

°

C

110

mA

Sinking

Full range

60

Si ki

25

°

C

63

Sinking,

Outside of rails‡

TLV247xC

Full range

61

Outside of rails‡

TLV247xI

Full range

58

IO

Output current

VO = 0.5 V from rail

25

°

C

±

35

mA

AVD

Large-signal differential voltage 

VO(PP) = 3 V

R

10 k

25

°

C

92

120

dB

AVD

g

g

g

amplification

VO(PP) = 3 V,

RL = 10 k

Full range

91

dB

ri(d)

Differential input resistance

25

°

C

1012

CIC

Common-mode input 

capacitance

f = 10 kHz

25

°

C

18.9

pF

zo

Closed-loop output impedance

f = 10 kHz,

AV = 10

25

°

C

1.8

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

‡ Depending on package dissipation rating

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, V

DD

 = 5 V (unless otherwise noted)

(continued)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

V

0 t 5 V

25

°

C

64

84

VIC = 0 to 5 V,

RS = 50

TLV247xC

Full range

63

CMRR

Common mode rejection ratio

RS = 50

TLV247xI

Full range

58

dB

CMRR

Common-mode rejection ratio

VIC = –0.2 to 5.2 V,

25

°

C

63

82

dB

VIC =  0.2 to 5.2 V,

RS = 50

,

TLV247xC

Full range

61

Outside of rails

TLV247xI

Full range

58

VDD =  2.7 V to 6 V,

VIC = VDD /2,

25

°

C

74

90

kSVR

Supply voltage rejection ratio

DD

,

No load

IC

DD

,

Full range

66

dB

kSVR

y

g

j

(

VDD  /

VIO)

VDD =  3 V to 5 V,

VIC = VDD /2,

25

°

C

77

92

dB

DD

,

No load

IC

DD

,

Full range

66

IDD

Supply current (per channel)

VO = 2 5 V

No load

25

°

C

600

900

µ

A

IDD

Supply current (per channel)

VO = 2.5 V,

No load

Full range

1000

µ

A

Supply current in shutdown

25

°

C

1000

2500

nA

IDD(SHDN)

Su

ly current in shutdown

mode (TLV2470, TLV2473,

SHDN = 0 V

TLV247xC

Full range

3000

nA

(

)

TLV2475) (per channel)

TLV247xI

Full range

6000

nA

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

operating characteristics at specified free-air temperature, V

DD

 = 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

SR

Slew rate at unity gain

VO(PP) = 2 V,

CL = 150 pF,

25

°

C

1.1

1.5

V/

µ

s

SR

Slew rate at unity gain

O(PP)

,

RL = 10 k

L

,

Full range

0.7

V/

µ

s

V

Equivalent input noise voltage

f = 100 Hz

25

°

C

28

nV/

Hz

Vn

Equivalent input noise voltage

f = 1 kHz

25

°

C

15

nV/

Hz

In

Equivalent input noise current

f = 1 kHz

25

°

C

0.39

pA /

Hz

VO(PP) = 4 V,

AV = 1

0.01%

THD + N

Total harmonic distortion plus noise

VO(PP) = 4 V,

RL = 10 k

,

AV = 10

25

°

C

0.05%

f = 1 kHz

AV = 100

0.3%

t(on)

Amplifier turnon time

RL OPEN‡

25

°

C

5

µ

s

t(off)

Amplifier turnoff time

RL = OPEN‡

25

°

C

250

ns

Gain-bandwidth product

f = 10 kHz,

RL = 600 

25

°

C

2.8

MHz

V(STEP)PP = 2 V,

AV = –1,

0.1%

1.8

t

Settling time

V

,

CL = 10 pF,

RL = 10 k

0.01%

25

°

C

3.3

µ

s

ts

Settling time

V(STEP)PP = 2 V,

AV = –1,

0.1%

25

°

C

1.7

µ

s

V

,

CL = 56 pF,

RL = 10 k

0.01%

3

φ

m

Phase margin

RL = 10 k

,

CL = 1000 pF

25

°

C

68

°

Gain margin

RL = 10 k

,

CL = 1000 pF

25

°

C

23

dB

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

‡ Disable and enable time are defined as the interval between application of logic signal to SHDN and the point at which the supply current has

reached half its final value.

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

VIO

Input offset voltage

vs Common-mode input voltage

1, 2

IIB

Input bias current

vs Free air temperature

3 4

IIO

Input offset current

vs Free-air temperature

3, 4

VOH

High-level output voltage

vs High-level output current

5, 7

VOL

Low-level output voltage

vs Low-level output current

6, 8

Zo

Output impedance

vs Frequency

9

IDD

Supply current

vs Supply voltage

10

PSRR

Power supply rejection ratio

vs Frequency

11

CMRR

Common-mode rejection ratio

vs Frequency

12

Vn

Equivalent input noise voltage

vs Frequency

13

VO(PP)

Maximum peak-to-peak output voltage

vs Frequency

14, 15

AVD

Differential voltage gain and phase

vs Frequency

16, 17

φ

m

Phase margin

vs Load capacitance

18, 19

Gain margin

vs Load capacitance

20, 21

Gain-bandwidth product

vs Supply voltage

22

SR

Slew rate

vs Supply voltage

23

SR

Slew rate

vs Free-air temperature

24, 25

Crosstalk

vs Frequency

26

THD+N

Total harmonic distortion + noise

vs Frequency

27, 28

VO

Large and small signal follower

vs Time

29 – 32

Shutdown pulse response

vs Time

33, 34

Shutdown forward and reverse isolation

vs Frequency

35, 36

IDD(SHDN)

Shutdown supply current

vs Supply voltage

37

IDD(SHDN)

Shutdown supply current

vs Free-air temperature

38

IDD(SHDN)

Shutdown pulse current

vs Time

39, 40

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 1

–800

–600

–400

–200

0

200

400

600

–0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

INPUT OFFSET VOLTAGE

vs

COMMON-MODE INPUT VOLTAGE

IO

V

Input Offset V

oltage –

–V

µ

VDD=3 V

  TA=25

°

 C

VICR – Common-Mode Input Voltage – V

Figure 2

–800

–600

–400

–200

0

200

400

600

–0.5

0.5

1.5

2.5

3.5

4.5

5.5

IO

V

Input Offset V

oltage –

–V

µ

VDD=5 V

    TA=25 

°

C

INPUT OFFSET VOLTAGE

vs

COMMON-MODE INPUT VOLTAGE

VICR – Common-Mode Input Voltage – V

Figure 3

–10

0

10

20

30

40

50

–55 –35 –15

5

25

45

65

85 105 125

INPUT BIAS AND INPUT OFFSET

CURRENTS

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – 

°

C

I

IO

– Input Offset Current – pA

I

IB

– Input Bias Current – pA

IIB

IIO

VDD=3 V

Figure 4

–10

0

10

20

30

40

50

–55 –35 –15

5

25

45

65

85 105 125

INPUT BIAS AND INPUT OFFSET

CURRENTS

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – 

°

C

I

IO

– Input Offset Current – pA

I

IB

– Input Bias Current – pA

IIB

IIO

VDD=5 V

Figure 5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

10

20

30

40

50

60

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

IOH – High-Level Output Current – mA

VDD=3 V

TA=125

°

C

TA=85

°

C

V

OH

– High-Level Output V

oltage – V

TA=25

°

C

TA=–40

°

C

Figure 6

0

0.5

1.0

1.5

2.0

2.5

3.0

0

10

20

30

40

50

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

IOL – Low-Level Output Current – mA

VDD=3 V

TA=125

°

C

TA=85

°

C

OL

V

 Low-Level Output V

oltage – V

TA=25

°

C

TA=–40

°

C

Figure 7

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0

20

40

60

80

100 120 140 160

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

IOH – High-Level Output Current – mA

VDD=5 V

TA=125

°

C

TA=85

°

C

V

OH

– High-Level Output V

oltage – V

TA=25

°

C

TA=–40

°

C

Figure 8

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0

20

40

60

80

100

120

140

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

IOL – Low-Level Output Current – mA

VDD=5 V

TA=125

°

C

TA=85

°

C

OL

V

 Low-Level Output V

oltage – V

TA=25

°

C

TA=–40

°

C

Figure 9

OUTPUT IMPEDANCE

vs

FREQUENCY

f – Frequency – Hz

100

1k

10k

100k

1M

10M

– Output Impedance –

Z

o

0.1

0.01

1000

10

1

100

AV=10

VDD=3 & 5 V

TA=25

°

C

AV=100

AV=1

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

11

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD – Supply Voltage – V

I

DD

– Supply Current – mA

AV= 1

SHDN= VDD

Per Channel

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

TA=125

°

C

TA=85

°

C

TA=25

°

C

TA=–40

°

C

30

40

50

60

70

80

90

100

POWER SUPPLY REJECTION RATIO

vs

FREQUENCY

f – Frequency – Hz

– Power Supply Rejection Ratio – dB

PSRR

10

100

1k

10k

100k

1M

10M

VDD=3 & 5 V

RF=5  k

RI=50 

TA=25

°

C

PSRR+

PSRR–

Figure 11

Figure 12

50

60

70

80

90

100

110

120

130

COMMON-MODE REJECTION RATIO

vs

FREQUENCY

f – Frequency – Hz

100

1k

10k

100k

1M

10M

CMRR – Common-Mode Rejection Ratio – dB

VDD=5 V

VIC=2.5 V

VDD=3 V

VIC=1.5 V

Figure 13

0

10

20

30

40

50

60

70

80

EQUIVALENT NOISE VOLTAGE

vs

FREQUENCY

f – Frequency – Hz

1k

10k

100k

10

100

nV/

Hz

– Equivalent Input Noise V

oltage –

V

n

VDD=3 & 5 V

AV= 10

VIN= VDD/2

TA=25

°

C

Figure 14

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

MAXIMUM PEAK-TO-PEAK

OUTPUT VOLTAGE

vs

FREQUENCY

f – Frequency – Hz

1M

10k

100k

V

O(PP)

– Maximum Peak-T

o-Peak Output V

oltage – V

VO(PP)=5 V

VO(PP)=3 V

THD+N 

2.0%

RL=10 k

TA=25

°

C

Figure 15

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

MAXIMUM PEAK-TO-PEAK

OUTPUT VOLTAGE

vs

FREQUENCY

f – Frequency – Hz

1M

10k

100k

VO(PP)=3 V

VO(PP)=5 V

THD+N 

2.0%

RL=600 

TA=25

°

C

V

O(PP)

– Maximum Peak-T

o-Peak Output V

oltage – V

Figure 16

DIFFERENTIAL VOLTAGE GAIN AND PHASE

vs

FREQUENCY

Frequency – Hz

100

1k

10k

100k

– Differential V

oltage Gain – dB

20

0

–40

–20

60

40

80

100

–135

–180

–270

–225

–45

–90

0

45

Phase – 

°

1M

10M

100M

VDD=

±

3

RL=600 

CL=0

TA=25

°

C

A

VD

Figure 17

DIFFERENTIAL VOLTAGE GAIN AND PHASE

vs

FREQUENCY

Frequency – Hz

100

1k

10k

100k

20

0

–40

–20

60

40

80

100

–135

–180

–270

–225

–45

–90

0

45

Phase – 

°

1M

10M

100M

VDD=

±

5

RL=600 

CL=0

TA=25

°

C

– Differential V

oltage Gain – dB

A

VD

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

12

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 18

0

10

20

30

40

50

60

70

80

90

PHASE MARGIN

vs

LOAD CAPACITANCE

CL – Load Capacitance – pF

100

1k

10k

100k

VDD=3 V 

RL=10 k

Ω 

TA=25

°

C

See Figure 42

Rnull=100

Rnull=50

Rnull=20

Rnull=0

φ

m

– Phase Margin – 

°

Figure 19

0

10

20

30

40

50

60

70

80

90

100

PHASE MARGIN

vs

LOAD CAPACITANCE

CL – Load Capacitance – pF

100

1k

10k

100k

VDD=5V

RL=10 k

TA=25

°

C

See Figure 42

Rnull=100

Rnull=50

Rnull=0

Rnull=20

φ

m

– Phase Margin – 

°

Figure 20

Rnull=100

Rnull=0

VDD=3V

RL=10 k

TA=25

°

C

Rnull=20

Rnull=50

GAIN MARGIN

vs

LOAD CAPACITANCE

CL – Load Capacitance – pF

100

1k

10k

100k

Gain Margin – dB

15

20

30

25

5

10

0

Figure 21

GAIN MARGIN

vs

LOAD CAPACITANCE

CL – Load Capacitance – pF

100

1k

10k

100k

Gain Margin – dB

15

20

30

25

5

10

0

VDD=5V

RL=10 k

TA=25

°

C

Rnull=0

Rnull=50

Rnull=20

Rnull=100

35

Figure 22

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

CL=11 pF

f=10 kHz

TA=25

°

C

RL=10 k

GAIN-BANDWIDTH PRODUCT

vs

SUPPLY VOLTAGE

VDD – Supply Voltage – V

Gain-Bandwidth Product – MHz

RL=600 

Figure 23

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VO(PP)=1.5 V

AV=–1

RL=10 k

CL=150 pF

SR–

SLEW RATE

vs

SUPPLY VOLTAGE

VDD – Supply Voltage – V

SR+

SR – Slew Rate – V/

µ

s

Figure 24

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

–55 –35 –15

5

25

45

65

85 105 125

VDD=3  V

RL=10 k

CL=150 pF

AV=–1

SR–

SLEW RATE

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – 

°

C

SR+

SR – Slew Rate – V/

µ

s

Figure 25

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

–55 –35 –15

5

25

45

65

85 105 125

VDD=5  V

RL=10 k

CL=150 pF

AV=–1

SR–

SLEW RATE

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – 

°

C

SR – Slew Rate – V/

µ

s

SR+

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TYPICAL CHARACTERISTICS

Figure 26

CROSSTALK

vs

FREQUENCY

f – Frequency – Hz

10

100

10 k

100 k

Crosstalk – dB

–100

–120

–140

–60

–80

–40

–160

1 k

–20

0

VDD = 3V & 5V

AV = 1     

RL= 600

VI(PP)=2V

 All Channels

Figure 27

10

1k

10k

100

0.001

1

0.01

0.1

100k

TOTAL HARMONIC

DISTORTION PLUS NOISE

vs

FREQUENCY

THD+N–T

otal Harmonic Distortion + Noise

f – Frequency – Hz

AV = 10

AV = 1

VDD = 3 V

RL = 10 k

V0 =  2 VPP

TA = 25

°

C

AV = 100

Figure 28

10

1k

10k

100

0.001

1

0.01

0.1

100k

VDD = 5 V

RL = 10 k

V0 =  4 VPP

TA = 25

°

C

TOTAL HARMONIC

DISTORTION PLUS NOISE

vs

FREQUENCY

THD+N–T

otal Harmonic Distortion + Noise

f – Frequency – Hz

AV = 100

AV = 10

AV = 1

Figure 29

0

1

2

3

4

5

6

7

8

9

10

t – Time – 

µ

s

– Output V

oltage 

LARGE SIGNAL FOLLOWER

 PULSE RESPONSE

vs

TIME

V

O

VDD  = 3 V

RL = 10 k

CL = 8 pF

f = 85 kHz

TA = 25

°

C

VI (2 V/DIV)

VO (1 V/DIV)

Figure 30

t – Time – 

µ

s

LARGE SIGNAL FOLLOWER

 PULSE RESPONSE

vs

TIME

0

1

2

3

4

5

6

7

8

9

10

VDD  = 5 V

RL = 10 k

CL = 8 pF

f = 85 kHz

TA = 25

°

C

VI (2 V/DIV)

VO (1 V/DIV)

– Output V

oltage 

V

O

Figure 31

t – Time – 

µ

s

SMALL SIGNAL FOLLOWER

 PULSE RESPONSE

vs

TIME

0

100

200

300

400

500

VDD  = 3 V

RL = 10 k

CL = 8 pF

f = 1 MHz

TA = 25

°

C

VI (50 mV/DIV)

VO (50 mV/DIV)

– Output V

oltage 

V

O

Figure 32

t – Time – 

µ

s

SMALL SIGNAL FOLLOWER

 PULSE RESPONSE

vs

TIME

0

100

200

300

400

500

VDD  = 5 V

RL = 10 k

CL = 8 pF

f = 1 MHz

TA = 25

°

C

VI (50 mV/DIV)

VO (50 mV/DIV)

– Output V

oltage 

V

O

Figure 33

VDD  = 3 V

CL = 8 pF

TA = 25

°

C

0

2

4

6

8

10 12

14

t – Time – 

µ

s

16

SHUTDOWN (ON AND OFF)

 PULSE RESPONSE

vs

TIME

VSHDN (2 V/DIV)

VO (500 mV/DIV)

RL = 600 

RL = 10 k

– Output V

oltage 

V

O

Figure 34

SHUTDOWN (ON AND OFF)

 PULSE RESPONSE

vs

TIME

0

2

4

6

8

10

12 14

16

t – Time – 

µ

s

RL = 600 

RL = 10 k

18

VDD  = 5 V

CL = 8 pF

TA = 25

°

C

VSHDN (2 V/DIV)

VO (1 V/DIV)

– Output V

oltage 

V

O

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TYPICAL CHARACTERISTICS

Figure 35

RL=10 k

SHUTDOWN FORWARD

ISOLATION

vs

FREQUENCY

f – Frequency – Hz

100

1k

10k

100k

60

40

0

20

80

100

1M

10M

RL=600 

Shutdown Forward Isolation - dB

120

VDD = 3 & 5 V

CL=0 pF

AV  = 1

VI(PP)=0.1, 1.5, 3 V

Figure 36

RL=10 k

SHUTDOWN REVERSE ISOLATION

vs

FREQUENCY

f – Frequency – Hz

100

1k

10k

100k

60

40

0

20

80

100

1M

10M

RL=600 

Shutdown Forward Isolation - dB

120

VDD = 3 & 5 V

RL=10 k

CL=0 pF

AV  = 1

VIN=0.1, 1.5, 3 Vp-p

Figure 37

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

TA=125

TA=85

SHUTDOWN SUPPLY CURRENT

vs

SUPPLY VOLTAGE

VDD – Supply Voltage – V

– Shutdown Supply Current –

I DD(SHDN)

Shutdown On

RL=OPEN

VI=VDD/2

µ

A

TA=25

 TA=–40

Figure 38

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

–55 –35 –15

5

25

45

65

85 105 125

SHUTDOWN SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – 

°

C

SD MODE Channel 1 & 2

AV  = 1

RL= OPEN

VIN=VDD/2

DD

I

Shutdown Supply Current –

–A

µ

VDD=3 V

VDD=5 V

Figure 39

–1

–2

–4

–3

2

1

3

4

Shutdown Pulse

IDD RL=10 k

SHUTDOWN PULSE CURRENT

vs

TIME

t – Time – 

µ

s

1.25

0.75

–0.5

0.5

1.5

1.75

2

VDD = 3 V

CL=8 pF

TA=25

°

C

1

0.25

0

–0.25

0

–8

–7

–5

–6

0

4

8

12

16

20

24

28 30

I

DD

– Supply Current – mA

IDD RL=600

Shutdown Pulse – V

Figure 40

–2

–4

2

6

Shutdown Pulse – V

Shutdown Pulse

IDD RL=10 k

SHUTDOWN PULSE CURRENT

vs

TIME

t – Time – 

µ

s

1.25

0.75

–0.5

0.5

1.5

1.75

2

VDD = 5 V

CL=8 pF

TA=25

°

C

1

0.25

0

–0.25

0

–8

–6

0

4

8

30

24

20

16

12

I

DD

– Supply Current – mA

IDD RL=600 

4

–10

–12

28

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PARAMETER MEASUREMENT INFORMATION

_

+

Rnull

RL

CL

Figure 41

APPLICATION INFORMATION

driving a capacitive load

When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the

device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater

than 10 pF, it is recommended that a resistor be placed in series (R

NULL

) with the output of the amplifier, as

shown in Figure 42. A minimum value of 20 

 should work well for most applications.

CLOAD

RF

Input

Output

RG

RNULL

_

+

Figure 42. Driving a Capacitive Load

offset voltage

The output offset voltage, (V

OO

) is the sum of the input offset voltage (V

IO

) and both input bias currents (I

IB

) times

the corresponding gains. The following schematic and formula can be used to calculate the output offset

voltage:

V

OO

+

V

IO

ǒ

1

)

ǒ

R

F

R

G

Ǔ

Ǔ

"

I

IB

)

R

S

ǒ

1

)

ǒ

R

F

R

G

Ǔ

Ǔ

"

I

IB–

R

F

+

VI

+

RG

RS

RF

IIB–

VO

IIB+

Figure 43. Output Offset Voltage Model

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APPLICATION INFORMATION

general configurations

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often

required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier

(see Figure 44).

VI

VO

C1

+

RG

RF

R1

f

–3dB

+

1

2

p

R1C1

V

O

V

I

+

ǒ

1

)

R

F

R

G

Ǔ

ǒ

1

1

)

sR1C1

Ǔ

Figure 44. Single-Pole Low-Pass Filter

If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this

task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.

Failure to do this can result in phase shift of the amplifier.

VI

C2

R2

R1

C1

RF

RG

R1 = R2 = R

C1 = C2 = C

Q = Peaking Factor

(Butterworth Q = 0.707)

(

=

1

Q

2 –

)

RG

RF

_

+

f

–3dB

+

1

2

p

RC

Figure 45. 2-Pole Low-Pass Sallen-Key Filter

shutdown function

Three members of the TLV247x family (TLV2470/3/5) have a shutdown terminal for conserving battery life in

portable applications. When the shutdown terminal is tied low, the supply current is reduced to 350 nA/channel,

the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the

shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care

should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place

the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V

DD

/2.

Therefore, when operating the device with split supply voltages (e.g. 

±

2.5 V), the shutdown terminal needs to

be pulled to V

DD

– (not GND) to disable the operational amplifier.

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APPLICATION INFORMATION

shutdown function (continued)

The amplifier’s output with a shutdown pulse is shown in Figures 33 and 34. The amplifier is powered with a

single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff

times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The

times for the single, dual, and quad are listed in the data tables.

Figures 35 and 36 show the amplifier’s forward and reverse isolation in shutdown. The operational amplifier is

powered by 

±

1.35-V supplies and configured as a voltage follower (A

= 1). The isolation performance is plotted

across frequency using 0.1-V

PP

, 1.5-V

PP

, and 2.5-V

PP

 input signals. During normal operation, the amplifier

would not be able to handle a 2.5-V

PP

 input signal with a supply voltage of 

±

1.35 V since it exceeds the

common-mode input voltage range (V

ICR

). However, this curve illustrates that the amplifier remains in shutdown

even under a worst case scenario.

circuit layout considerations

To achieve the levels of high performance of the TLV247x, follow proper printed-circuit board design techniques.

A general set of guidelines is given in the following.

D

Ground planes – It is highly recommended that a ground plane be used on the board to provide all

components with a low inductive ground connection. However, in the areas of the amplifier inputs and

output, the ground plane can be removed to minimize the stray capacitance.

D

Proper power supply decoupling – Use a 6.8-

µ

F tantalum capacitor in parallel with  a 0.1-

µ

F ceramic

capacitor on each supply terminal.  It may be possible to share the tantalum among several amplifiers

depending on the application, but a 0.1-

µ

F ceramic capacitor should always be used on the supply terminal

of every amplifier.  In addition, the 0.1-

µ

F capacitor should be placed as close as possible to the supply

terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less

effective. The designer should strive for distances of less than 0.1 inches between the device power

terminals and the ceramic capacitors.

D

Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins

will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board

is the best implementation.

D

Short trace runs/compact part placements – Optimum high performance is achieved when stray series

inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,

thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of

the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at

the input of the amplifier.

D

Surface-mount passive components – Using surface-mount passive components is recommended for high

performance amplifier circuits for several reasons.  First, because of the extremely low lead inductance of

surface-mount components, the problem with stray series inductance is greatly reduced.   Second, the small

size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray

inductance and capacitance.  If leaded components are used, it is recommended that the  lead lengths be

kept as short as possible.

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APPLICATION INFORMATION

general PowerPAD

 design considerations

The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are

constructed using a downset leadframe upon which the die is mounted [see Figure 46(a) and Figure 46(b)]. This

arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see

Figure 46(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance

can be achieved by providing a good thermal path away from the thermal pad.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.

During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be

soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,

heat can be conducted away from the package into either a ground plane or other heat dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of

surface mount with the, heretofore, awkward mechanical methods of heatsinking.

DIE

Side View (a)

End View (b)

Bottom View (c)

DIE

Thermal

Pad

NOTE A: The thermal pad is electrically isolated from all terminals in the package.

Figure 46. Views of Thermally Enhanced DGN Package

Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the

recommended approach.

68 mils x 70 mils) with 5 vias

(Via diameter = 13 mils

78 mils x 94 mils) with 9 vias

(Via diameter = 13 mils)

Thermal Pad Area

Single or Dual

Quad

Figure 47. PowerPAD PCB Etch and Via Pattern

PowerPAD is a trademark of Texas Instruments Incorporated.

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APPLICATION INFORMATION

general PowerPAD design considerations (continued)

1.

Prepare the PCB with a top side etch pattern as shown in Figure 47. There should be etch for the leads as

well as etch for the thermal pad.

2.

Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils

in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.

3.

Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps

dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13-mil

diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad

area to be soldered so that wicking is not a problem.

4.

Connect all holes to the internal ground plane.

5.

When connecting these holes to the ground plane, do not use the typical web or spoke via connection

methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat

transfer during soldering operations. This makes the soldering of vias that have plane connections easier.

In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,

the holes under the TLV247x PowerPAD package should make their connection to the internal ground plane

with a complete connection around the entire circumference of the plated-through hole.

6.

The top-side solder mask should leave the terminals of the package and the thermal pad area with its five

holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes

of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the

reflow process.

7.

Apply solder paste to the exposed thermal pad area and all of the IC terminals.

8.

With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the solder

reflow operation as any standard surface-mount component. This results in a part that is properly installed.

For a given 

θ

JA

, the maximum power dissipation is shown in Figure 48 and is calculated by the following formula:

P

D

+

ǒ

T

MAX

–T

A

q

JA

Ǔ

Where:

P

D

= Maximum power dissipation of TLV247x IC (watts)

T

MAX

= Absolute maximum junction temperature (150

°

C)

T

A

= Free-ambient air temperature (

°

C)

θ

JA

θ

JC 

+

 

θ

CA

θ

JC

= Thermal coefficient from junction to case

θ

CA

= Thermal coefficient from case to ambient air (

°

C/W)

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APPLICATION INFORMATION

general PowerPAD design considerations (continued)

TJ  = 150

°

C

4

3

2

0

–55 –40

–10

20 35

Maximum Power Dissipation – W

5

6

MAXIMUM POWER DISSIPATION

vs

FREE-AIR TEMPERATURE

7

65

95

125

1

TA – Free-Air Temperature – 

°

C

DGN Package

Low-K Test PCB

θ

JA = 52.3

°

C/W

SOT-23 Package

Low-K Test PCB

θ

JA = 324

°

C/W

–25

5

50

80

110

PWP Package

Low-K Test PCB

θ

JA = 29.7

°

C/W

SOIC Package

Low-K Test PCB

θ

JA = 176

°

C/W

PDIP Package

Low-K Test PCB

θ

JA = 104

°

C/W

NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.

Figure 48. Maximum Power Dissipation vs Free-Air Temperature

The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent

power and output power. The designer should never forget about the quiescent heat generated within the

device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most

of the heat dissipation is at low output voltages with high output currents. Figure 49 to Figure 54 show this effect,

along with the quiescent heat, with an ambient air temperature of 70

°

C and 125

°

C. When using V

DD

 = 3 V, there

is generally not a heat problem with an ambient air temperature of 70

°

C. But, when using V

DD

 = 5 V, the

packages are severely limited in the amount of heat it can dissipate. The other key factor when looking at these

graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat

dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation

properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted

on the PCB. As more trace and copper area is placed around the device, 

θ

JA

 decreases and the heat dissipation

capability increases. The currents and voltages shown in these graphs are for the total package. For the dual

or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the

proper package.

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APPLICATION INFORMATION

general PowerPAD design considerations (continued)

Figure 49

100

80

40

0

0

0.25

0.5

0.75

– Maximum RMS Output Current – mA

140

180

1

1.25

160

120

60

20

| VO | – RMS Output Voltage – V

I O||

Maximum Output

Current Limit Line

TLV2470, TLV2471†

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

1.5

Safe Operating Area

VDD = 

±

 3 V

TJ  = 150

°

C

TA = 125

°

C

A

B

C

Packages With

θ

JA 

 110

°

C/W

at TA = 125

°

C

or

θ

JA 

 355

°

C/W

at TA = 70

°

C

Figure 50

100

80

40

0

0

0.5

1

1.5

– Maximum RMS Output Current – mA

140

180

2

2.5

160

120

60

20

| VO | – RMS Output Voltage – V

I O||

Maximum Output

Current Limit Line

TLV2470, TLV2471†

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

Safe Operating Area

VDD = 

±

 5 V

TJ  = 150

°

C

TA = 125

°

C

Packages With

θ

JA 

 210

°

C/W

at TA = 70

°

C

A

B

C

G

Figure 51

100

80

40

0

0

0.25

0.5

0.75

– Maximum RMS Output Current – mA

140

180

1

1.25

160

120

60

20

| VO | – RMS Output Voltage – V

I O||

Maximum Output

Current Limit Line

TLV2472, TLV2473†

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

1.5

C

Safe Operating Area

VDD = 

±

 3 V

TJ  = 150

°

C

TA = 125

°

C

Packages With

θ

JA 

 55

°

C/W

at TA = 125

°

C

or

θ

JA 

 178

°

C/W

at TA = 70

°

C

D

G

H

Figure 52

100

80

40

0

0

0.5

1

1.5

– Maximum RMS Output Current – mA

140

180

2

2.5

160

120

60

20

| VO | – RMS Output Voltage – V

I O||

Maximum Output

Current Limit Line

TLV2472, TLV2473†

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

Safe Operating Area

VDD = 

±

 5 V

TJ  = 150

°

C

TA = 125

°

C

Packages With

θ

JA 

 105

°

C/W

at TA = 70

°

C

H

D

C

G

F

† A – SOT23(5); B – SOT23 (6); C – SOIC (8); D – SOIC (14); E – SOIC (16); F – MSOP PP (8); G – PDIP (8); H – PDIP (14); I – PDIP (16);

J – TSSOP PP (14/16)

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

22

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

general PowerPAD design considerations (continued)

Figure 53

100

80

40

0

0

0.25

0.5

0.75

– Maximum RMS Output Current – mA

140

180

1

1.25

160

120

60

20

| VO | – RMS Output Voltage – V

I O||

Maximum Output

Current Limit Line

TLV2474, TLV2475†

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

1.5

E

Safe Operating Area

VDD = 

±

3 V

TJ  = 150

°

C

TA = 125

°

C

Packages With

θ

JA 

 88

°

C/W

at TA = 70

°

C

D

H and I

J

Figure 54

100

80

40

0

0

0.5

1

1.5

– Maximum RMS Output Current – mA

140

180

2

2.5

160

120

60

20

| VO | – RMS Output Voltage – V

I O||

Maximum Output

Current Limit Line

TLV2474, TLV2475†

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

Safe Operating Area

VDD = 

±

 5 V

TJ  = 150

°

C

TA = 125

°

C

Packages With

θ

JA 

 52

°

C/W

at TA = 70

°

C

J

D

E

H and I

† A – SOT23(5); B – SOT23 (6); C – SOIC (8); D – SOIC (14); E – SOIC (16); F – MSOP PP (8); G – PDIP (8); H – PDIP (14); I – PDIP (16); J

– TSSOP PP (14/16)

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

23

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using Microsim

Parts

, the model generation software used

with Microsim

 PSpice

. The Boyle macromodel (see Note 2) and subcircuit in Figure 55 are generated using

the TLV247x typical electrical and operating characteristics at T

A

 = 25

°

C. Using this information, output

simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

D

Maximum positive output voltage swing

D

Maximum negative output voltage swing

D

Slew rate

D

Quiescent power dissipation

D

Input bias current

D

Open-loop voltage amplification

D

Unity-gain frequency

D

Common-mode rejection ratio

D

Phase margin

D

DC output resistance

D

AC output resistance

D

Short-circuit output current limit

NOTE  1: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” 

IEEE Journal

of Solid-State Circuits, SC-9, 353 (1974).

* TLV247x operational amplifier ”macromodel” subcircuit

* created using Parts release 8.0 on 4/27/99 at 14:31

* Parts is a MicroSim product.

*

* connections:   non–inverting input

*

           | inverting input

*

           |  |  positive power supply

*

           |  |  |  negative power supply

*

           |  |  |  |  output

*

           |  |  |  |  |

.subckt  TLV247x 1 2 3 4 5

*

c1   

11 

12 

1.1094E–12

c2    

6  

5.5000E–12

css 

 

10 99 556.53E–15

dc    

53 

dy

de   

54  

dy

dlp 

 

90 91 dx

dln 

 

92 90 dx

dp    

4  

dx

  

egnd 

99  

poly(2) (3,0) (4,0) 0 .5 .5

  

fb

99 

poly(5) vb vc ve vlp vln 0 

+ 39.614E6 –1E3 1E3 40E6 –40E6

  

ga    

6  

11 

12   79.828E–6

  

gcm   

0  

10 

99   32.483E–9

  

iss  

10  

dc 

10.714E–6

  

hlim 

90  

vlim 1K

  

ioff

0

6

dc

75E–9

  

j1   

11  

10 jx1

  

j2   

12  

10 jx2

  

r2    

6  

100.00E3

  

rd1   

11 

12.527E3

  

rd2   

12 

12.527E3

  

ro1   

8  

10

  

ro2   

99 

10

  

rp    

3  

3.8023E3

rss

10

99

18.667E6

  

vb    

9  

dc 0

  

vc    

53 

dc .842

  

ve   

54  

dc .842

  

vlim  

7  

dc 0

  

vlp  

91  

dc 110

  

vln   

92 

dc 110

.model dx  D(Is=800.00E–18)

.model 

dy 

D(Is=800.00E–18 Rs=1m Cjo=10p)

.model 

jx1 

NJF(Is=1.0825E–12 Beta=594.78E–06 + Vto=–1)

.model 

jx2 

NJF(Is=1.0825E–12 Beta=594.78E–06 + Vto=–1)

.ends

*$

IN–

G

D

S

D

S

G

rp

IN+

rd1

rd2

rss

egnd

fb

ro2

ro1

vlim

OUT

ga

ioff

gcm

vb

c1

dc

iss

dp

GND

VDD

css

c2

ve

de

dlp

dln

vln

hlim

vlp

10

4

1

11

12

3

53

54

9

6

8

5

7

91

90

92

vc

99

+

+

+

+

+

+

+

+

r2

2

Figure 55. Boyle Macromodel and Subcircuit

PSpice and Parts are trademarks of MicroSim Corporation.

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

24

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**)    

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047 / D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A  MIN

A  MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0

°

– 8

°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

25

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

DBV (R-PDSO-G5)   

PLASTIC SMALL-OUTLINE PACKAGE

0,25

0,35

0,55

Gage Plane

0,15 NOM

4073253-4/B 10/97

2,50

3,00

0,40

0,20

1,50

1,80

4

5

3

3,10

1

2,70

1,00

1,30

0,05 MIN

Seating Plane

0,10

0,95

M

0,25

0

°

– 8

°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions include mold flash or protrusion.

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

26

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

DBV (R-PDSO-G6)    

PLASTIC SMALL-OUTLINE PACKAGE

0,25

Gage Plane

0,15 NOM

4073253-5/B 10/97

2,50

3,00

0,40

0,20

1,50

1,80

4

6

3

3,10

1

2,70

1,30

1,00

0,05 MIN

Seating Plane

0,95

M

0,25

0

°

– 8

°

0,10

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions include mold flash or protrusion.

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

27

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

DGN (S-PDSO-G8)    

PowerPAD

 PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

Thermal Pad

(See Note D)

0,15 NOM

Gage Plane

4073271/A 04/98

4,98

0,25

5

3,05

4,78

2,95

8

4

3,05

2,95

1

0,38

0,15

0,05

1,07 MAX

Seating Plane

0,10

0,65

M

0,25

0

°

– 6

°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions include mold flash or protrusions.

D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. 

This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal

pad is 68 mils (height as illustrated) 

×

 70 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package.

E. Falls within JEDEC MO-187

PowerPAD is a trademark of Texas Instruments Incorporated.

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

28

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

DGQ (S-PDSO-G10)    

PowerPAD

 PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

Thermal Pad

(See Note D)

0,15 NOM

Gage Plane

4073273/A 04/98

4,98

0,17

6

3,05

4,78

2,95

10

5

3,05

2,95

1

0,27

0,15

0,05

1,07 MAX

Seating Plane

0,10

0,50

M

0,25

0

°

– 6

°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. 

This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal

pad is 68 mils (height as illustrated) 

×

 70 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package.

PowerPAD is a trademark of Texas Instruments Incorporated.

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

29

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

N (R-PDIP-T**)   

PLASTIC DUAL-IN-LINE PACKAGE

20

0.975

(24,77)

0.940

(23,88)

18

0.920

0.850

14

0.775

0.745

(19,69)

(18,92)

16

0.775

(19,69)

(18,92)

0.745

A  MIN

DIM

A  MAX

PINS **

0.310 (7,87)

0.290 (7,37)

(23.37)

(21.59)

Seating Plane

0.010 (0,25) NOM

14/18 PIN ONLY

4040049/C 08/95

9

8

0.070 (1,78) MAX

A

0.035 (0,89) MAX

0.020 (0,51) MIN

16

1

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

M

0.010 (0,25)

0.100 (2,54)

0

°

– 15

°

16 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

30

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

P (R-PDIP-T8)  

PLASTIC DUAL-IN-LINE PACKAGE

4040082 / B 03/95

0.310 (7,87)

0.290 (7,37)

0.010 (0,25) NOM

0.400 (10,60)

0.355 (9,02)

5

8

4

1

0.020 (0,51) MIN

0.070 (1,78) MAX

0.240 (6,10)

0.260 (6,60)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.015 (0,38)

0.021 (0,53)

Seating Plane

M

0.010 (0,25)

0.100 (2,54)

0

°

– 15

°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

background image

TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

FAMILY OF 600-

µ

A/Ch 2.8-MHz RAIL-TO-RAIL INPUT/OUTPUT

HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

 

SLOS232B – JUNE 1999 – REVISED MARCH 2000

31

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

PWP (R-PDSO-G**)

PowerPAD

 PLASTIC SMALL-OUTLINE

4073225/F 10/98

0,50

0,75

0,25

0,15 NOM

Thermal Pad

(See Note D)

Gage Plane

28

24

7,70

7,90

20

6,40

6,60

9,60

9,80

6,60

6,20

11

0,19

4,50

4,30

10

0,15

20

A

1

0,30

1,20 MAX

16

14

5,10

4,90

PINS **

4,90

5,10

DIM

A  MIN

A  MAX

0,05

Seating Plane

0,65

0,10

M

0,10

0

°

– 8

°

20 PINS SHOWN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusions.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal

pad is 78 mils (height as illustrated) 

×

 94 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package.

E. Falls within JEDEC MO-153

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 2000, Texas Instruments Incorporated