background image

Rev:  1.01c  11/2002

1/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

GS841Z18/36AT-180/166/150/100

4Mb Pipelined and Flow Through 

Synchronous NBT SRAMs

180 MHz–100 MHz

3.3 V V

DD

2.5 V and 3.3 V V

DDQ

100-Pin TQFP

Commercial Temp

Industrial Temp

Preliminary

Features

• 256K x 18 and 128K x 36 configurations

• User-configurable Pipelined and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Fully pin-compatible with both pipelined and flow through 

NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered, address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP  package

  

Functional Description

The GS841Z18/36AT is an 4Mbit Synchronous Static SRAM. 

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other 

pipelined read/double late write or flow through read/single 

late write SRAMs, allow utilization of all available bus 

bandwidth by eliminating the need to insert deselect cycles 

when the device is switched from read to write cycles. 

Because it is a synchronous device, address, data inputs, and 

read/ write control inputs are captured on the rising edge of the 

input clock. Burst order control (LBO) must be tied to a power 

rail for proper operation. Asynchronous inputs include the 

Sleep mode enable (ZZ) and Output Enable. Output Enable can 

be used to override the synchronous control of the output 

drivers and turn the RAM's output drivers off at any time. 

Write cycles are internally self-timed and initiated by the rising 

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs 

and simplifies input signal timing. 

The GS841Z18/36AT  may be configured by the user to 

operate in Pipeline or Flow Through mode. Operating as a 

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device 

incorporates a rising-edge-triggered output register. For read 

cycles, pipelined SRAM output data is temporarily stored by 

the edge-triggered output register during the access cycle and 

then released to the output drivers at the next rising edge of 

clock. 

The GS841Z18/36AT is implemented with GSI's high 

performance CMOS technology and is available in a JEDEC-

Standard 100-pin TQFP package. 

–180

–166

–150

–100

Pipeline

3-1-1-1

tCycle

t

KQ

I

DD

5.5 ns

3.2 ns

335 mA

6.0 ns

3.5 ns

310 mA

6.6 ns

3.8 ns

280 mA

10 ns

4.5 ns

190 mA

Flow 

Through

2-1-1-1

t

KQ

tCycle

I

DD

8 ns

9.1 ns

210 mA

8.5 ns

10 ns

190 mA

10 ns

12 ns

165 mA

12 ns

15 ns

135 mA

A

B

C

D

E

F

R

W

R

W

R

W

Q

A

D

B

Q

C

D

D

Q

E

Q

A

D

B

Q

C

D

D

Q

E

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

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Rev:  1.01c  11/2002

2/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

GS841Z18AT Pinout

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

DDQ

V

SS

    

DQ

B1

DQ

B2

V

SS

   

V

DDQ

    

DQ

B3

DQ

B4

FT

V

DD

    

NC

V

SS

   

DQ

B5

DQ

B6

V

DDQ

    

V

SS

   

DQ

B7

DQ

B8

DQ

B9

V

SS

   

V

DDQ

    

V

DDQ

V

SS

DQ

A8

DQ

A7

V

SS

V

DDQ

DQ

A6

DQ

A5

V

SS

NC

V

DD

ZZ

DQ

A4

DQ

A3

V

DDQ

V

SS

DQ

A2

DQ

A1

V

SS

V

DDQ

LB

O

A

5

A

4

A

3

A

2

A

1

A

0

TMS

TD

I

V

SS

V

DD

TDO

TCK

 A

10

 A

11

 A

12

 A

13

 A

14

 A

16

A

6

A

7

E

1

E

2

 

NC

NC

B

B

B

A

E

3

CK

W

CKE

V

DD

V

SS

G

ADV

NC

NC

A

8

A

9

 A

15

256K x 18

Top View

DQ

A9

A

17

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Rev:  1.01c  11/2002

3/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

GS841Z36AT Pinout

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

DDQ

V

SS

    

DQ

C4

DQ

C3

V

SS

   

V

DDQ

     

DQ

C2

DQ

C1

FT

V

DD

    

NC

V

SS

    

DQ

D1

DQ

D2

V

DDQ

     

V

SS

   

DQ

D3

DQ

D4

DQ

D5

V

SS

   

V

DDQ

     

V

DDQ

V

SS

DQ

B4

DQ

B3

V

SS

V

DDQ

DQ

B2

DQ

B1

V

SS

NC

V

DD

ZZ

DQ

A1

DQ

A2

V

DDQ

V

SS

DQ

A3

DQ

A4

V

SS

V

DDQ

LB

O

A

5

A

4

A

3

A

2

A

1

A

0

TMS

TDI

V

SS

V

DD

TD

O

TCK

 A

10

 A

11

 A

12

 A

13

 A

14

 A

16

A

6

A

7

E

1

E

2

 

B

D

B

C

B

B

B

A

E

3

CK

W

CKE

V

DD

V

SS

G

ADV

NC

NC

A

8

A

9

 A

15

128K x 36

Top View

DQ

B5

DQ

B9

DQ

B7

DQ

B8

DQ

B6

DQ

A6

DQ

A5

DQ

A8

DQ

A7

DQ

A9

DQ

C7

DQ

C8

DQ

C6

DQ

D6

DQ

D8

DQ

D7

DQ

D9

DQ

C5

DQ

C9

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

background image

Rev:  1.01c  11/2002

4/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

100-Pin TQFP Pin Descriptions 

Symbol

Type

Description

A

0

, A

1

In

Burst Address Inputs—Preload the burst counter

A

2

–A

16

In

Address Inputs

A

17

In

Address Input

CK

In

Clock Input Signal

B

A

In

Byte Write signal for data inputs DQ

A1

–DQ

A9

; active low

B

B

In

Byte Write signal for data inputs DQ

B1

–DQ

B9

; active low

B

C

In

Byte Write signal for data inputs DQ

C1

–DQ

C9

; active low

B

D

In

Byte Write signal for data inputs DQ

D1

–DQ

D9

; active low

W

In

Write Enable; active low

E

1

In

Chip Enable; active low

E

2

In

Chip Enable; active high; for self decoded depth expansion

E

3

In

Chip Enable; active low; for self decoded depth expansion

G

In

Output Enable; active low

ADV

In

Advance / Load—Burst address counter control pin

CKE

In

Clock Input Buffer Enable; active low

NC

No Connect

DQ

A1

–DQ

A9

I/O

Byte A Data Input and Output pins

 DQ

B1

–DQ

B9

I/O

Byte B Data Input and Output pins

 DQ

C1

–DQ

C9

I/O

Byte C Data Input and Output pins

DQ

D1

–DQ

D9

I/O

Byte D Data Input and Output pins

ZZ

In

Power down control; active high

FT

In

Pipeline/Flow Through Mode Control; active low 

LBO

In

Linear Burst Order; active low

TMS

Scan Test Mode Select

TDI

Scan Test Data In

TDO

Scan Test Data Out

TCK

Scan Test Clock

V

DD

In

3.3 V power supply

V

SS

In

Ground

V

DDQ

In

3.3 V output power supply for noise reduction

NC

No Connect

background image

Rev:  1.01c  11/2002

5/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to 

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. 

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle 

read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device 

activation is accomplished by asserting all three of the Chip Enable inputs (E

1

, E

2,

 and E

3

). Deassertion of any one of the Enable 

inputs will deactivate the device. 

   

  

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three 

chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address 

presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control 

logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At 

the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock. 

The Byte Write Enable inputs (B

A

, B

B

, B

C,

 and B

D

) determine which bytes will be written. All or none may be activated. A Write 

Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, 

matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At 

the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is 

required at the third rising edge of clock. 

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the 

use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after 

new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow 

Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter, preserving the ability 

to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late 

write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address 

and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of 

clock.

Function

W

B

A

B

B

B

C

B

D

Read

H

X

X

X

X

Write Byte “a”

L

L

H

H

H

Write Byte “b”

L

H

L

H

H

Write Byte “c”

L

H

H

L

H

Write Byte “d”

L

H

H

H

L

Write all Bytes

L

L

L

L

L

Write Abort/NOP

L

H

H

H

H

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6/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

Synchronous Truth Table

Operation

Type Address E

1

E

2

E

3

ZZ ADV W Bx G CKE CK

DQ

Notes

Deselect Cycle, Power Down

D

None

H

X

X

L

L

X

X

X

L

L-H High-Z

Deselect Cycle, Power Down

D

None

X

X

H

L

L

X

X

X

L

L-H High-Z

Deselect Cycle, Power Down

D

None

X

L

X

L

L

X

X

X

L

L-H High-Z

Deselect Cycle, Continue

D

None

X

X

X

L

H

X

X

X

L

L-H High-Z

1

Read Cycle, Begin Burst

R

External

L

H

L

L

L

H

X

L

L

L-H

Q

Read Cycle, Continue Burst

B

Next

X

X

X

L

H

X

X

L

L

L-H

Q

1,10

NOP/Read, Begin Burst

R

External

L

H

L

L

L

H

X

H

L

L-H High-Z

2

Dummy Read, Continue Burst

B

Next

X

X

X

L

H

X

X

H

L

L-H High-Z

1,2,10

Write Cycle, Begin Burst

W

External

L

H

L

L

L

L

L

X

L

L-H

D

3

Write Cycle, Continue Burst

B

Next

X

X

X

L

H

X

L

X

L

L-H

D

1,3,10

NOP/Write Abort, Begin Burst

W

None

L

H

L

L

L

L

H

X

L

L-H High-Z

2,3

Write Abort, Continue Burst

B

Next

X

X

X

L

H

X

H

X

L

L-H High-Z 1,2,3,10

Clock Edge Ignore, Stall

Current

X

X

X

L

X

X

X

X

H

L-H

-

4

Sleep Mode

None

X

X

X

H

X

X

X

X

X

X

High-Z

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect 

cycle is executed first

2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is 

sampled low but no Byte Write pins are active, so no Write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write 

cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus 

will remain in High Z. 

5.  X  = Don’t Care;  H = Logic High; L = Logic Low;  Bx = High = All Byte Write signals are high;  Bx = Low = One or more Byte/Write signals 

are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

background image

Rev:  1.01c  11/2002

7/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

    

Deselect

New Read

New Write

Burst Read

Burst Write

W

R

B

R

B

W

D

D

B

B

W

R

D

B

W

R

D

D

Pipeline and Flow Through Read-Write Control State Diagram

Current State (n)

Next State (n+1)

Transition

ƒ

Input Command Code

Key

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B and D represent input command

codes, as indicated in the Synchronous Truth Table.

Clock (CK)

Command

Current State

Next State

ƒ

n

n+1

n+2

n+3

ƒ

ƒ

ƒ

Current State and Next State Definition for 

Pipelined and Flow Through Read/Write Control State Diagram

W

R

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GS841Z18/36AT-180/166/150/100

Preliminary

     

Intermediate

Intermediate

Intermediate

Intermediate

Intermediate

Intermediate

High Z

(Data In)

Data Out

(Q Valid)

High Z

B W

B

R

B

D

R

W

R

W

D

D

Pipeline Mode Data I/O State Diagram

Current State (n)

Next State (n+2)

Transition

ƒ

Input Command Code

Key

Transition

Intermediate State (N+1)

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Clock (CK)

Command

Current State

Intermediate

ƒ

n

n+1

n+2

n+3

ƒ

ƒ

ƒ

Current State and Next State Definition for 

Pipeline Mode Data I/O State Diagram

Next State

State

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

     

High Z

(Data In)

Data Out

(Q Valid)

High Z

B W

B

R

B

D

R

W

R

W

D

D

Current State (n)

Next State (n+1)

Transition

ƒ

Input Command Code

Key

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Flow Through Mode Data I/O State Diagram

Clock (CK)

Command

Current State

Next State

ƒ

n

n+1

n+2

n+3

ƒ

ƒ

ƒ

Current State and Next State Definition for: 

Pipeline and Flow Through Read Write Control State Diagram

background image

Rev:  1.01c  11/2002

10/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from 

read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address 

generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when 

driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write 

the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into 

Load mode. 

 

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been 

accessed.   The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst 

sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables 

below for details.

 

Note:

There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will 

operate in the default states as specified in the above table.

Burst Counter Sequences

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, 

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to 

low, the SRAM operates normally after 2 cycles of wake up time. 

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

SB

2. The duration of 

Mode Pin Functions

Mode Name

Pin Name

State

Function

Burst Order Control

LBO

L

Linear Burst

H or NC

Interleaved Burst

Output Register Control

FT

L

Flow Through

H or NC

Pipeline

Power Down Control

ZZ

L or NC

Active

Standby, I

DD

 = I

SB

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

I

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0]

A[1:0]

A[1:0]

A[1:0]

1st address

00

01

10

11

2nd address

01

10

11

00

3rd address

10

11

00

01

4th address

11

00

01

10

A[1:0]

A[1:0]

A[1:0]

A[1:0]

1st address

00

01

10

11

2nd address

01

00

11

10

3rd address

10

11

00

01

4th address

11

10

01

00

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Rev:  1.01c  11/2002

11/30

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become 

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. 

When the ZZ pin is driven high, I

SB

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending 

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated 

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands 

may be applied while the SRAM is recovering from Sleep mode.

 Sleep Mode Timing Diagram

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found 

on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V

DD

 or V

DDQ

 on pipelined parts and V

SS

 on flow 

through parts. GSI NBT SRAMs are fully compatible with these sockets. 

Pin 66, a No Connect (NC) on GSI’s GS880Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT 

SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked  V

DD

 or V

DDQ

 on 

pipelined parts and V

SS

 on flow through parts.  Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature 

may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or 

tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up 

resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs 

(GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open 

drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs. 

CK

ZZ

tZZR

tZZH

tZZS

~ ~

~ ~

Sleep

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

  

Note: 

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended 

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended 

period of time, may affect reliability of this component.  

   

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V 

 V

DDQ

 

 2.375 V 

(i.e., 2.5 V I/O) and 3.6 V 

 V

DDQ

 

 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges.  The part number of 

Industrial Temperature Range versions end the character “I”.  Unless otherwise noted, all performance specifications quoted are evaluated 

for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < V

DD 

+2 V with a pulse width not to exceed 20% tKC.

Absolute Maximum Ratings

(All voltages reference to V

SS

)

Symbol

Description

Value

Unit

V

DD

Voltage on V

DD

 Pins

–0.5 to 4.6

V

V

DDQ

Voltage in V

DDQ

 Pins

–0.5 to V

DD

V

V

CK

Voltage on Clock Input Pin

–0.5 to 6

V

V

I/O

Voltage on I/O Pins

–0.5 to V

DDQ 

+0.5  (

 4.6 V max.)

V

V

IN

Voltage on Other Input Pins

–0.5 to V

DD 

+0.5  (

 4.6 V max.)

V

I

IN

Input Current on Any Pin

+/–20

mA

I

OUT

Output Current on Any I/O Pin

+/–20

mA

P

D

Package Power Dissipation 

1.5

W

T

STG

Storage Temperature

–55 to 125

o

C

T

BIAS

Temperature Under Bias

–55 to 125

o

C

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Supply Voltage

V

DD

3.135

3.3

3.6

V

I/O Supply Voltage

V

DDQ

2.375

2.5

V

DD

V

1

Input High Voltage

V

IH

1.7

V

DD 

+0.3

V

2

Input Low Voltage

V

IL

–0.3

0.8

V

2

Ambient Temperature (Commercial Range Versions)

T

A

0

25

70

°

C

3

Ambient Temperature (Industrial Range Versions)

T

A

–40

25

85

°

C

3

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Rev:  1.01c  11/2002

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

     

  

Note: These parameters are sample tested.

 

Notes: 

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. 

Temperature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Capacitance 

(T

= 25

o

C, f = 1 MH

Z

, V

DD 

= 3.3 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance

C

IN

V

IN 

= 0 V

4

5

pF

Input/Output Capacitance

C

I/O

V

OUT 

= 0 V

6

7

pF

Package Thermal Characteristics

Rating

Layer Board

Symbol

Max

Unit

Notes

Junction to Ambient (at 200 lfm)

single 

R

Θ

JA

40

°

C/W

1,2

Junction to Ambient (at 200 lfm)

four 

R

Θ

JA

24

°

C/W

1,2

Junction to Case (TOP)

R

Θ

JC

9

°

C/W

3

20% tKC

V

SS

 – 2.0 V

50%

V

SS

V

IH

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

V

DD

 + 2.0 V

50%

V

DD

V

IL

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Rev:  1.01c  11/2002

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

 

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for t

LZ

, t

HZ

, t

OLZ

 and t

OHZ

4. Device is deselected as defined by the Truth Table. 

   

AC Test Conditions

Parameter

Conditions

Input high level

 2.3 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

1.25 V

Output reference level

1.25 V

Output load 

Fig. 1& 2

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

IL

V

IN 

= 0 to V

DD

–1 uA

1 uA

ZZ Input Current

I

INZZ

V

DD 

 

V

IN 

 

V

IH

0 V

 

≤ 

V

IN 

≤ 

V

IH

–1 uA

–1 uA

1 uA

300 uA

Mode Pin Input Current

I

INM

V

DD 

 

V

IN 

 

V

IL

0 V

 

≤ 

V

IN 

≤ 

V

IL

–300 uA

–1 uA

1 uA

1 uA

Output Leakage Current

I

OL

Output Disable,

V

OUT

 = 0 to V

DD

–1 uA

1 uA

Output High Voltage

V

OH

I

OH 

= – mA, V

DDQ 

= 2.375 V

1.7 V

Output High Voltage

V

OH

I

OH 

= – mA, V

DDQ 

= 3.135 V

2.4 V

Output Low Voltage

V

OL

I

OL 

= 8 mA

0.4 V

DQ

VT = 1.25 V

50

30pF

*

DQ

2.5 V

Output Load 1

Output Load 2

225

225

5pF

*

* Distributed Test Jig Capacitance

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

Operating Currents

Parameter Test Conditions Symbol

-

180

-

166

-

150

-

100

Unit

0 to 

70°C

–40 to 

85°C

0 to 

70°C

–40 to 

85°C

0 to 

70°C

–40 to 

85°C

0 to 

70°C

–40 to 

85°C

Operating

Current

Device Selected; 

All other inputs 

V

IH

 or 

≤ 

V

IL

Output open

I

DD

Pipeline

335

345

310

320

280

290

190

200

mA

I

DD

Flow-Thru

210

220

190

200

165

175

135

145

mA

Standby

Current

ZZ 

≥ 

V

DD

 

0.2 V

I

SB

Pipeline

20

30

20

30

20

30

20

30

mA

I

SB

Flow-Thru

20

30

20

30

20

30

20

30

mA

Deselect

Current

Device Deselected; 

All other inputs 

≥ 

V

IH

 or 

 V

IL

I

DD

Pipeline

55

65

50

60

50

60

40

50

mA

I

DD

Flow-Thru

40

50

40

50

35

45

35

45

mA

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Rev:  1.01c  11/2002

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

 

AC Electrical Characteristics

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold 

times as specified above.

Parameter

Symbol

-180

-166

-150

-100

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Pipeline

Clock Cycle Time

tKC

5.5

6.0

6.7

10

ns

Clock to Output Valid

tKQ

3.2

3.5

3.8

4.5

ns

Clock to Output Invalid

tKQX

1.5

1.5

1.5

1.5

ns

Clock to Output in Low-Z

tLZ

1

1.5

1.5

1.5

1.5

ns

Flow

Through

Clock Cycle Time

tKC

9.1

10.0

12.0

15.0

ns

Clock to Output Valid

tKQ

8.0

8.5

10.0

12.0

ns

Clock to Output Invalid

tKQX

3.0

3.0

3.0

3.0

ns

Clock to Output in Low-Z

tLZ

1

3.0

3.0

3.0

3.0

ns

Clock HIGH Time

tKH

1.3

1.3

1.3

1.3

ns

Clock LOW Time

tKL

1.5

1.5

1.5

1.5

ns

Clock to Output in High-Z

tHZ

1

1.5 3.2

1.5

3.5

1.5 3.8

1.5

5

ns

G to Output Valid

tOE

3.2

3.5

3.8

5

ns

G to output in Low-Z

tOLZ

1

0

0

0

0

ns

G to output in High-Z

tOHZ

1

3.2

3.5

3.8

5

ns

Setup time

tS

1.5

1.5

1.5

2.0

ns

Hold time

tH

0.5

0.5

0.5

0.5

ns

ZZ setup time

tZZS

2

5

5

5

5

ns

ZZ hold time

tZZH

2

1

1

1

1

ns

ZZ recovery

tZZR

20

20

20

20

ns

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Rev:  1.01c  11/2002

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

Pipeline Mode Read/Write Cycle Timing  

*Note: E = High (False) if E

1

 = 1 or E

2

 = 0 or E

3

 = 1

tH

tS

tH

CK

CKE

E*

ADV

tKH

W

tKL

tKC

tS

Bn

A

0

–An

A1

tH

tS

A2

A3

D(A1)

D(A2)

Q(A3)

Q

Q(A6)

tH

tS

D

D(A5)

tKQLZ

tKQ

tKQHZ

tOEHZ

tOELZ

tKQX

tKHQZ

tGLQV

G

1

2

3

4

5

6

7

8

9

10

COMMAND

Write

D(A1)

Write

D(A2)

BURST

Write

D(A2+1)

Read

Q(A3)

Read

Q(A4)

BURST

Read

Q(A4+1)

Write

D(A5)

Read

Q(A6)

Write

D(A7)

DESELECT

DON’T CARE

UNDEFINED

DQ

A

–DQ

D

tH

tS

tH

tS

tH

tS

A4

A5

A6

A7

Q(A4)

(A4+1)

(A2+1)

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Rev:  1.01c  11/2002

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

Pipeline Mode No-Op, Stall and Deselect Timing

*Note: E = High (False) if E

1

 = 1 or E

2

 = 0 or E

3

 = 1

CK

CKE

E

*

ADV

W

Bn

A

0

An

A1

A5

D(A1)

Q(A2)

Q(A3)

Q(A5)

DQ

1

2

3

4

5

6

7

8

9

10

COMMAND

Write

D(A1)

Read

Q(A2)

STALL

Read

Q(A3)

Write

D(A4)

STALL

NOP

Read

Q(A5)

CONTINUE

DON’T CARE

UNDEFINED

D(A4)

tKHQZ

tKQHZ

DESELECT

DESELECT

tH

tS

A2

A3

A4

tH

tS

tH

tS

tH

tS

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© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

Flow Through Mode Read/Write Cycle Timing

*Note: E = High (False) if E

1

 = 1 or E

2

 = 0 or E

3

 = 1

CK

CKE

E*

ADV

tKH

W

tKL

tKC

Bn

A

0

–An

tH

tS

A7

DQ

1

2

3

4

5

6

7

8

9

10

COMMAND

Write

D(A1)

Write

D(A2)

BURST

Write

D(A2+1)

Read

Q(A3)

Read

Q(A4)

BURST

Read

Q(A4+1)

Write

D(A5)

Read

Q(A6)

Write

D(A7)

DESELECT

DON’T CARE

UNDEFINED

tH

tS

tH

tS

tH

tS

tH

tS

tH

tS

A1

A2

A3

A4

A5

A6

D(A1)

D(A2)

Q(A3)

Q

Q(A6)

tH

tS

D

D(A5)

tKQLZ

tKQ

tKQHZ

tOEHZ

tOELZ

tKQX

tKHQZ

tGLQV

Q(A4)

(A4+1)

(A2+1)

G

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© 2001, Giga Semiconductor, Inc.

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GS841Z18/36AT-180/166/150/100

Preliminary

Flow Through Mode No-Op, Stall and Deselect Timing

*Note: E = High (False) if E

1

 = 1 or E

2

 = 0 or E

3

 = 1

CK

CKE

E

*

ADV

W

Bn

A

0

An

Q(A5)

DQ

1

2

3

4

5

6

7

8

9

10

COMMAND

Write

D(A1)

Read

Q(A2)

STALL

Read

Q(A3)

Write

D(A4)

STALL

NOP

Read

Q(A5)

CONTINUE

DON’T CARE

UNDEFINED

D(A4)

tKHQZ

tKQHZ

DESELECT

DESELECT

D(A1)

Q(A2)

Q(A3)

A1

A5

A2

A3

A4

tH

tS

tH

tS

tH

tS

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GS841Z18/36AT-180/166/150/100

Preliminary

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface 

standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some 

functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP 

(Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of  

Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless 

clocked.  TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG 

Port unused, TCK, TDI, and TMS may be left floating or tied to either V

DD

 or V

SS

. TDO should be left unconnected. 

JTAG Port Registers

Overview

The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS 

as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and 

push serial data out on the next  falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or 

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the 

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the 

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through 

the RAMs  JTAG Port  to another device in the scan chain with as little delay as possible.

JTAG Pin Descriptions

Pin

Pin Name

I/O

Description

TCK

Test Clock

In

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the 

falling edge of TCK.

TMS Test Mode Select

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state 

machine. An undriven TMS input will produce the same result as a logic one input level.

TDI

Test Data In

In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed 

between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP 

Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to 

the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input 

level.

TDO

Test Data Out

Out

Output that is active depending on the state of the TAP state machine. Output changes in response to the 

falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is 

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. 

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GS841Z18/36AT-180/166/150/100

Preliminary

Boundary Scan Register

Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The 

flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin.  The Boundary 

Scan Register also  includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins 

and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the 

control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then 

is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP instructions can be used to 

activate the Boundary Scan Register. 

 JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in 

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. 

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the 

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

 

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific 

ID Register Contents

Die

Revision

Code

Not Used

I/O 

Configuration

GSI Technology

JEDEC Vendor 

ID Code

Presence Register

Bit  # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0

x36

X X X X 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1 0 0 0 1 1 0 1 1 0 0 1

1

x18

X X X X 0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1 0 0 0 1 1 0 1 1 0 0 1

1

Instruction Register

ID Code Register

Boundary Scan  Register

0

1

2

0

1

2

·

· · ·

31 30 29

0

1

2

· · ·

· · ·

· · ·

n

0

Bypass Register

TDI

TDO

TMS

TCK

Test Access Port (TAP) Controller

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GS841Z18/36AT-180/166/150/100

Preliminary

(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be 

implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1-

compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor 

all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This 

device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. 

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired 

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the 

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this 

device is listed in the following table.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when 

the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices 

in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc-

tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan 

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

0

0

1

0

1

1

0

0

1

1

1

0

0

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

1

1

1

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GS841Z18/36AT-180/166/150/100

Preliminary

Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-

tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm 

the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap-

ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O 

ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the 

TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-

DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This 

functionality is not Standard 1149.1-compliant.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in 

the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Neverthe-

less, this RAM’s TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction regis-

ter the RAM responds just as it does in response to the BYPASS instruction described above.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID 

register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any 

time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-

ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

 

JTAG TAP Instruction Set Summary

Instruction

Code

Description

Notes

EXTEST

000

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *

1

IDCODE

001

Preloads ID Register and places it between TDI and TDO.

1, 2

SAMPLE-Z

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 

Forces all RAM output drivers to High-Z.

1

RFU

011

Do not use this instruction;  Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

SAMPLE/

PRELOAD

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 

This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *

1

GSI

101

GSI private instruction.

1

RFU

110

Do not use this instruction;  Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

BYPASS

111

Places Bypass Register between TDI and TDO.

1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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GS841Z18/36AT-180/166/150/100

Preliminary

  

 

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol Min.

Max.

Unit Notes

Test Port Input High Voltage

V

IHT

1.7

V

DD 

+0.3

V

1,  2

Test Port Input Low Voltage

V

ILT

–0.3

0.8

V

1, 2

 TMS, TCK and TDI Input Leakage Current

I

INTH

–300

1

uA

3

 TMS, TCK and TDI Input Leakage Current

I

INTL

–1

1

uA

4

TDO Output Leakage Current

I

OLT

–1

1

uA

5

Test Port Output High Voltage

V

OHT

2.4

V

6, 7

Test Port Output Low Voltage

V

OLT

0.4

V

6, 8

Notes:

1. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

2. Input Under/overshoot voltage must be –2 V > Vi < V

DD 

+2 V with a pulse width not to exceed 20% 

tTKC.

3. V

DD 

 

V

IN 

 

V

IL

4. 0 V

 

≤ 

V

IN 

≤ 

V

IL

5. Output Disable, V

OUT

 = 0 to V

DD

6. The TDO output driver is served by the V

DD

 supply.

7. I

OH 

= –4 mA

8. I

OL 

= +4 mA

 

Notes:

1. Include scope and jig capacitance.

JTAG Port AC Test Conditions

Parameter

Conditions

Input high level

 2.3 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

1.25 V

Output reference level

1.25 V

DQ

V

= 1.25 V

50

30pF

*

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS841Z18/36AT-180/166/150/100

Preliminary

JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

TCK Cycle Time

tTKC

20

ns

TCK Low to TDO Valid

tTKQ

10

ns

TCK High Pulse Width

tTKH

10

ns

TCK Low Pulse Width

tTKL

10

ns

TDI & TMS Set Up Time

tTS

5

ns

TDI & TMS Hold Time

tTH

5

ns

tTKQ

tTS

tTH

tTKH

tTKL

TCK

TMS

TDI

TDO

tTKC

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GS841Z18/36AT-180/166/150/100

Preliminary

Output Driver Characteristics

BPR 1999.05.18

-140.0

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

80.0

100.0

120.0

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

V Out (Pull Down)

VDDQ - V Out (Pull Up)

I Out (mA)

3.6V PD HD

3.3V PD HD

3.1V PD HD

3.1V PU HD

3.3V PU HD

3.6V PU HD

Pull Up Drivers

Pull Down Drivers

VD D Q

VO ut

O ut

VS S

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GS841Z18/36AT-180/166/150/100

Preliminary

TQFP Package Drawing    

BPR 1999.05.18

D1

D

E1

E

Pin 1

b

e

c

L

L1

A2

A1

Y

θ

  

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Symbol

Description

Min. Nom. Max

A1

Standoff

0.05

0.10

0.15

A2

Body Thickness

1.35

1.40

1.45

b

Lead Width

0.20

0.30

0.40

c

Lead Thickness

0.09

0.20

D

Terminal Dimension

21.9

22.0

22.1

D1

Package Body

19.9

20.0

20.1

E

Terminal Dimension

15.9

16.0

16.1

E1

Package Body

13.9

14.0

14.1

e

Lead Pitch

0.65

L

Foot Length

0.45

0.60

0.75

L1

Lead Length

1.00

Y

Coplanarity

0.10

θ

Lead Angle

0

°

7

°

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GS841Z18/36AT-180/166/150/100

Preliminary

 Ordering Information—GSI NBT Synchronous SRAM

Org

Part Number

1

Type

Package

Speed

2

(MHz/ns)

T

A

3

Status

256K x 18

GS841Z18AT-180

NBT Pipeline/Flow Through

TQFP

180/8

C

256K x 18

GS841Z18AT-166

NBT Pipeline/Flow Through

TQFP

166/8.5

C

256K x 18

GS841Z18AT-150

NBT Pipeline/Flow Through

TQFP

150/10

C

256K x 18

GS841Z18AT-100

NBT Pipeline/Flow Through

TQFP

100/12

C

128K x 36

GS841Z36AT-180

NBT Pipeline/Flow Through

TQFP

180/8

C

128K x 36

GS841Z36AT-166

NBT Pipeline/Flow Through

TQFP

166/8.5

C

128K x 36

GS841Z36AT-150

NBT Pipeline/Flow Through

TQFP

150/10

C

128K x 36

GS841Z36AT-100

NBT Pipeline/Flow Through

TQFP

100/12

C

256K x 18

GS841Z18AT-180I

NBT Pipeline/Flow Through

TQFP

180/8

I

256K x 18

GS841Z18AT-166I

NBT Pipeline/Flow Through

TQFP

166/8.5

I

256K x 18

GS841Z18AT-150I

NBT Pipeline/Flow Through

TQFP

150/10

I

256K x 18

GS841Z18AT-100I

NBT Pipeline/Flow Through

TQFP

100/12

I

128K x 36

GS841Z36AT-180I

NBT Pipeline/Flow Through

TQFP

180/8

I

128K x 36

GS841Z36AT-166I

NBT Pipeline/Flow Through

TQFP

166/8.5

I

128K x 36

GS841Z36AT-150I

NBT Pipeline/Flow Through

TQFP

150/10

I

128K x 36

GS841Z36AT-100I

NBT Pipeline/Flow Through

TQFP

100/12

I

 Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8Z36A-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns)  in Flow Through mode. Each 

device is Pipeline/Flow Through mode-selectable by the user.

3. T

A

 = C = Commercial Temperature Range. T

A

 = I = Industrial Temperature Range. 

4. GSI offers other versions this type of device in many different configurations and with a variety of different  features, only some          

     

of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

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© 2001, Giga Semiconductor, Inc.

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Preliminary

4Mb Synchronous NBT Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page /Revisions/Reason

841Z18A_r1

• Creation of new datasheet

841Z18A_r1; 

841Z18A_r1_01

Content

• Changed description of E2 in pin description table (from active 

low to active high)

• Removed pin locations from pin description table

• Removed 200 MHz speed bin


Document Outline