background image

Rev:  2.04  6/2000

1/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840H18/32/36T/B-180/166/150/100

 256K x 18, 128K x 32, 128K x 36

4Mb Sync Burst SRAMs

180Mhz - 100Mhz

3.3V VDD

3.3V & 2.5V I/O

TQFP, BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user configurable flow through or pipelined operation.

• Single Cycle Deselect (SCD) Operation.

• High Output Drive current.

• 3.3V +10%/-5% Core power supply

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.

• Default to Interleaved Pipelined Mode.

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

• Automatic power-down for portable applications.

• JEDEC standard 100-lead TQFP or 119 Bump BGA  package.

  

Functional Description

Applications

The GS840H18/32/36 is a 4,718,592 bit (4,194,304 bit for x32 

version) high performance synchronous SRAM with a 2 bit burst 

address counter. Although of a type originally developed for Level 2 

Cache applications supporting high performance CPU’s, the device 

now finds application in synchronous SRAM applications ranging from 

DSP main store to networking chip set support. The GS840H18/32/36 

is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA  

package.

Controls 

Addresses, data I/O’s, chip enables (E

1

, E

2

, E

3

), address burst control 

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are 

synchronous and are controlled by a positive edge triggered clock 

input (CK). Output enable (G) and power down control (ZZ) are 

asynchronous inputs. Burst cycles can be initiated with either ADSP 

or ADSC inputs. In Burst mode, subsequent burst addresses are 

generated internally and are controlled by ADV. The burst address 

counter may be configured to count in either linear or interleave order 

with the Linear Burst Order (LBO) input. The Burst function need not 

be used. New addresses can be loaded on every cycle with no 

degradation of chip performance.

Flow Through / Pipeline Reads

The function of the Data Output register can be controlled by the user 

via the FT mode pin/bump (pin 14 in the TQFP and  bump 5R in the 

BGA, ). Holding the FT mode pin/bump low places the RAM in Flow 

through mode, causing output data to bypass the Data Output 

Register. Holding FT high places the RAM in Pipelined Mode, 

activating the rising edge triggered Data Output Register.

SCD Pipelined Reads

The GS840H18/32/36 is an SCD (Single Cycle Deselect) pipelined 

synchronous SRAM. DCD (Dual Cycle Deselect) versions are also 

available.SCD SRAMs pipeline deselect commands one stage less 

than read commands. SCD RAMs begin turning off their outputs 

immediately after the deselect command has been captured in the 

input registers. 

Byte Write and Global Write

Byte write operation is performed by using byte write enable (BW) 

input combined with one or more individual byte write signals (Bx). In 

addition, Global Write (GW) is available for writing all bytes at one 

time, regardless of the Byte Write control inputs. 

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of 

the ZZ signal, or by stopping the clock (CK). Memory data is retained 

during Sleep mode. 

Core and Interface Voltages

The GS840H18/32/36 operates on a 3.3V power supply and all 

inputs/outputs are 3.3V and 2.5V compatible. Separate output power 

(V

DDQ

) pins are used to de-couple output noise from the internal 

circuit.

-180

-166

-150

-100

Pipeline

3-1-1-1

tCycle

t

KQ

I

DD

5.5ns

3.2ns

330mA

6.0ns

3.5ns

310mA

6.6ns

3.8ns

275mA

10ns

4.5ns

190mA

Flow Through

2-1-1-1

t

KQ

tCycle

I

DD

8ns

10ns

190mA

8.5ns

10ns

190mA

10ns

10ns

190mA

12ns

15ns

140mA

background image

Rev:  2.04  6/2000

2/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 

GS840H18 100 Pin TQFP Pinout

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

DDQ

V

SS    

DQ

B1

DQ

B2

V

SS   

V

DDQ    

DQ

B3

DQ

B4

V

DD    

NC

V

SS   

DQ

B5

DQ

B6

V

DDQ    

V

SS   

DQ

B7

DQ

B8

DQ

B9

V

SS   

V

DDQ    

V

DDQ

V

SS

DQ

A8

DQ

A7

V

SS

V

DDQ

DQ

A6

DQ

A5

V

SS

NC

V

DD

ZZ

DQ

A4

DQ

A3

V

DDQ

V

SS

DQ

A2

DQ

A1

V

SS

V

DDQ

L

B

O

A

5

A

4

A

3

A

2

A

1

A

0

N

C

N

C

V

SS

V

D

D

N

C

 N

C

 A

10

 A

11

 A

12

 A

13

 A

14

 A

16

A

6

A

7

E

1

E

2

 

N

C

N

C

B

B

B

A

E

3

C

K

G

W

B

W

V

D

D

V

SS

G

A

D

S

C

A

D

S

P

A

D

V

A

8

A

9

 A

15

256K x 18

Top View

DQ

A9

A

17

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

FT

background image

Rev:  2.04  6/2000

3/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 

GS840H32 100 Pin TQFP Pinout

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

DDQ

V

SS    

DQ

C4

DQ

C3

V

SS  

V

DDQ     

DQ

C2

DQ

C1

V

DD    

NC

V

SS    

DQ

D1

DQ

D2

V

DDQ     

V

SS   

DQ

D3

DQ

D4

DQ

D5

V

SS   

V

DDQ    

V

DDQ

V

SS

DQ

B4

DQ

B3

V

SS

V

DDQ

DQ

B2

DQ

B1

V

SS

NC

V

DD

ZZ

DQ

A1

DQ

A2

V

DDQ

V

SS

DQ

A3

DQ

A4

V

SS

V

DDQ

L

B

O

A

5

A

4

A

3

A

2

A

1

A

0

N

C

N

C

V

SS

V

D

D

N

C

 N

C

 A

10

 A

11

 A

12

 A

13

 A

14

 A

16

A

6

A

7

E

1

E

2

 

B

D

B

C

B

B

B

A

E

3

C

K

G

W

B

W

V

D

D

V

SS

G

A

D

S

C

A

D

S

P

A

D

V

A

8

A

9

 A

15

128K x 32

Top View

DQ

B5

NC

DQ

B7

DQ

B8

DQ

B6

DQ

A6

DQ

A5

DQ

A8

DQ

A7

NC

DQ

C7

DQ

C8

DQ

C6

DQ

D6

DQ

D8

DQ

D7

NC

DQ

C5

NC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

FT

background image

Rev:  2.04  6/2000

4/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 

GS840H36 100 Pin TQFP Pinout

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

DDQ

V

SS    

DQ

C4

DQ

C3

V

SS   

V

DDQ     

DQ

C2

DQ

C1

V

DD    

NC

V

SS    

DQ

D1

DQ

D2

V

DDQ     

V

SS   

DQ

D3

DQ

D4

DQ

D5

V

SS   

V

DDQ     

V

DDQ

V

SS

DQ

B4

DQ

B3

V

SS

V

DDQ

DQ

B2

DQ

B1

V

SS

NC

V

DD

ZZ

DQ

A1

DQ

A2

V

DDQ

V

SS

DQ

A3

DQ

A4

V

SS

V

DDQ

L

B

O

A

5

A

4

A

3

A

2

A

1

A

0

N

C

N

C

V

SS

V

D

D

N

C

 N

C

 A

10

 A

11

 A

12

 A

13

 A

14

 A

16

A

6

A

7

E

1

E

2

 

B

D

B

C

B

B

B

A

E

3

C

K

G

W

B

W

V

D

D

V

SS

G

A

D

S

C

A

D

S

P

A

D

V

A

8

A

9

 A

15

128K x 36

Top View

DQ

B5

DQ

B9

DQ

B7

DQ

B8

DQ

B6

DQ

A6

DQ

A5

DQ

A8

DQ

A7

DQ

A9

DQ

C7

DQ

C8

DQ

C6

DQ

D6

DQ

D8

DQ

D7

DQ

D9

DQ

C5

DQ

C9

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

FT

background image

Rev:  2.04  6/2000

5/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

TQFP Pin Description

Pin Location

Symbol

Type

Description

37, 36

A

0

, A

1

I

Address field LSB’s and Address Counter preset Inputs

35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46, 

47, 48, 49, 50 

A

2

-

16

I

Address Inputs

80

A

17

I

Address Inputs (x18 versions)

52, 53, 56, 57, 58, 59, 62, 63

68, 69, 72, 73, 74, 75, 78, 79

2, 3, 6, 7, 8, 9, 12, 13

18, 19, 22, 23, 24, 25, 28, 29

DQ

A1

-DQ

A8

DQ

B1

-DQ

B8

DQ

C1

-DQ

C8

DQ

D1

-DQ

D8

I/O

Data Input and Output pins. (x32, x36 Version)

51, 80, 1, 30

DQ

A9

, DQ

B9

DQ

C9

, DQ

D9

I/O

Data Input and Output pins. (x36 Version)

51, 80, 1, 30

NC

No Connect (x32 Version)

58, 59, 62, 63, 68, 69, 72, 73, 74

8, 9, 12, 13, 18, 19, 22, 23, 24

DQ

A1

-DQ

A9

DQ

B1

-DQ

B9

I/O

Data Input and Output pins. (x18 Version)

51, 52, 53, 56, 57

75, 78, 79

1, 2, 3, 6, 7

25, 28, 29, 30

NC

-

No Connect (x18 Version)

87

BW

I

Byte Write. Writes all enabled bytes. Active Low.

93, 94

B

A

, B

B

I

Byte Write Enable for DQ

A

, DQ

B

 Data I/O’s. Active Low.

95, 96

B

C

, B

D

I

Byte Write Enable for DQ

C

, DQ

D

 Data I/O’s. Active Low. 

(x32, x36 Version)

95, 96

NC

-

No Connect (x18 Version)

89

CK

I

Clock Input Signal. Active High.

88

GW

I

Global Write Enable. Writes all bytes. Active Low.

98, 92

E

1

, E

3

I

Chip Enable. Active Low.

97

E

2

I

Chip Enable. Active High.

86

G

I

Output Enable. Active Low.

83

ADV

I

Burst address counter advance enable. Active Low.

84, 85

ADSP, ADSC

I

Address Strobe (Processor, Cache Controller). Active Low.

64

ZZ

I

Sleep Mode control. Active High.

14

FT

I

Flow Through or Pipeline mode. Active Low.

31

LBO

I

Linear Burst Order mode. Active Low.

15, 41, 65, 91

V

DD

I

Core power supply.

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90

V

SS

I

I/O and Core Ground.

4, 11, 20, 27, 54, 61, 70, 77

V

DDQ

I

Output driver power supply.

 16, 38, 39, 42, 43, 66

NC

-

No Connect.

background image

Rev:  2.04  6/2000

6/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

GS840H18 Pad Out

   

 

119 Bump BGA - Top View

1

2

3

4

5

6

7

A

V

DDQ

A

6

A

7

ADSP

A

8

A

9

V

DDQ

B

NC

E

2

A

4

ADSC

A

15

E

3

NC

C

NC

A

5

A

3

V

DD

A

14

A

16

NC

D

DQ

B1

NC

V

SS

NC

V

SS

DQ

A9

NC

E

NC

DQ

B2

V

SS

E

1

V

SS

NC

DQ

A8

F

V

DDQ

NC

V

SS

G

V

SS

DQ

A7

V

DDQ

G

NC

D

Q

B3

B

B

ADV 

NC

NC

DQ

A6

H

DQ

B4

N

C

V

SS

GW

V

SS

DQ

A5

NC

J

V

DDQ

V

DD

NC

V

DD

NC

V

DD

V

DDQ

K

NC

DQ

B5

V

SS

CK

V

SS

NC

DQ

A4

L

DQ

B6

NC

NC

NC

B

A

DQ

A3

NC

M

V

DDQ

DQ

B7

V

SS

BW

V

SS

NC

V

DDQ

N

DQ

B8

NC

V

SS

A

1

V

SS

DQ

A2

NC

P

NC

DQ

B9

V

SS

A

0

V

SS

NC

DQ

A1

R

NC

A

2

LBO

V

DD

FT

A

13

NC

T

NC

A

10

A

11

NC

A

12

 A

17

ZZ

U

V

DDQ

NC

NC

NC

NC

NC

V

DDQ

background image

Rev:  2.04  6/2000

7/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

GS840H32 Pad Out

   

 

119 Bump BGA - Top View

1

2

3

4

5

6

7

A

V

DDQ

A

6

A

7

ADSP

A

8

A

9

V

DDQ

B

NC

E

2

A

4

ADSC

A

15

E

3

NC

C

NC

A

5

A

3

V

DD

A

14

A

16

NC

D

DQ

C4

NC

V

SS

NC

V

SS

NC

DQ

B4

E

DQ

C3

DQ

C8

V

SS

E

1

V

SS

DQ

B8

DQ

B3

F

V

DDQ

DQ

C7

V

SS

G

V

SS

DQ

B7

V

DDQ

G

DQ

C2

D

Q

C6

B

C

ADV 

B

B

DQ

B6

DQ

B2

H

DQ

C1

DQ

C5

V

SS

GW

V

SS

DQ

B5

DQ

B1

J

V

DDQ

V

DD

NC

V

DD

NC

V

DD

V

DDQ

K

DQ

D1

DQ

D5

V

SS

CK

V

SS

DQ

A5

DQ

A1

L

DQ

D2

DQ

D6

B

D

NC

B

A

DQ

A6

DQ

A2

M

V

DDQ

DQ

D78

V

SS

BW

V

SS

DQ

A7

V

DDQ

N

DQ

D3

DQ

D8

V

SS

A

1

V

SS

DQ

A8

DQ

A3

P

DQ

D4

NC

V

SS

A

0

V

SS

NC

DQ

A4

R

NC

A

2

LBO

V

DD

FT

A

13

NC

T

NC

NC

A

10

A

11

A

12

 NC

ZZ

U

V

DDQ

NC

NC

NC

NC

NC

V

DDQ

background image

Rev:  2.04  6/2000

8/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

GS840H36Pad Out

   

 

119 Bump BGA - Top View

1

2

3

4

5

6

7

A

V

DDQ

A

6

A

7

ADSP

A

8

A

9

V

DDQ

B

NC

E

2

A

4

ADSC

A

15

E

3

NC

C

NC

A

5

A

3

V

DD

A

14

A

16

NC

D

DQ

C4

DQ

C9

V

SS

NC

V

SS

DQ

B9

DQ

B4

E

DQ

C3

DQ

C8

V

SS

E

1

V

SS

DQ

B8

DQ

B3

F

V

DDQ

DQ

C7

V

SS

G

V

SS

DQ

B7

V

DDQ

G

DQ

C2

D

Q

C6

B

C

ADV 

B

B

DQ

B6

DQ

B2

H

DQ

C1

DQ

C5

V

SS

GW

V

SS

DQ

B5

DQ

B1

J

V

DDQ

V

DD

NC

V

DD

NC

V

DD

V

DDQ

K

DQ

D1

DQ

D5

V

SS

CK

V

SS

DQ

A5

DQ

A1

L

DQ

D2

DQ

D6

B

D

NC

B

A

DQ

A6

DQ

A2

M

V

DDQ

DQ

D78

V

SS

BW

V

SS

DQ

A7

V

DDQ

N

DQ

D3

DQ

D8

V

SS

A

1

V

SS

DQ

A8

DQ

A3

P

DQ

D4

DQ

D9

V

SS

A

0

V

SS

DQ

A9

DQ

A4

R

NC

A

2

LBO

V

DD

FT

A

13

NC

T

NC

NC

A

10

A

11

A

12

 NC

ZZ

U

V

DDQ

NC

NC

NC

NC

NC

V

DDQ

background image

Rev:  2.04  6/2000

9/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

  

 

BGA Pin Description

Pin Location

Symbol

Type

Description

N4, P4

A

0

, A

1

I

Address field LSB’s and Address Counter Preset Inputs.

A2, A3, A5, A6, B3, B5, C2, C3, C5, 

C6, R2, R6, T3, T5

An

I

Address Inputs

T4

An

Address Input (x32/36 Versions)

T2, T6

NC

-

No Connect (x32/36 Versions)

T2, T6

An

I

Address Input (x18 Version)

K7, K6, L7, L6, M6, N7, N6, P7

H7, H6, G7, G6, F6, E7, E6, D7

H1, H2, G1, G2, F2, E1, E2, D1

K1, K2, L1, L2, M2, N1, N2, P1

DQ

A1

-DQ

A8

DQ

B1

-DQ

B8

DQ

C1

-DQ

C8

DQ

D1

-DQ

D8

I/O

Data Input and Output pins. (x32/36 Versions)

P6, D6, D2, P2

DQ

A9

, DQ

B9

DQ

C9

, DQ

D9

I/O

Data Input and Output pins. (x36 Version)

P6, D6, D2, P2

NC

-

No Connect (x32 Version)

L5, G5, G3, L3

B

A

, B

B

, B

C

, B

D

I

Byte Write Enable for DQ

A

, DQ

B

, DQ

C

, DQ

D

 I/O’s. Active Low. ( x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

DQ

A1

-DQ

A9

DQ

B1

-DQ

B9

I/O

Data Input and Output pins. (x18 Version)

L5, G3

B

A

, B

B

I

Byte Write Enable for DQ

A

, DQ

B

 I/O’s. Active Low. ( x18 Version)

B1, C1, R1, T1, U2, J3, U3, D4, L4, 

U4, J5, U5, U6, B7, C7, R7

NC

-

No Connect

P6, N7, M6, L7, K6, H7, G6, E6, D7, 

D2, B1, E1, F2, G1, H2, K1, L2, N2, 

P1, G5, L3, T4

NC

-

No Connect (x18 Version)

K4

CK

I

Clock Input Signal. Active High.

M4

BW

I

Byte Write. Writes all enabled bytes. Active Low.

H4

GW

I

Global Write Enable. Writes all bytes. Active Low.

E4, B6

E

1

, E

3

I

Chip Enable. Active Low.

B2

E

2

I

Chip Enable. Active High.

F4

G

I

Output Enable. Active Low.

G4

ADV

I

Burst address counter advance enable. Active Low.

A4, B4

ADSP, ADSC

I

Address Strobe (Processor, Cache Controller). Active Low.

T7

ZZ

I

Sleep Mode control. Active High.

R5

FT

I

Flow Through or Pipeline mode. Active Low.

R3

LBO

I

Linear Burst Order mode. Active Low.

J2, C4, J4, R4, J6

V

DD

I

Core power supply.

D3, E3, F3, H3, K3, M3, N3, P3, D5, 

E5, F5, H5, K5, M5, N5, P5

V

SS

I

I/O and Core Ground.

A1, F1, J1, M1, U1, A7, F7, J7, M7, 

U7

V

DDQ

I

Output driver power supply.

background image

Rev:  2.04  6/2000

10/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

         

GS840H18/32/36 Block Diagram

A1

A0

A0

A1

D0

D1

Q1

Q0

Counter

Load

D

Q

D

Q

Register

Register

D

Q

Register

D

Q

Register

D

Q

Register

D

Q

Register

D

Q

Register

D

Q

Register

D

Q

R

e

g

is

te

r

D

Q

R

e

g

is

te

r

A0-An

LBO

ADV

CK

ADSC

ADSP

GW

BW

B

A

B

B

B

C

B

D

E

1

G

ZZ

Power Down

Control

Memory

Array

36

36

4

A

Q

D

E

3

E

2

DQx0-DQx9

Note: Only x36 version shown for simplicity.

1

FT

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Rev:  2.04  6/2000

11/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 

Note:

There are pull up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will 

operate in the default states as specified in the above tables.

Burst Counter Sequences

Byte Write Truth Table

Note:

1. All byte outputs are active in read cycles regardle

ss

 of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs B

A

, B

B

, B

C

 and/or B

D

 may be used in any combination with BW to write single or multiple bytes.

3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “

C

” and “

D

” are only available on the x32 and x36 versions.

Mode Pin Functions

Mode Name

Pin Name State

Function

Burst Order Control

LBO

L

Linear Burst

H or NC

Interleaved Burst

Output Register Control

FT

L

Flow Through

H or NC

Pipeline

Power Down Control

ZZ

L or NC

Active

Standby, I

DD

 = I

SB

Function

GW

BW

B

A

B

B

B

C

B

D

Notes

Read

H

H

X

X

X

X

1

Read

H

L

H

H

H

H

1

Write byte 

A

H

L

L

H

H

H

2, 3

Write byte 

B

H

L

H

L

H

H

2, 3

Write byte 

C

H

L

H

H

L

H

2, 3, 4

Write byte 

D

H

L

H

H

H

L

2, 3, 4

Write all bytes

H

L

L

L

L

L

2, 3, 4

Write all bytes

L

X

X

X

X

X

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

I

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0]

A[1:0]

A[1:0]

A[1:0]

1st address

00

01

10

11

2nd address

01

10

11

00

3rd address

10

11

00

01

4th address

11

00

01

10

A[1:0]

A[1:0]

A[1:0]

A[1:0]

1st address

00

01

10

11

2nd address

01

00

11

10

3rd address

10

11

00

01

4th address

11

10

01

00

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Rev:  2.04  6/2000

12/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 Synchronous Truth Table

Operation

Address Used

State

Diagram

Key

5

E

1

E

2

ADSP ADSC

ADV

W

3

DQ

4

Deselect Cycle, Power Down

None

X

H

X

X

L

X

X

High-Z

Deselect Cycle, Power Down

None

X

L

F

L

X

X

X

High-Z

Deselect Cycle, Power Down

None

X

L

F

H

L

X

X

High-Z

Read Cycle, Begin Burst

External

R

L

T

L

X

X

X

Q

Read Cycle, Begin Burst

External

R

L

T

H

L

X

F

Q

Write Cycle, Begin Burst

External

W

L

T

H

L

X

T

D

Read Cycle, Continue Burst

Next

CR

X

X

H

H

L

F

Q

Read Cycle, Continue Burst

Next

CR

H

X

X

H

L

F

Q

Write Cycle, Continue Burst

Next

CW

X

X

H

H

L

T

D

Write Cycle, Continue Burst

Next

CW

H

X

X

H

L

T

D

Read Cycle, Suspend Burst

Current

X

X

H

H

H

F

Q

Read Cycle, Suspend Burst

Current

H

X

X

H

H

F

Q

Write Cycle, Suspend Burst

Current

X

X

H

H

H

T

D

Write Cycle, Suspend Burst

Current

H

X

X

H

H

T

D

Note:

1. X = Don’t Care, H = High, L = Low.

2. E = T (True) if E

2

 = 1 and E

3

 = 0;  E = F (False) if E

2

 = 0 or E

= 1.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.  

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown 

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish 

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

background image

Rev:  2.04  6/2000

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© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

  

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CR

CW

X

X

W

R

R

W

R

X

X

X

Si

m

pl

Sy

nc

hr

on

ou

O

pe

ra

tio

n

Si

m

pl

Bu

rs

t S

yn

ch

ro

no

us

 O

pe

ra

tio

n

CR

R

CW

CR

CR

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.

2. The upper portion of the diagram assumes active use of only the Enable (E

1, 

E

2, 

E

3

) and Write (B

A

, B

B

, B

C

, B

D

, BW and GW) control inputs 

and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes 

ADSP is tied high and ADV is tied low.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

  

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CR

CW

X

X

W

R

R

W

R

X

X

X

CR

R

CW

CR

CR

W

CW

W

CW

Simplified State Diagram with G

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported  transitions that depend upon the use of G. 

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing 

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet 

Data Input Set Up Time.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

  

Note:

 

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended 

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of 

this component.  

   

Note:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V 

 VDDQ 

 2.375V (i.e. 2.5V I/O) 

and 3.6V 

 VDDQ 

 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case. 

2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges.  The part number of 

Industrial Temperature Range versions end the character “I”.  Unless otherwise noted, all performance specifications quoted are evaluated 

for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be -2V > Vi < V

DD

+2V with a pulse width not to exceed 20% tKC.

Absolute Maximum Ratings

(All voltages reference to V

SS

)

Symbol

Description

Value

Unit

V

DD

Voltage on V

DD

 Pins

-0.5 to 4.6

V

V

DDQ

Voltage in V

DDQ

 Pins

-0.5 to V

DD

V

V

CK

Voltage on Clock Input Pin

-0.5 to 6

V

V

I/O

Voltage on I/O Pins

-0.5 to V

DDQ

+0.5  (

 4.6 V max.)

V

V

IN

Voltage on Other Input Pins

-0.5 to V

DD

+0.5  (

 4.6 V max.)

V

I

IN

Input Current on Any Pin

+/- 20

mA

I

OUT

Output Current on Any I/O Pin

+/- 20

mA

P

D

Package Power Dissipation 

1.5

W

T

STG

Storage Temperature

-55 to 125

o

C

T

BIAS

Temperature Under Bias

-55 to 125

o

C

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Supply Voltage

V

DD

3.135

3.3

3.6

V

I/O Supply Voltage

V

DDQ

2.375

2.5

V

DD

V

1

Input High Voltage

V

IH

1.7

---

V

DD

+0.3

V

2

Input Low Voltage

V

IL

-0.3

---

0.8

V

2

Ambient Temperature (Commercial Range Versions)

T

A

0

25

70

°

C

3

Ambient Temperature (Industrial Range Versions)

T

A

-40

25

85

°

C

3

background image

Rev:  2.04  6/2000

16/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

     

  

Note: This parameter is sample tested.

 

Notes: 

Notes: 

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-

ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87.

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.

4.     For x18 configuration, consult factory.

Capacitance

 

(T

A

=25

o

C, f=1MH

Z

, V

DD

=3.3V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Control Input Capacitance

C

I

V

DD

=3.3V

3

4

pF

Input Capacitance

C

IN

V

IN

=0V

4

5

pF

Output Capacitance

C

OUT

V

OUT

=0V

6

7

pF

Package Thermal Characteristics

Rating

Layer Board

Symbol

TQFP Max

BGA Max

Unit

Notes

Junction to Ambient (at 200 lfm)

single 

R

Θ

JA

40

38

°

C/W

1,2,4

Junction to Ambient (at 200 lfm)

four 

R

Θ

JA

24

21

°

C/W

1,2,4

Junction to Case (TOP)

R

Θ

JC

9

5

°

C/W

3,4

20% tKC

V

SS

-2.0V

50%

V

SS

V

IH

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

V

DD

+-2.0V

50%

V

DD

V

IL

background image

Rev:  2.04  6/2000

17/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for t

LZ

, t

HZ

, t

OLZ

 and t

OHZ

.

4. Device is deselected as defined by the Truth Table. 

   

AC Test Conditions

Parameter

Conditions

Input high level

 2.3V

Input low level

0.2V

Input slew rate

1V/ns

Input reference level

1.25V

Output reference level

1.25V

Output load 

Fig. 1& 2

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

IL

V

IN 

= 0 to V

DD

-1uA

1uA

ZZ Input Current

I

INZZ

V

DD

 

 

V

IN 

 

V

IH

0V

 

≤ 

V

IN 

≤ 

V

IH

-1uA

-1uA

1uA

300uA

Mode Pin Input Current

I

INM

V

DD

 

 

V

IN 

 

V

IL

0V

 

≤ 

V

IN 

≤ 

V

IL

-300uA

-1uA

1uA

1uA

Output Leakage Current

I

OL

Output Disable,

V

OUT

 = 0 to V

DD

-1uA

1uA

Output High Voltage

V

OH

I

OH 

= - 8mA, V

DDQ

=2.375V

1.7V

Output High Voltage

V

OH

I

OH 

= - 8mA, V

DDQ

=3.135V

2.4V

Output Low Voltage

V

OL

I

OL 

= 8mA

0.4V

DQ

VT=1.25V

50

30pF

*

DQ

2.5V

Output Load 1

Output Load 2

225

225

5pF

*

* Distributed Test Jig Capacitance

background image

Rev:  2.04  6/2000

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© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

Operating Currents

Parameter Test Conditions Symbol

-180

-166

-150

-100

0 to 

70°C

-40 to 

85°C

0 to 

70°C

-40 to 

85°C

0 to 

70°C

-40 to 

85°C

0 to 

70°C

-40 to 

85°C

Operating

Current

Device Selected; 

All other inputs

 

V

IH

 

o

≤ 

V

IL

Output

 

open

I

DD

Pipeline

330mA 340mA 310mA 320mA 275mA 285mA 190mA 200mA

I

DD

Flow-Thru

190mA 200mA 190mA 200mA 190mA 200mA 140mA 150mA

Standby

Current

ZZ

 

≥ 

V

DD

 

- 0.2V

I

SB

Pipeline

30mA

40mA

30mA

40mA

30mA

40mA

30mA

40mA

I

SB

Flow-Thru

30mA

40mA

30mA

40mA

30mA

40mA

30mA

40mA

Deselect

Current

Device Deselected; 

All other inputs

 

≥ 

V

IH

 

or

 

 V

IL

I

DD

Pipeline

120mA 130mA 110mA 120mA 105mA 115mA 80mA

90mA

I

DD

Flow-Thru

80mA

90mA

80mA

90mA

80mA

90mA

65mA

75mA

background image

Rev:  2.04  6/2000

19/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

AC Electrical Characteristics

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold 

times as specified above.

Parameter

Symbol

-180

-166

-150

-100

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Pipeline

Clock Cycle Time

tKC

5.5

---

6.0

---

6.7

---

10

---

ns

Clock to Output Valid

tKQ

---

3.2

---

3.5

---

3.8

---

4.5

ns

Clock to Output Invalid

tKQX

1.5

---

1.5

---

1.5

---

1.5

---

ns

Clock to Output in Low-Z

tLZ

1

1.5

---

1.5

---

1.5

---

1.5

---

ns

Flow-

Thru

Clock Cycle Time

tKC

10.0

---

10.0

---

10.0

---

15.0

---

ns

Clock to Output Valid

tKQ

---

8.0

---

8.5

---

10.0

---

12.0

ns

Clock to Output Invalid

tKQX

3.0

---

3.0

---

3.0

---

3.0

---

ns

Clock to Output in Low-Z

tLZ

1

3.0

---

3.0

---

3.0

---

3.0

---

ns

Clock HIGH Time

tKH

1.3

---

1.3

---

1.5

---

2

---

ns

Clock LOW Time

tKL

1.5

---

1.5

---

1.7

---

2.2

---

ns

Clock to Output in High-Z

tHZ

1

1.5 

3.2

1.5

3.5

1.5 

3.8

1.5

5

ns

G to Output Valid

tOE

---

3.2

---

3.5

---

3.8

---

5

ns

G to output in Low-Z

tOLZ

1

0

---

0

---

0

---

0

---

ns

G to output in High-Z

tOHZ

1

---

3.2

---

3.5

---

3.8

---

5

ns

Setup time

tS

1.5

---

1.5

---

1.5

---

2.0

---

ns

Hold time

tH

0.5

---

0.5

---

0.5

---

0.5

---

ns

ZZ setup time

tZZS

2

5

---

5

---

5

---

5

---

ns

ZZ hold time

tZZH

2

1

---

1

---

1

---

1

---

ns

ZZ recovery

tZZR

20

---

20

---

20

---

20

---

ns

background image

Rev:  2.04  6/2000

20/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

CK

ADSP

ADSC

ADV

GW

BW

G

WR2

WR3

WR1

WR1

WR2

WR3

tKC

Single Write

Burst  Write

D2a

D2b

D2c

D2d

D3a

D1

a

t

KL

t

KH

tS tH

tS tH

tS tH

tS tH

tS tH

tS tH

tS tH

tS tH

Write specified byte for 2

a

 and all bytes for 2

b

, 2

c

& 2

d

ADV must be inactive for ADSP Write

ADSC initiated write

ADSP is blocked by E

1

 inactive

A

0

-An

B

A

 - B

D

DQ

A

 - DQ

D

Write

Deselected

Hi-Z

WR1

WR2

WR3

       Write Cycle Timing

E

1

E

3

tS tH

tS tH

tS tH

E

2

 and E

3

 only sampled with ADSP or ADSC

E

1

 masks ADSP

E

2

Deselected with E

2

background image

Rev:  2.04  6/2000

21/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 

Q

1a

Q

3a

Q

2d

Q

2c

Q

2b

Q

2a

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2

RD3

tKL

tS

tH

tH

tS tH

tS tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E

1

 inactive

A

0

-An

B

A

 - B

D

 

tKH

tKC

tS tH

tS

tS

tH

DQ

A

-DQ

D

RD1

Hi-Z

Suspend Burst

Flow Through Read Cycle Timing

E

2

tS

tH

tH

tH

E

1

 masks ADSP

E

2

 and E

3

 only sampled with ADSP or ADSC 

Deselected with E

2

E

3

E

1

tS

tS

background image

Rev:  2.04  6/2000

22/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

  

Flow Through Read-Write Cycle Timing

CK

ADSP

ADSC

ADV

GW

BW

G

RD1

WR1

RD2

Q1a

D1a

Q2a

Q2b

Q2c

Q2d

Single Read

Burst Read

tOE

tOHZ

tS tH

tS

tH

tH

tS tH

tS tH

tS tH

tS tH

tKH

ADSC initiated read

DQ

A

 - DQ

D

B

A

 - B

D

A0-An

tKL

tKC

tS

Single Write

ADSP is blocked by E inactive

tKQ

tS

tH

Hi-Z

Q2a

Burst wrap around to it’s initial state

WR1

E

1

E

3

E

2

tS

tS tH

tS

E

1

 masks ADSP

E

2

 and E

3

 only sampled with ADSP and ADSC

Deselected with E

3

tH

tH

background image

Rev:  2.04  6/2000

23/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 

Pipelined SCD Read Cycle Timing

Q1a

Q3a

Q2d

Q2c

Q2b

Q2a

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2

RD3

tKL

tS

tH

tH

tS tH

tS tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E

1

 inactive

A

0

-A

17

BW

A

 - BW

D

 

tKH

tKC

tS

tH

tS

tS

tH

DQ

A

 - DQ

D

RD1

Hi-Z

E

2

tS

tH

tH

tH

E1 masks ADSP

E

2

 and E

3

 only sampled with ADSP or ADSC 

Deselected with E

2

E

3

E

1

tS

tS

background image

Rev:  2.04  6/2000

24/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

CK

ADSP

ADV

GW

BW

G

Q1a

D1a

Q2a

Q2b

Q2c

Q2d

Single Read

Burst Read

tOE

tOHZ

tS tH

tS

tH

tH

tS tH

tS tH

tKH

DQ

A

 - DQ

D

BW

A

 - BW

D

tKL

tKC

tS

Single Write

ADSP is blocked by E inactive

tKQ

tS tH

Hi-Z

Pipelined SCD Read - Write Cycle Timing

WR1

ADSC

tS tH

ADSC initiated read

RD1

WR1

RD2

tS tH

A0-An

E

1

E

3

E

2

tS

tS tH

tS

E

1

 masks ADSP

E

2

 and E

3

 only sampled with ADSP and ADSC

Deselected with E

3

tH

tH

background image

Rev:  2.04  6/2000

25/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

  

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in 

a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in 

transitions from reads to writes or between banks of RAMs.  DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to 

manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised 

to avoid excessive bus contention. 

CK

ADSP

ADSC

tH

tKH tKL

tKC

tS

ZZ

tZZR

tZZH

tZZS

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

Snooze

Sleep Mode Timing Diagram

background image

Rev:  2.04  6/2000

26/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

GS 840H18/32/36 Output Driver Characteristics

 

-140.0

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

80.0

100.0

120.0

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

V Out (Pull Down)

VDDQ - V Out (Pull Up)

I Out (mA)

3.6V PD HD

3.3V PD HD

3.1V PD HD

3.1V PU HD

3.3V PU HD

3.6V PU HD

Pull Up Drivers

Pull Down Drivers

VDDQ

VOut

I Out

VSS

background image

Rev:  2.04  6/2000

27/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 TQFP Package Drawing

   

D

1

D

E1

E

P

in

 1

b

e

c

L

L1

A2

A1

Y

θ

  

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion

Symbol

Description

Min. Nom. Max

A1

Standoff

0.05

0.10

0.15

A2

Body Thickness

1.35

1.40

1.45

b

Lead Width

0.20

0.30

0.40

c

Lead Thickness

0.09

0.20

D

Terminal Dimension

21.9

22.0

22.1

D1

Package Body

19.9

20.0

20.1

E

Terminal Dimension

15.9

16.0

16.1

E1

Package Body

13.9

14.0

14.1

e

Lead Pitch

0.65

L

Foot Length

0.45

0.60

0.75

L1

Lead Length

1.00

Y

Coplanarity

0.10

θ

Lead Angle

0

°

7

°

background image

Rev:  2.04  6/2000

28/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

 Package Dimensions - 119 Pin BGA

  N

P

  

A

  B

 

Pin 1

Corner

K

E

F

C

T

  

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

G

S

D

1

2

3

4

5

6

7

 Package Dimensions - 119 Pin BGA

Unit: mm

Symbol

Description

Min. Nom. Max

A

Width

13.8

14.0

14.2

B

Length

21.8

22.0

22.2

C

Package Height (including ball)

-

2.40

D

Ball Size

0.60

0.75

0.90

E

Ball Height

0.50

0.60

0.70

F

Package Height (excluding balls)

1.46

1.70

G

Width between Balls

1.27

K

Package Height above board 

0.80

0.90

1.00

N

Cut-out Package Width

12.00

P

Foot Length

19.50

R

Width of package between balls

7.62

S

Length of package between balls

20.32

T

Variance of Ball Height

0.15

Bottom View

R

Top View

Side View

background image

Rev:  2.04  6/2000

29/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

   Ordering Information for GSI Synchronous Burst RAMS

Org

Part Number

1

Type

Package

Speed

2

(Mhz/

ns)

T

A

3

Status

256K x 18

GS840H18T-180

Pipeline/Flow Through

TQFP

180/8

C

256K x 18

GS840H18T-166

Pipeline/Flow Through

TQFP

166/8.5

C

256K x 18

GS840H18T-150

Pipeline/Flow Through

TQFP

150/10

C

256K x 18

GS840H18T-100

Pipeline/Flow Through

TQFP

100/12

C

128K x 32

GS840H32T-180

Pipeline/Flow Through

TQFP

180/8

C

128K x 32

GS840H32T-166

Pipeline/Flow Through

TQFP

166/8.5

C

128K x 32

GS840H32T-150

Pipeline/Flow Through

TQFP

150/10

C

128K x 32

GS840H32T-100

Pipeline/Flow Through

TQFP

100/12

C

128K x 36

GS840H36T-180

Pipeline/Flow Through

TQFP

180/8

C

128K x 36

GS840H36T-166

Pipeline/Flow Through

TQFP

166/8.5

C

128K x 36

GS840H36T-150

Pipeline/Flow Through

TQFP

150/10

C

128K x 36

GS840H36T-100

Pipeline/Flow Through

TQFP

100/12

C

256K x 18

GS840H18T-180I

Pipeline/Flow Through

TQFP

180/8

I

Not Available

256K x 18

GS840H18T-166I

Pipeline/Flow Through

TQFP

166/8.5

I

256K x 18

GS840H18T-150I

Pipeline/Flow Through

TQFP

150/10

I

256K x 18

GS840H18T-100I

Pipeline/Flow Through

TQFP

100/12

I

128K x 32

GS840H32T-180I

Pipeline/Flow Through

TQFP

180/8

I

Not Available

128K x 32

GS840H32T-166I

Pipeline/Flow Through

TQFP

166/8.5

I

128K x 32

GS840H32T-150I

Pipeline/Flow Through

TQFP

150/10

I

128K x 32

GS840H32T-100I

Pipeline/Flow Through

TQFP

100/12

I

128K x 36

GS840H36T-180I

Pipeline/Flow Through

TQFP

180/8

I

Not Available

128K x 36

GS840H36T-166I

Pipeline/Flow Through

TQFP

166/8.5

I

128K x 36

GS840H36T-150I

Pipeline/Flow Through

TQFP

150/10

I

128K x 36

GS840H36T-100I

Pipeline/Flow Through

TQFP

100/12

I

256K x 18

GS840H18B-180

Pipeline/Flow Through

BGA

180/8

C

256K x 18

GS840H18B-166

Pipeline/Flow Through

BGA

166/8.5

C

256K x 18

GS840H18B-150

Pipeline/Flow Through

BGA

150/10

C

256K x 18

GS840H18B-100

Pipeline/Flow Through

BGA

100/12

C

128K x 32

GS840H32B-180

Pipeline/Flow Through

BGA

180/8

C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T.

2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns)  in Flow Through mode. 

Each device is Pipeline / Flow through mode selectable by the user.

3. T

A

 = C = Commercial Temperature Range. T

A

 = I = Industrial Temperature Range.

4.  GSI offers other versions this type of device in many different configurations and with a variety of different  features, only some of which 

are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.

background image

Rev:  2.04  6/2000

30/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

128K x 32

GS840H32B-166

Pipeline/Flow Through

BGA

166/8.5

C

128K x 32

GS840H32B-150

Pipeline/Flow Through

BGA

150/10

C

128K x 32

GS840H32B-100

Pipeline/Flow Through

BGA

100/12

C

128K x 36

GS840H36B-180

Pipeline/Flow Through

BGA

180/8

C

128K x 36

GS840H36B-166

Pipeline/Flow Through

BGA

166/8.5

C

128K x 36

GS840H36B-150

Pipeline/Flow Through

BGA

150/10

C

128K x 36

GS840H36B-100

Pipeline/Flow Through

BGA

100/12

C

256K x 18

GS840H18B-180I

Pipeline/Flow Through

BGA

180/8

I

Not Available

256K x 18

GS840H18B-166I

Pipeline/Flow Through

BGA

166/8.5

I

256K x 18

GS840H18B-150I

Pipeline/Flow Through

BGA

150/10

I

256K x 18

GS840H18B-100I

Pipeline/Flow Through

BGA

100/12

I

128K x 32

GS840H32B-180I

Pipeline/Flow Through

BGA

180/8

I

Not Available

128K x 32

GS840H32B-166I

Pipeline/Flow Through

BGA

166/8.5

I

128K x 32

GS840H32B-150I

Pipeline/Flow Through

BGA

150/10

I

128K x 32

GS840H32B-100I

Pipeline/Flow Through

BGA

100/12

I

128K x 36

GS840H36B-180I

Pipeline/Flow Through

BGA

180/8

I

Not Available

128K x 36

GS840H36B-166I

Pipeline/Flow Through

BGA

166/8.5

I

128K x 36

GS840H36B-150I

Pipeline/Flow Through

BGA

150/10

I

128K x 36

GS840H36B-100I

Pipeline/Flow Through

BGA

100/12

I

Org

Part Number

1

Type

Package

Speed

2

(Mhz/

ns)

T

A

3

Status

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T.

2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns)  in Flow Through mode. 

Each device is Pipeline / Flow through mode selectable by the user.

3. T

A

 = C = Commercial Temperature Range. T

A

 = I = Industrial Temperature Range.

4.  GSI offers other versions this type of device in many different configurations and with a variety of different  features, only some of which 

are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.

background image

Rev:  2.04  6/2000

31/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS840H18/32/36T/B-180/166/150/100

Revision History

Rev. Code: Old;

New

Types of Changes

Format or Content

Page /Revisions;Reason

GS840H18/32/36 Rev 1.02c 5/

1999;

GS840H18/32/36 2.00 8/1999D

Format/Typos

• Document/Continued changing to new format.

Content

• Added Fine Pitch BGA Package.

• 

GS840H18/32/362.00 8/

1999;GS840H18/32/362.01 9/

1999E 

Format/Typos

• Took “E” out of 840HE...in Core and Interface Voltages.

• Pin outs/New small caps format.

• Timing Diagrams/New format.

• Block Diagrams/New small caps format.

Content

• Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to DQB3.

• Pin Description/Rearranged Address Inputs to match order on TQFP Pinout.

• TQFP Package Diagram/Corrected Dimension D Max from 20.1 to 22.1.

• Corrected ordering information.

• 

GS840H18/32/362.01 9/

1999E;GS840H18/32/362.02 

• Took out Fine Pitch BGA Package. Package change in progress.

GS840H18/32/362.0210-11/

1999;GS840H18/32/362.032/

2000G

Format

• New GSI Logo

• Took “Pin” out of heading for consistency.

GS840E18/32/362.032/2000G; 

840H18_r2_04

Content

• Updated BGA pin description table to meet JEDEC standard