background image

TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA

FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

OPERATIONAL AMPLIFIERS

 

SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Wide Bandwidth . . . 10 MHz

D

High Output Drive

–  I

OH

. . . 57 mA at V

DD 

– 1.5

–  I

OL

. . . 55 mA at 0.5 V

D

High Slew Rate

–  SR+ . . . 16 V/

µ

s

–  SR– . . . 19 V/

µ

s

D

Wide Supply Range . . . 4.5 V to 16  V

D

Supply Current . . . 1.9 mA/Channel

D

Ultra-Low Power Shutdown Mode

I

DD

. . . 125 

µ

A/Channel

D

Low Input Noise Voltage . . . 7  nV

Hz

D

Input Offset Voltage . . . 60 

µ

V

D

Ultra-Small Packages

–  8 or 10 Pin MSOP (TLC070/1/2/3)

     

description

Introducing the first members of TI’s new BiMOS general-purpose operational amplifier family—the TLC07x.

The BiMOS family concept is simple: provide an upgrade path for BiFET users who are moving away from

dual-supply to single-supply systems and demand higher ac and dc performance. With performance rated from

4.5 V to 16 V across commercial (0

°

C to 70

°

C) and an extended industrial temperature range (–40

°

C to 125

°

C),

BiMOS suits a wide range of audio, automotive, industrial and instrumentation applications. Familiar features

like offset nulling pins, and new features like MSOP PowerPAD

 packages and shutdown modes, enable higher

levels of performance in a multitude of applications.

Developed in TI’s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input

impedance low-noise CMOS front end with a high-drive Bipolar output stage—thus providing the optimum

performance features of both. AC performance improvements over the TL07x BiFET predecessors include a

bandwidth of 10 MHz (an increase of 300%) and voltage noise of 7 nV/

Hz (an improvement of 60%). DC

improvements include a factor of 4 reduction in input offset voltage down to 1.5 mV (maximum) in the standard

grade, and a power supply rejection improvement of greater than 40 dB to 130 dB. Added to this list of impressive

features is the ability to drive 

±

50-mA loads comfortably from an ultra-small-footprint MSOP PowerPAD

package, which positions the TLC07x as the ideal high-performance general-purpose operational amplifier

family.

FAMILY PACKAGE TABLE

DEVICE

NO. OF

PACKAGE TYPES

SHUTDOWN

UNIVERSAL

DEVICE

CHANNELS

MSOP

PDIP

SOIC

TSSOP

SHUTDOWN

EVM BOARD

TLC070

1

8

8

8

Yes

TLC071

1

8

8

8

TLC072

2

8

8

8

Refer to the EVM

Selection Guide

TLC073

2

10

14

14

Yes

Selection Guide

(Lit# SLOU060)

TLC074

4

14

14

20

(Lit# SLOU060)

TLC075

4

16

16

20

Yes

Copyright 

©

 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

 

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

8

7

6

5

NULL

IN –

IN +

GND

SHDN

V

DD

OUT

NULL

TLC070

D, DGN OR P PACKAGE

(TOP VIEW)

PowerPAD is a trademark of Texas Instruments Incorporated.

background image

TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA

FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

OPERATIONAL AMPLIFIERS

 

SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TLC070 and TLC071 AVAILABLE OPTIONS

PACKAGED DEVICES

PACKAGED DEVICES

TA

SMALL OUTLINE

SMALL OUTLINE

SYMBOL

PLASTIC DIP

(D)†

(DGN)†

SYMBOL

(P)

0

°

C to 70

°

C

TLC070CD

TLC071CD

TLC070CDGN

TLC071CDGN

xxTIACS

xxTIACU

TLC070CP

TLC071CP

– 40

°

C to 125

°

C

TLC070ID

TLC071ID

TLC070IDGN

TLC071IDGN

xxTIACT

xxTIACV

TLC070IP

TLC071IP

– 40

°

C to 125

°

C

TLC070AID

TLC071AID

TLC070AIP

TLC071AIP

† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC070CDR).

‡ Chip forms are tested at TA = 25

°

C only.

TLC072 and TLC073 AVAILABLE OPTIONS

PACKAGED DEVICES

TA

SMALL

OUTLINE

MSOP

PLASTIC

DIP

PLASTIC

DIP

OUTLINE

(D)†

(DGN)†

SYMBOL§

(DGQ)†

SYMBOL§

DIP

(N)

DIP

(P)

0

°

C to 70

°

C

TLC072CD

TLC073CD

TLC072CDGN

xxTIADV

TLC073CDGQ

xxTIADX

TLC073CN

TLC072CP

– 40

°

C to 125

°

C

TLC072ID

TLC073ID

TLC072IDGN

xxTIADW

TLC073IDGQ

xxTIADY

TLC073IN

TLC072IP

– 40

°

C to 125

°

C

TLC072AID

TLC073AID

TLC073AIN

TLC072AIP

† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC072CDR).

‡ Chip forms are tested at TA = 25

°

C only.

§ xx represents the device date code.

TLC074 and TLC075 AVAILABLE OPTIONS

PACKAGED DEVICES

TA

SMALL OUTLINE

(D)†

PLASTIC DIP

(N)

TSSOP

(PWP)†

0

°

C to 70

°

C

TLC074CD

TLC075CD

TLC074CN

TLC075CN

TLC074CPWP

TLC075CPWP

– 40

°

C to 125

°

C

TLC074ID

TLC075ID

TLC074IN

TLC075IN

TLC074IPWP

TLC075IPWP

– 40

°

C to 125

°

C

TLC074AID

TLC075AID

TLC074AIN

TLC075AIN

TLC074AIPWP

TLC075AIPWP

† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g.,

TLC074CDR).

‡ Chip forms are tested at TA = 25

°

C only.

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TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA

FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

OPERATIONAL AMPLIFIERS

 

SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

3

POST OFFICE BOX 655303 

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TLC07x PACKAGE PINOUTS

NC – No internal connection

1

2

3

4

8

7

6

5

NULL

IN –

IN +

GND

SHDN

V

DD

OUT

NULL

TLC070

D, DGN OR P PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

NULL

IN –

IN +

GND

NC

V

DD

OUT

NULL

TLC071

D, DGN OR P PACKAGE

(TOP VIEW)

1

2

3

5

6

7

14

13

12

11

10

9

8

1OUT

1IN –

1IN+

GND

NC

1SHDN

NC

V

DD

2OUT

2IN –

2IN+

NC

2SHDN

NC

(TOP VIEW)

1

2

3

4

8

7

6

5

1OUT

1IN –

1IN +

GND

V

DD

2OUT

2IN –

2IN+

TLC072

D, DGN, OR P PACKAGE

(TOP VIEW)

TLC073

D OR N PACKAGE

1

2

3

5

6

7

8

16

15

14

13

12

11

10

9

1OUT

1IN –

1IN+

V

DD

2IN+

2IN –

2OUT

1/2SHDN

4OUT

4IN –

4IN+

GND

3IN +

3IN–

3OUT

3/4SHDN

(TOP VIEW)

TLC075

D OR N PACKAGE

1

2

3

5

6

7

14

13

12

11

10

9

8

1OUT

1IN –

1IN+

V

DD

2IN+

2IN –

2OUT

4OUT

4IN –

4IN+

GND

3IN+

3IN –

3OUT

(TOP VIEW)

TLC074

D OR N PACKAGE

1

2

3

4

5

10

9

8

7

6

1OUT

1IN –

1IN+

GND

1SHDN

V

DD

2OUT

2IN –

2IN+

2SHDN

TLC073

DGQ PACKAGE

(TOP VIEW)

1

2

3

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1OUT

1IN–

1IN+

VDD

2IN+

2IN–

2OUT

1/2SHDN

NC

NC

4OUT

4IN–

4IN+

GND

3IN+

3IN–

3OUT

3/4SHDN

NC

NC

(TOP VIEW)

TLC075

PWP PACKAGE

1

2

3

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

(TOP VIEW)

TLC074

PWP PACKAGE

1OUT

1IN–

1IN+

VDD

2IN+

2IN–

2OUT

NC

NC

NC

4OUT

4IN–

4IN+

GND

3IN+

3IN–

3OUT

NC

NC

NC

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TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA

FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

OPERATIONAL AMPLIFIERS

 

SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

4

POST OFFICE BOX 655303 

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

DD

 (see Note 1) 

17 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Differential input voltage, V

ID

 

 

±

V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous total power dissipation 

See Dissipation Rating Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

: C suffix 

0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

I suffix 

– 40

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Maximum junction temperature, T

J

 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

  – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 

260

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltage values, except differential voltages, are with respect to GND .

DISSIPATION RATING TABLE

PACKAGE

θ

JC

(

°

C/W)

θ

JA

(

°

C/W)

TA 

 25

°

C

POWER RATING

D (8)

38.3

176

710 mW

D (14)

26.9

122.3

1022 mW

D (16)

25.7

114.7

1090 mW

DGN (8)

4.7

52.7

2.37 W

DGQ (10)

4.7

52.3

2.39 W

N (14, 16)

32

78

1600 mW

P (8)

41

104

1200 mW

PWP (20)

1.40

26.1

4.79 W

recommended operating conditions

MIN

MAX

UNIT

Supply voltage VDD

Single supply

4.5

16

V

Supply voltage, VDD

Split supply

±

2.25

±

8

V

Common-mode input voltage range, VICR

+0.5

VDD–0.8

V

Operating free air temperature TA

C-suffix

0

70

°

C

Operating free-air temperature, TA

I-suffix

– 40

125

°

C

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TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA

FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

OPERATIONAL AMPLIFIERS

 

SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

5

POST OFFICE BOX 655303 

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electrical characteristics at specified free-air temperature, V

DD

 = 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

V

V

TLC070/1/2/3

25

°

C

60

1000

V

V

TLC070/1/2/3

Full range

1500

V

V

TLC070/1/2/3A

25

°

C

20

750

VIO

Input offset voltage

VDD = 5 V,

TLC070/1/2/3A

Full range

1000

µ

V

VIO

Input offset voltage

VDD = 5 V,

VIC = 2.5, 

TLC074/5

25

°

C

390

1900

µ

V

IC

VO = 2.5,

RS 50

TLC074/5

Full range

3000

RS = 50 

TLC074/5A

25

°

C

390

1400

TLC074/5A

Full range

2000

α

VIO

Temperature coefficient of input

1 2

µ

V/

°

C

α

VIO

offset voltage

1.2

µ

V/

°

C

V

V

25

°

C

0.7

50

IIO

Input offset current

VDD = 5 V

TLC07XC

Full range

100

pA

VDD = 5 V,

VIC = 2.5,

TLC07XI

Full range

700

IC

,

VO = 2.5,

R

50

25

°

C

1.5

50

IIB

Input bias current

RS = 50 

TLC07XC

Full range

100

pA

TLC07XI

Full range

700

VICR

Common-mode input voltage

CMRR > 70 dB,

RS = 50 

25

°

C

0.5

to

4.2

V

VICR

g

range

CMRR > 52 dB,

RS = 50 

Full range

0.5

to

4.2

V

IOH = 1 mA

25

°

C

4.1

4.3

IOH = – 1 mA

Full range

3.9

IOH = 20 mA

25

°

C

3.7

4

IOH = – 20 mA

Full range

3.5

VOH

High-level output voltage

VIC = 2.5 V

IOH = 35 mA

25

°

C

3.4

3.8

V

IOH = – 35 mA

Full range

3.2

25

°

C

3.2

3.6

IOH = – 50 mA

–40

°

C to

85

°

C

3

IOL = 1 mA

25

°

C

0.18

0.25

IOL = 1 mA

Full range

0.35

IOL = 20 mA

25

°

C

0.35

0.39

IOL = 20 mA

Full range

0.45

VOL

Low-level output voltage

VIC = 2.5 V

IOL = 35 mA

25

°

C

0.43

0.55

V

IOL = 35 mA

Full range

0.7

25

°

C

0.48

0.63

IOL = 50 mA

–40

°

C to

85

°

C

0.7

IOS

Short circuit output current

Sourcing

25

°

C

100

mA

IOS

Short-circuit output current

Sinking

25

°

C

100

mA

IO

Output current

VOH = 1.5 V from positive rail

25

°

C

57

mA

IO

Output current

VOL = 0.5 V from negative rail

25

°

C

55

mA

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

background image

TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA

FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

OPERATIONAL AMPLIFIERS

 

SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, V

DD

 = 5 V (unless otherwise noted)

(continued)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

AVD

Large-signal differential voltage

VO(PP) = 3 V

R

10 k

25

°

C

100

120

dB

AVD

g

g

g

amplification

VO(PP) = 3 V,

RL = 10 k

Full range

100

dB

ri(d)

Differential input resistance

25

°

C

1000

G

CIC

Common-mode input 

capacitance

f = 10 kHz

25

°

C

22.9

pF

zo

Closed-loop output impedance

f = 10 kHz,

AV = 10

25

°

C

0.25

CMRR

Common mode rejection ratio

VIC = 1 to 3 V

RS = 50

25

°

C

100

140

dB

CMRR

Common-mode rejection ratio

VIC = 1 to 3 V,

RS = 50

Full range

100

dB

kSVR

Supply voltage rejection ratio

VDD = 4.5 V to 16 V,

VIC = VDD /2,

25

°

C

95

130

dB

kSVR

y

g

j

(

VDD  /

VIO)

DD

,

No load

IC

DD

,

Full range

95

dB

IDD

Supply current 

VO = 2 5 V

No load

25

°

C

1.9

2.5

mA

IDD

y

(per channel)

VO = 2.5 V,

No load

Full range

3.5

mA

V(ON)

Turnon voltage level

Relative to GND

25

°

C

1.41

V

V(OFF)

Turnoff voltage level

Relative to GND

25

°

C

1.4

V

IDD(SHDN)

Supply current in shutdown

mode (per channel)

SHDN

1 45 V

25

°

C

125

200

µ

A

IDD(SHDN) mode (per channel)

(TLC070, TLC073, TLC075)

SHDN 

 1.45 V

Full range

250

µ

A

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

background image

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FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

OPERATIONAL AMPLIFIERS

 

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7

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 DALLAS, TEXAS 75265

operating characteristics at specified free-air temperature, V

DD

 = 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

SR+

Positive slew rate at unity gain

VO(PP) = 0.8 V,

CL = 50 pF,

25

°

C

10

16

V/

µ

s

SR+

Positive slew rate at unity gain

O(PP)

,

RL = 10 k

L

,

Full range

9.5

V/

µ

s

SR

Negative slew rate at unity gain

VO(PP) = 0.8 V,

CL = 50 pF,

25

°

C

12.5

19

V/

µ

s

SR–

Negative slew rate at unity gain

O(PP)

,

RL = 10 k

L

,

Full range

10

V/

µ

s

V

Equivalent input noise voltage

f = 100 Hz

25

°

C

12

nV/

Hz

Vn

Equivalent input noise voltage

f = 1 kHz

25

°

C

7

nV/

Hz

In

Equivalent input noise current

f = 1 kHz

25

°

C

0.6

fA /

Hz

VO(PP) = 3 V,

AV = 1

0.002%

THD + N

Total harmonic distortion plus noise

VO(PP) = 3 V,

RL = 10 k

 and 250 

,

AV = 10

25

°

C

0.012%

f = 1 kHz

AV = 100

0.085%

t(on)

Amplifier turnon time‡

RL = 10 k

25

°

C

0.15

µ

s

t(off)

Amplifier turnoff time‡

RL = 10 k

25

°

C

1.3

µ

s

Gain-bandwidth product

f = 10 kHz,

RL = 10 k

25

°

C

10

MHz

V(STEP)PP = 1 V,

AV = –1,

0.1%

0.18

t

Settling time

V

,

CL = 10 pF,

RL = 10 k

0.01%

25

°

C

0.39

µ

s

ts

Settling time

V(STEP)PP = 1 V,

AV = –1,

0.1%

25

°

C

0.18

µ

s

V

,

CL = 47 pF,

RL = 10 k

0.01%

0.39

φ

Phase margin

RL = 10 k

,

CL = 50 pF

25

°

C

32

°

φ

m

Phase margin

RL = 10 k

,

CL = 0 pF

25

°

C

40

°

Gain margin

RL = 10 k

,

CL = 50 pF

25

°

C

2.2

dB

Gain margin

RL = 10 k

,

CL = 0 pF

25

°

C

3.3

dB

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current

has reached half its final value.

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TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA

FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

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SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

8

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electrical characteristics at specified free-air temperature, V

DD

 = 12 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

V

12 V

TLC070/1/2/3

25

°

C

60

1000

V

12 V

TLC070/1/2/3

Full range

1500

V

12 V

TLC070/1/2/3A

25

°

C

20

750

VIO

Input offset voltage

VDD = 12 V

TLC070/1/2/3A

Full range

1000

µ

V

VIO

Input offset voltage

VDD = 12 V

VIC = 6, 

TLC074/5

25

°

C

390

1900

µ

V

IC

VO = 6,

RS 50

TLC074/5

Full range

3000

RS = 50 

TLC074/5A

25

°

C

390

1400

TLC074/5A

Full range

2000

α

VIO

Temperature coefficient of input

1 2

µ

V/

°

C

α

VIO

offset voltage

1.2

µ

V/

°

C

V

12 V

25

°

C

0.7

50

IIO

Input offset current

VDD = 12 V

TLC07xC

Full range

100

pA

VDD = 12 V

VIC = 6, 

TLC07xI

Full range

700

IC

,

VO = 6,

R

50

25

°

C

1.5

50

IIB

Input bias current

RS = 50 

TLC07xC

Full range

100

pA

TLC07xI

Full range

700

VICR

Common-mode input voltage

CMRR > 70 dB

RS = 50 

25

°

C

0.5

to

11.2

V

VICR

g

range

CMRR > 52 dB

RS = 50 

Full range

0.5

to

11.2

V

IOH = 1 mA

25

°

C

11.1

11.2

IOH = – 1 mA

Full range

11

IOH = 20 mA

25

°

C

10.8

10.9

IOH = – 20 mA

Full range

10.7

VOH

High-level output voltage

VIC = 6 V

IOH = 35 mA

25

°

C

10.6

10.7

V

IOH = – 35 mA

Full range

10.3

25

°

C

10.4

10.5

IOH = – 50 mA

–40

°

C to

85

°

C

10.3

IOL = 1 mA

25

°

C

0.17

0.25

IOL = 1 mA

Full range

0.35

IOL = 20 mA

25

°

C

0.35

0.45

IOL = 20 mA

Full range

0.5

VOL

Low-level output voltage

VIC = 6 V

IOL = 35 mA

25

°

C

0.4

0.52

V

IOL = 35 mA

Full range

0.6

25

°

C

0.45

0.6

IOL = 50 mA

–40

°

C to

85

°

C

0.65

IOS

Short circuit output current

Sourcing

25

°

C

150

mA

IOS

Short-circuit output current

Sinking

25

°

C

150

mA

IO

Output current

VOH = 1.5 V from positive rail

25

°

C

57

mA

IO

Output current

VOL = 0.5 V from negative rail

25

°

C

55

mA

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

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FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

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SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, V

DD

 = 12 V (unless otherwise noted)

(continued)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

AVD

Large-signal differential voltage

VO(PP) = 8 V

R

10 k

25

°

C

120

140

dB

AVD

g

g

g

amplification

VO(PP) = 8 V,

RL = 10 k

Full range

120

dB

ri(d)

Differential input resistance

25

°

C

1000

G

CIC

Common-mode input 

capacitance

f = 10 kHz

25

°

C

21.6

pF

zo

Closed-loop output impedance

f = 10 kHz,

AV = 10

25

°

C

0.25

CMRR

Common mode rejection ratio

VIC = 1 to 10 V

RS = 50

25

°

C

100

140

dB

CMRR

Common-mode rejection ratio

VIC = 1 to 10 V,

RS = 50

Full range

100

dB

kSVR

Supply voltage rejection ratio

VDD = 4.5 V to 16 V,

VIC = VDD /2,

25

°

C

95

130

dB

kSVR

y

g

j

(

VDD  /

VIO)

DD

,

No load

IC

DD

,

Full range

95

dB

IDD

Supply current 

VO = 7 5 V

No load

25

°

C

2.1

2.9

mA

IDD

y

(per channel)

VO = 7.5 V,

No load

Full range

3.5

mA

V(ON)

Turnon voltage level

Relative to GND

25

°

C

1.39

V

V(OFF)

Turnoff voltage level

Relative to GND

25

°

C

1.38

V

IDD(SHDN)

Supply current in shutdown

mode (TLC070 TLC073

SHDN

1 45 V

25

°

C

125

200

µ

A

IDD(SHDN) mode (TLC070, TLC073,

TLC075) (per channel)

SHDN 

 1.45 V

Full range

250

µ

A

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

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FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

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SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

operating characteristics at specified free-air temperature, V

DD

 = 12 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA†

MIN

TYP

MAX

UNIT

SR+

Positive slew rate at unity gain

VO(PP) = 2 V,

CL = 50 pF,

25

°

C

10

16

V/

µ

s

SR+

Positive slew rate at unity gain

O(PP)

,

RL = 10 k

L

,

Full range

9.5

V/

µ

s

SR

Negative slew rate at unity gain

VO(PP) = 2 V,

CL = 50 pF,

25

°

C

12.5

19

V/

µ

s

SR–

Negative slew rate at unity gain

O(PP)

,

RL = 10 k

L

,

Full range

10

V/

µ

s

V

Equivalent input noise voltage

f = 100 Hz

25

°

C

12

nV/

Hz

Vn

Equivalent input noise voltage

f = 1 kHz

25

°

C

7

nV/

Hz

In

Equivalent input noise current

f = 1 kHz

25

°

C

0.6

fA /

Hz

VO(PP) = 8 V,

AV = 1

0.002%

THD + N

Total harmonic distortion plus noise

VO(PP) = 8 V,

RL = 10 k

 and 250 

,

AV = 10

25

°

C

0.005%

f = 1 kHz

AV = 100

0.022%

t(on)

Amplifier turnon time‡

RL = 10 k

25

°

C

0.47

µ

s

t(off)

Amplifier turnoff time‡

RL = 10 k

25

°

C

2.5

µ

s

Gain-bandwidth product

f = 10 kHz,

RL = 10 k

25

°

C

10

MHz

V(STEP)PP = 1 V,

AV = –1,

0.1%

0.17

t

Settling time

V

,

CL = 10 pF,

RL = 10 k

0.01%

25

°

C

0.22

µ

s

ts

Settling time

V(STEP)PP = 1 V,

AV = –1,

0.1%

25

°

C

0.17

µ

s

V

,

CL = 47 pF,

RL = 10 k

0.01%

0.29

φ

Phase margin

RL = 10 k

,

CL = 50 pF

25

°

C

37

°

φ

m

Phase margin

RL = 10 k

,

CL = 0 pF

25

°

C

42

°

Gain margin

RL = 10 k

,

CL = 50 pF

25

°

C

3.1

dB

Gain margin

RL = 10 k

,

CL = 0 pF

25

°

C

4

dB

† Full range is 0

°

C to 70

°

C for C suffix and – 40

°

C to 125

°

C for I suffix. If not specified, full range is – 40

°

C to 125

°

C.

‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current

has reached half its final value.

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TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA

FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

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SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

11

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

VIO

Input offset voltage

vs Common-mode input voltage

1, 2

IIO

Input offset current

vs Free-air temperature

3, 4

IIB

Input bias current

vs Free-air temperature

3, 4

VOH

High-level output voltage

vs High-level output current

5, 7

VOL

Low-level output voltage

vs Low-level output current

6, 8

Zo

Output impedance

vs Frequency

9

IDD

Supply current

vs Supply voltage

10

PSRR

Power supply rejection ratio

vs Frequency

11

CMRR

Common-mode rejection ratio

vs Frequency

12

Vn

Equivalent input noise voltage

vs Frequency

13

VO(PP)

Peak-to-peak output voltage

vs Frequency

14, 15

Crosstalk

vs Frequency

16

Differential voltage gain

vs Frequency

17, 18

Phase

vs Frequency

17, 18

φ

m

Phase margin

vs Load capacitance

19, 20

Gain margin

vs Load capacitance

21, 22

Gain-bandwidth product

vs Supply voltage

23

SR

Slew rate

vs Supply voltage

vs Free-air temperature

24

25, 26

THD + N

Total harmonic distortion plus noise

vs Frequency

27, 28

THD + N

Total harmonic distortion plus noise

vs Peak-to-peak output voltage

29, 30

Large-signal follower pulse response

vs Time

31, 32

Small-signal follower pulse response

vs Time

33

Large-signal inverting pulse response

vs Time

34, 35

Small-signal inverting pulse response

vs Time

36

Shutdown forward isolation

vs Frequency

37, 38

Shutdown reverse isolation

vs Frequency

39, 40

Shutdown supply current

vs Supply voltage

41

Shutdown supply current

vs Free-air temperature

42

Shutdown pulse

43, 44

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FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

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SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

12

POST OFFICE BOX 655303 

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TYPICAL CHARACTERISTICS

Figure 1

INPUT OFFSET VOLTAGE

vs

COMMON-MODE INPUT VOLTAGE

100

75

50

25

0

–25

0.0 0.5 1.0 1.5 2.0 2.5 3.0

125

150

175

200

250

225

3.5 4.0 4.5 5.0

VICR – Common-Mode Input Voltage – V

VDD = 5 V

TA = 25

°

 C

V

IO

– Input Offset V

oltage –

V

µ

Figure 2

INPUT OFFSET VOLTAGE

vs

COMMON-MODE INPUT VOLTAGE

–150

–175

–200

–225

–250

–275

0

1

2

3

4

5

6

–125

–100

–75

–50

0

–25

7

8

9 10 11 12

VICR – Common-Mode Input Voltage – V

V

IO

– Input Offset V

oltage –

V

µ

VDD = 12 V

TA = 25

°

 C

Figure 3

INPUT BIAS CURRENT AND

INPUT OFFSET CURRENT

vs

FREE-AIR TEMPERATURE

–120

–55 –40

–80

–20

–10 5

TA – Free–Air Temperature – 

°

C

–40

–60

–100

–25

20 35 50

IIB

/

I

IO

Input Bias and Input Offset Current – pA

I

IB

VDD = 5V

65 80 95 110 125

0

20

IIO

Figure 4

INPUT BIAS CURRENT AND

INPUT OFFSET CURRENT

vs

FREE-AIR TEMPERATURE

–120

–55 –40

–80

–20

–10 5

TA – Free-Air Temperature – 

°

C

IIO

–40

–60

–100

–25

–140

–160

20 35 50

IIB

/

I

IO

Input Bias and Input Offset Current – pA

I

IB

VDD= 12V

65 80 95 110 125

0

20

Figure 5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0

5

10 15 20 25 30 35 40 45 50

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

IOH - High-Level Output Current - mA

VDD=5 V

V

OH

– High-Level Output V

oltage – V

TA= 125

°

C

TA= 70

°

C

TA= 25

°

C

TA= –40

°

C

Figure 6

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

5

10 15 20 25 30 35 40 45 50

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

IOL - Low-Level Output Current - mA

TA= 125

°

C

TA= 70

°

C

TA= 25

°

C

TA= –40

°

C

VDD=5 V

OL

V

 Low-Level Output V

oltage – V

Figure 7

9.0

9.5

10.0

10.5

11.0

11.5

12.0

0

5

10 15 20 25 30 35 40 45 50

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

IOH - High-Level Output Current - mA

TA= 125

°

C

TA= 70

°

C

TA= 25

°

C

TA= –40

°

C

V

OH

– High-Level Output V

oltage – V

VDD=12  V

Figure 8

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

5

10 15 20 25 30 35 40 45 50

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

IOL - Low-Level Output Current - mA

TA= 125

°

C

TA= 25

°

C

TA= –40

°

C

OL

V

 Low-Level Output V

oltage – V

VDD=12 V

TA= 70

°

C

Figure 9

OUTPUT IMPEDANCE

vs

FREQUENCY

f - Frequency - Hz

100k

1000

1M

10M

– Output Impedance –

Z

o

10k

100

1k

100

10

1

0.10

0.01

AV = 100

AV = 10

AV = 1

VDD=5 & 12 V

TA = 25

°

C

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FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

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SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

13

POST OFFICE BOX 655303 

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TYPICAL CHARACTERISTICS

Figure 10

0.0

0.5

1.0

1.5

2.0

2.5

3.0

4

5

6

7

8

9 10 11 12 13 14 15 16

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

VDD – Supply Voltage - V

AV = 1

SHDN = VDD

Per Channel

TA= 125

°

C

TA= 70

°

C

TA= 25

°

C

TA= –40

°

C

I

DD

– Supply Current – mA

Figure 11

POWER SUPPLY REJECTION RATIO

vs

FREQUENCY

40

0

10

80

140

1k

10k

f – Frequency – Hz

VDD = 12 V

120

100

60

100

20

0

Power Supply Rejection Ratio – dB

PSRR

100k

1M

10M

VDD = 5 V

0

20

40

60

80

100

120

140

Figure 12

COMMON-MODE REJECTION RATIO

vs

FREQUENCY

f - Frequency - Hz

100k

1M

10M

10k

100

1k

CMRR – Common-Mode Rejection Ratio – dB

VDD = 5 & 12 V

TA= 25

°

C

Figure 13

EQUIVALENT INPUT NOISE VOLTAGE

vs

FREQUENCY

0

10

100

10

25

10k

100k

f – Frequency – Hz

VDD = 5 V

40

VDD = 12 V

35

30

20

15

5

1k

nV/

Hz

– Equivalent Input Noise V

oltage –

V

n

Figure 14

0

2

4

6

8

10

12

PEAK-TO-PEAK OUTPUT

VOLTAGE

vs

FREQUENCY

f - Frequency - Hz

100k

1M

10M

10k

THD+N < =5%

RL=600 

TA = 25

°

C

VDD=12 V

VDD=5 V

V

O(PP)

– Peak-to-Peak Output V

oltage – V

Figure 15

0

2

4

6

8

10

12

PEAK-TO-PEAK OUTPUT

VOLTAGE

vs

FREQUENCY

f - Frequency - Hz

100k

1M

10M

10k

V

O(PP)

– Peak-to-Peak Output V

oltage – V

THD+N < =5%

RL=10 k

TA = 25

°

C

VDD=12 V

VDD=5 V

Figure 16

–120

10

100

–80

–20

10k

f – Frequency – Hz

0

–40

–60

–100

1k

–140

–160

Crosstalk – dB

100k

CROSSTALK

vs

FREQUENCY

VDD= 5V and 12 V

AV = 1

RL = 10 k

VI(PP) = 2V 

For All Channels

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FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY

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SLOS219B – JUNE 1999 – REVISED NOVEMBER 1999

14

POST OFFICE BOX 655303 

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TYPICAL CHARACTERISTICS

Figure 17

DIFFERENTIAL VOLTAGE GAIN AND

PHASE

vs

FREQUENCY

0

1k

10k

20

50

1M

10M

f – Frequency – Hz

Gain

80

70

60

40

30

10

100k

–10

–20

Different V

oltage Gain – dB

A

VD

100M

–180

–135

0

–45

–90

–225

Phase

VDD= 

±

2.5V

RL = 10 k

CL = 0pF 

TA = 25

°

C

Phase – 

°

Figure 18

DIFFERENTIAL VOLTAGE GAIN AND

PHASE

vs

FREQUENCY

0

1k

10k

20

50

1M

10M

f – Frequency – Hz

Gain

80

70

60

40

30

10

100k

–10

–20

Different V

oltage Gain – dB

A

VD

100M

–180

–135

0

–45

–90

–225

Phase

VDD = 

±

6V

RL = 10 k

CL = 0pF

TA = 25

°

C

Phase –

°

Figure 19

PHASE MARGIN

vs

LOAD CAPACITANCE

10

°

10

20

°

35

°

CL – Load Capacitance – pF

30

°

25

°

15

°

100

5

°

0

°

Rnull = 0 

Rnull = 20 

Rnull = 50 

Rnull = 100 

VDD = 5 V

RL = 10 k

TA = 25

°

C

40

°

m

φ

– Phase Margin

Figure 20

PHASE MARGIN

vs

LOAD CAPACITANCE

10

°

10

20

°

35

°

CL – Load Capacitance – pF

30

°

25

°

15

°

100

5

°

0

°

Rnull = 0 

Rnull = 20 

Rnull = 50 

Rnull = 100 

VDD = 12 V

RL = 10 k

TA = 25

°

C

40

°

45

°

m

φ

– Phase Margin

Figure 21

GAIN MARGIN

vs

LOAD CAPACITANCE

1

10

2

4

CL – Load Capacitance – pF

3.5

2.5

1.5

100

0.5

0

Gain Margin – dB

G

Rnull = 0 

Rnull = 20 

Rnull = 50 

Rnull = 100 

VDD = 5 V

RL = 10 k

TA = 25

°

C

3

Figure 22

GAIN MARGIN

vs

LOAD CAPACITANCE

1

10

2

3.5

CL – Load Capacitance – pF

3

2.5

1.5

100

0.5

0

Rnull = 0

 Ω

Rnull = 20

 Ω

Rnull = 50

 Ω

Rnull = 100

 Ω

VDD = 12 V

RL = 10k 

TA= 25

°

C

4

4.5

5

m

φ

– Phase Margin – dB

Figure 23

9.0

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

10.0

4

5

6

7

8

9 10 11 12 13 14 15 16

CL=11 pF

TA=25

°

C

GAIN BANDWIDTH PRODUCT

vs

SUPPLY VOLTAGE

VDD - Supply Voltage - V

GBWP

 - Gain Bandwidth Product - MHz

RL = 10 k

RL = 600 

Figure 24

12

13

14

15

16

17

18

19

20

21

22

4

5

6

7

8

9 10 11 12 13 14 15 16

SLEW RATE

vs

SUPPLY VOLTAGE

VDD - Supply Voltage - V

RL=600 

 & 10 k

CL = 50pF

AV = 1

SR – Slew Rate – V/

µ

s

Slew Rate +

Slew Rate –

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Figure 25

0

5

10

15

20

25

–55 –35 –15

5

25

45

65

85 105 125

SLEW RATE

vs

FREE-AIR TEMPERATURE

TA - Free-Air Temperature - 

°

C

VDD = 5 V

RL=600 

 & 10 k

CL = 50pF

AV = 1

SR – Slew Rate – V/

µ

s

Slew Rate +

Slew Rate –

Figure 26

0

5

10

15

20

25

–55 –35 –15

5

25

45

65

85 105 125

SLEW RATE

vs

FREE-AIR TEMPERATURE

TA - Free-Air Temperature - 

°

C

VDD = 12 V

RL=600 

 & 10 k

CL = 50pF

AV = 1

SR – Slew Rate – V/

µ

s

Slew Rate +

Slew Rate –

Figure 27

TOTAL HARMONIC DISTORTION

PLUS NOISE

vs

FREQUENCY

0.001

100

1k

0.01

0.1

10k

100k

f – Frequency – Hz

VDD = 5 V 

RL = 10 k

VO(PP) = 2 V

AV=100

AV=10

AV=1

1

T

otal Harmonic Distortion + Noise – %

Figure 28

TOTAL HARMONIC DISTORTION

PLUS NOISE

vs

FREQUENCY

T

otal Harmonic Distortion + Noise – %

0.001

100

1k

0.01

0.1

10k

100k

f – Frequency – Hz

AV=100

VDD = 12 V 

RL = 10 k

VO(PP) = 12 V

AV=10

AV=1

Figure 29

TOTAL HARMONIC DISTORTION

PLUS NOISE

vs

PEAK-TO-PEAK OUTPUT VOLTAGE

T

otal Harmonic Distortion + Noise – %

0.0001

0.25

0.75

0.01

0.1

1.25 1.75

VO(PP) – Peak-to-Peak Output Voltage – V

2.25

2.75

3.25 3.75

0.001

1

10

VDD = 5 V

AV = 1

f = 1 kHz

RL = 250 

RL = 600 

RL = 10 k

Figure 30

TOTAL HARMONIC DISTORTION

PLUS NOISE

vs

PEAK-TO-PEAK OUTPUT VOLTAGE

T

otal Harmonic Distortion + Noise – %

0.0001

0.5

2.5

0.01

0.1

4.5

6.5

VO(PP) – Peak-to-Peak Output Voltage – V

8.5

10.5

0.001

1

10

VDD = 12 V

AV = 1

f = 1 kHz

RL = 250 

RL = 600 

RL = 10 k

Figure 31

t – Time – 

µ

s

0

0.2 0.4 0.6 0.8

1

1.2

LARGE SIGNAL FOLLOWER

PULSE RESPONSE

vs

TIME

1.4 1.6 1.8

2

– Output V

oltage – V

V

O

VI (1 V/Div)

VO (500 mV/Div)

VDD = 5 V

RL = 600 

      & 10 k

CL = 8 pF

TA = 25

°

C

Figure 32

t – Time – 

µ

s

0

0.2 0.4 0.6 0.8

1

1.2

LARGE SIGNAL FOLLOWER

PULSE RESPONSE

vs

TIME

1.4 1.6 1.8

2

– Output V

oltage – V

V

O

VI (5 V/Div)

VO (2 V/Div)

VDD = 12 V

RL = 600 

       & 10 k

CL = 8 pF

TA = 25

°

C

Figure 33

SMALL SIGNAL FOLLOWER PULSE

RESPONSE

vs

TIME

0

0.1

0.3 0.4

t – Time – 

µ

s

0.2

0.5 0.6 0.7 0.8 0.9 0.10

VO(50mV/Div)

VI(100mV/Div)

VDD = 5 &12V

RL = 600 

Ω 

&10 k

CL = 8 pF

TA = 25

°

C

– Output V

oltage – V

V

O

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Figure 34

t – Time – 

µ

s

0

0.2 0.4 0.6 0.8

1

1.2

LARGE SIGNAL INVERTING

PULSE RESPONSE

vs

TIME

1.4 1.6 1.8

2

– Output V

oltage – V

V

O

VI (2 V/div)

VO (500 mV/Div)

VDD = 5 V

RL = 600 

 & 

         10 k

CL = 8 pF

TA = 25

°

C

Figure 35

t – Time – 

µ

s

0

0.2 0.4 0.6 0.8

1

1.2

LARGE SIGNAL INVERTING

PULSE RESPONSE

vs

TIME

1.4 1.6 1.8

2

– Output V

oltage – V

V

O

VI (5 V/div)

VO (2 V/Div)

VDD = 12 V

RL = 600 

 & 

         10 k

CL = 8 pF

TA = 25

°

C

Figure 36

t – Time – 

µ

s

0

0.1 0.2 0.3 0.4 0.5 0.6

SMALL SIGNAL INVERTING

PULSE RESPONSE

vs

TIME

0.7 0.8 0.9

1

– Output V

oltage – V

V

O

VI (100 mV/div)

VO (50 mV/Div)

VDD = 5 & 12 V

RL = 600 

 & 10 k

CL = 8 pF

TA = 25

°

C

Figure 37

20

40

60

80

100

120

140

SHUTDOWN FORWARD

ISOLATION

vs

FREQUENCY

f - Frequency - Hz

100k

1M

10M

10k

100

1k

Sutdown Forward Isolation - dB

100M

VDD = 5 V

CL= 0 pF

TA = 25

°

C

VI(PP)=0.1, 2.5, and 5

RL = 600 

RL = 10 k

Figure 38

20

40

60

80

100

120

140

SHUTDOWN FORWARD

ISOLATION

vs

FREQUENCY

f - Frequency - Hz

100k

1M

10M

10k

100

1k

Sutdown Forward Isolation - dB

100M

VDD = 12 V

CL= 0 pF

TA = 25

°

C

VI(PP)=0.1, 8, and 12

RL = 600 

RL = 10 k

Figure 39

20

40

60

80

100

120

140

SHUTDOWN REVERSE

ISOLATION

vs

FREQUENCY

f - Frequency - Hz

100k

1M

10M

10k

100

1k

Sutdown Reverse Isolation - dB

100M

RL = 600 

RL = 10 k

VDD = 5 V

CL= 0 pF

TA = 25

°

C

VI(PP)=0.1, 2.5, and 5

Figure 40

20

40

60

80

100

120

140

SHUTDOWN REVERSE

ISOLATION

vs

FREQUENCY

f - Frequency - Hz

100k

1M

10M

10k

100

1k

Sutdown Reverse Isolation - dB

100M

VDD = 12 V

CL= 0 pF

TA = 25

°

C

VI(PP)=0.1, 8, and 12

RL = 600 

RL = 10 k

Figure 41

118

120

122

124

126

128

130

132

134

136

4

5

6

7

8

9 10 11 12 13 14 15 16

SHUTDOWN SUPPLY CURRENT

vs

SUPPLY VOLTAGE

VDD - Supply Voltage - V

I DD(SHDN)

– Shutdown Supply Current -

A

µ

Shutdown On

RL = open

VIN = VDD/2

Figure 42

60

80

100

120

140

160

180

–55

–25

5

35

65

95

125

SHUTDOWN SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

TA - Free-Air Temperature - 

°

C

VDD=12 V

AV = 1

VIN=VDD/2

I DD(SHDN)

– Shutdown Supply Current -

A

µ

VDD=5 V

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Figure 43

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0

10

20

30

40

50

60

70

80

–2

–4

2

6

t - Time - 

µ

s

0

–6

4

Shutdown Pulse

SD Off

VDD = 5 V

CL= 8 pF

TA = 25

°

C

IDD RL = 600 

IDD RL = 10 k

I

DD

– Supply Current – mA

Shutdown Pulse - V

SHUTDOWN PULSE

Figure 44

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0

10

20

30

40

50

60

70

80

–2

–4

2

6

t - Time - 

µ

s

0

–6

4

Shutdown Pulse

SD Off

VDD = 12 V

CL= 8 pF

TA = 25

°

C

IDD RL = 600 

IDD RL = 10 k

I

DD

– Supply Current – mA

Shutdown Pulse - V

SHUTDOWN PULSE

PARAMETER MEASUREMENT INFORMATION

_

+

Rnull

RL

CL

Figure 45

APPLICATION INFORMATION

input offset voltage null circuit

The TLC070 and TLC071 has an input offset nulling function. Refer to Figure 46 for the diagram.

N1

100 k

+

N2

R1

VDD –

OUT

IN –

IN +

NOTE A: If R1 = 5.6 k

 for offset voltage adjustment of 

±

10 mV.

If R1 = 20 k

 for offset voltage adjustment of 

±

3 mV.

Figure 46. Input Offset Voltage Null Circuit

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APPLICATION INFORMATION

driving a capacitive load

When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the

device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater

than 10 pF, it is recommended that a resistor be placed in series (R

NULL

) with the output of the amplifier, as

shown in Figure 47. A minimum value of 20 

 should work well for most applications.

CLOAD

RF

Input

Output

RG

RNULL

_

+

Figure 47. Driving a Capacitive Load

offset voltage

The output offset voltage, (V

OO

) is the sum of the input offset voltage (V

IO

) and both input bias currents (I

IB

) times

the corresponding gains. The following schematic and formula can be used to calculate the output offset

voltage:

V

OO

+

V

IO

ǒ

1

)

ǒ

R

F

R

G

Ǔ

Ǔ

"

I

IB

)

R

S

ǒ

1

)

ǒ

R

F

R

G

Ǔ

Ǔ

"

I

IB–

R

F

+

VI

+

RG

RS

RF

IIB–

VO

IIB+

Figure 48. Output Offset Voltage Model

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APPLICATION INFORMATION

high speed CMOS input amplifiers

The TLC07x is a family of high-speed low-noise CMOS input operational amplifiers and has an input

capacitance of the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function

equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance.

For example, a gain of –10, source resistance of 1 k

 and a feedback resistance of 10 k

 adds an additional

pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their

greater input capacitance.

This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their

unity-gain bandwidth. However, the TLC07x with its 10-MHz bandwidth means that this pole normally occurs

at frequencies where there is on the order of 5 dB gain left and the phase shift adds considerably.

The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the

feedback resistance is increased, the gain peaking increases at a lower frequency and the 180

_

 phase shift

crossover point also moves down in frequency, decreasing the phase margin.

For the TLC07x, the maximum feedback resistor recommended is 5 k

, larger resistances can be used but a

capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance

pole.

The TLC073 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when

configured as a unity gain buffer and with a 10-k

 feedback resistor. By adding a 10-pF capacitor in parallel with

the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much

faster settling time (see Figure 49). The 10-pF capacitor was chosen for convenience only.

Load capacitance had little effect on these measurements due to the excellent output drive capability of the

TLC07x.

_

+

600 

22 pF

50 

10 k

10 pF

IN

With 

CF = 10 pF

VDD = 

±

5 V

AV = +1

RF = 10 k

RL = 600 

CL = 22 pF

V

I

– Input V

oltage – V

0

0.5

1

1.5

1

0

–1

2

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6

– Output V

oltage – V

V

O

t - Time - 

µ

s

VIN

VOUT

–0.5

Figure 49. 1-V Step Response

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general configurations

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often

required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifer

(see Figure 50).

VI

VO

C1

+

RG

RF

R1

f

–3dB

+

1

2

p

R1C1

V

O

V

I

+

ǒ

1

)

R

F

R

G

Ǔ

ǒ

1

1

)

sR1C1

Ǔ

Figure 50. Single-Pole Low-Pass Filter

If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this

task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.

Failure to do this can result in phase shift of the amplifier.

VI

C2

R2

R1

C1

RF

RG

R1 = R2 = R

C1 = C2 = C

Q = Peaking Factor

(Butterworth Q = 0.707)

(

=

1

Q

2 –

)

RG

RF

_

+

f

–3dB

+

1

2

p

RC

Figure 51. 2-Pole Low-Pass Sallen-Key Filter

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APPLICATION INFORMATION

shutdown function

Three members of the TLC07x family (TLC070/3/5) have a shutdown terminal (SHDN) for conserving battery

life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 16

nA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the

amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left

floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not

inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always

referenced to V

DD

/2. Therefore, when operating the device with split supply voltages (e.g. 

±

2.5 V), the shutdown

terminal needs to be pulled to V

DD

– (not GND) to disable the operational amplifier.

The amplifier’s output with a shutdown pulse is shown in Figures 43 and 44. The amplifier is powered with a

single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are

measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the

single, dual, and quad are listed in the data tables.

Figures 37, 38, 39, and 40 show the amplifier’s forward and reverse isolation in shutdown. The operational

amplifier is configured as a voltage follower (A

V

 = 1). The isolation performance is plotted across frequency

using 0.1 V

PP

, 2.5 V

PP

, and 5 V

PP

 input signals at 

±

2.5 V supplies and 0.1 V

PP

, 8 V

PP

, and 12 V

PP

 input signals

at 

±

6 V supplies.

circuit layout considerations

To achieve the levels of high performance of the TLC07x, follow proper printed-circuit board design techniques.

A general set of guidelines is given in the following.

D

Ground planes – It is highly recommended that a ground plane be used on the board to provide all

components with a low inductive ground connection. However, in the areas of the amplifier inputs and

output, the ground plane can be removed to minimize the stray capacitance.

D

Proper power supply decoupling – Use a 6.8-

µ

F tantalum capacitor in parallel with  a 0.1-

µ

F ceramic

capacitor on each supply terminal.  It may be possible to share the tantalum among several amplifiers

depending on the application, but a 0.1-

µ

F ceramic capacitor should always be used on the supply terminal

of every amplifier.  In addition, the 0.1-

µ

F capacitor should be placed as close as possible to the supply

terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less

effective. The designer should strive for distances of less than 0.1 inches between the device power

terminals and the ceramic capacitors.

D

Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins

will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board

is the best implementation.

D

Short trace runs/compact part placements – Optimum high performance is achieved when stray series

inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,

thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of

the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at

the input of the amplifier.

D

Surface-mount passive components – Using surface-mount passive components is recommended for high

performance amplifier circuits for several reasons.  First, because of the extremely low lead inductance of

surface-mount components, the problem with stray series inductance is greatly reduced.   Second, the small

size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray

inductance and capacitance.  If leaded components are used, it is recommended that the lead lengths be

kept as short as possible.

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APPLICATION INFORMATION

general PowerPAD

 design considerations

The TLC07x is available in a thermally-enhanced PowerPAD family of packages. These packages are

constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This

arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see

Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance

can be achieved by providing a good thermal path away from the thermal pad.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.

During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be

soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,

heat can be conducted away from the package into either a ground plane or other heat dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of

surface mount with the, heretofore, awkward mechanical methods of heatsinking.

DIE

Side View (a)

End View (b)

Bottom View (c)

DIE

Thermal

Pad

NOTE B: The thermal pad is electrically isolated from all terminals in the package.

Figure 52. Views of Thermally Enhanced DGN Package

Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the

recommended approach.

68 mils x 70 mils) with 5 vias

(Via diameter = 13 mils

78 mils x 94 mils) with 9 vias

(Via diameter = 13 mils)

Thermal Pad Area

Single or Dual

Quad

Figure 53. PowerPAD PCB Etch and Via Pattern

PowerPAD is a trademark of Texas Instruments Incorporated.

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general PowerPAD design considerations (continued)

1.

Prepare the PCB with a top side etch pattern as shown in Figure 53. There should be etch for the leads as

well as etch for the thermal pad.

2.

Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils

in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.

3.

Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps

dissipate the heat generated by the TLC07x IC. These additional vias may be larger than the 13-mil

diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad

area to be soldered so that wicking is not a problem.

4.

Connect all holes to the internal ground plane.

5.

When connecting these holes to the ground plane, do not use the typical web or spoke via connection

methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat

transfer during soldering operations. This makes the soldering of vias that have plane connections easier.

In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,

the holes under the TLC07x PowerPAD package should make their connection to the internal ground plane

with a complete connection around the entire circumference of the plated-through hole.

6.

The top-side solder mask should leave the terminals of the package and the thermal pad area with its five

holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes

of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the

reflow process.

7.

Apply solder paste to the exposed thermal pad area and all of the IC terminals.

8.

With these preparatory steps in place, the TLC07x IC is simply placed in position and run through the solder

reflow operation as any standard surface-mount component. This results in a part that is properly installed.

For a given 

θ

JA

, the maximum power dissipation is shown in Figure 54 and is calculated by the following formula:

P

D

+

ǒ

T

MAX

–T

A

q

JA

Ǔ

Where:

P

D

= Maximum power dissipation of TLC07x IC (watts)

T

MAX

= Absolute maximum junction temperature (150

°

C)

T

A

= Free-ambient air temperature (

°

C)

θ

JA

θ

JC 

+

 

θ

CA

θ

JC

= Thermal coefficient from junction to case

θ

CA

= Thermal coefficient from case to ambient air (

°

C/W)

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APPLICATION INFORMATION

general PowerPAD design considerations (continued)

TJ  = 150

°

C

4

3

2

0

–55 –40

–10

20 35

Maximum Power Dissipation – W

5

6

MAXIMUM POWER DISSIPATION

vs

FREE-AIR TEMPERATURE

7

65

95

125

1

TA – Free-Air Temperature – 

°

C

DGN Package

Low-K Test PCB

θ

JA = 52.3

°

C/W

SOT-23 Package

Low-K Test PCB

θ

JA = 324

°

C/W

–25

5

50

80

110

PWP Package

Low-K Test PCB

θ

JA = 29.7

°

C/W

SOIC Package

Low-K Test PCB

θ

JA = 176

°

C/W

PDIP Package

Low-K Test PCB

θ

JA = 104

°

C/W

NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.

Figure 54. Maximum Power Dissipation vs Free-Air Temperature

The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent

power and output power. The designer should never forget about the quiescent heat generated within the

device, especially muti-amplifier devices. Because these devices have linear output stages (Class A-B), most

of the heat dissipation is at low output voltages with high output currents.

The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The

PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a

copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other

hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around

the device, 

θ

JA

 decreases and the heat dissipation capability increases. The currents and voltages shown in

these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output

currents and voltages should be used to choose the proper package.

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APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using Microsim

Parts

, the model generation software used

with Microsim

 PSpice

. The Boyle macromodel (see Note 1) and subcircuit in Figure 55 are generated using

the TLC07x typical electrical and operating characteristics at T

A

 = 25

°

C. Using this information, output

simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

D

Maximum positive output voltage swing

D

Maximum negative output voltage swing

D

Slew rate

D

Quiescent power dissipation

D

Input bias current

D

Open-loop voltage amplification

D

Unity-gain frequency

D

Common-mode rejection ratio

D

Phase margin

D

DC output resistance

D

AC output resistance

D

Short-circuit output current limit

NOTE  1: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” 

IEEE Journal

of Solid-State Circuits, SC-9, 353 (1974).

PSpice and Parts are trademarks of MicroSim Corporation.

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APPLICATION INFORMATION

OUT

+

+

+

+

+

+

+

+

+

*DEVICE=TLC07X,OPAMP,NPN,INT

* TLC07X operational amplifier ”macromodel” subcircuit

* created using Parts release 8.0 on 06/21/99 at 17:12

* Parts is a MicroSim product.

*

* connections:   non–inverting input

*                                inverting input

*                                   positive power supply

*                                      negative power supply

*                                          output

*                                          

.subckt TLC07X–X 1 2 3 4 5

*

  c1   11 12 4.8697E–12

  c2    6  7 8.0000E–12

  cee  10 99 4.0063E–12

  dc    5 53 dy

  de   54  5 dy

  dlp  90 91 dx

  dln  92 90 dx

  dp    4  3 dx

  egnd 99  0 poly(2) (3,0) (4,0) 0 .5 .5

  fb    7 99 poly(5) vb vc ve vlp vln 0 6.9134E6 –1E3 1E3 

  +6E6 –6E6

  ga    6  0 11 12 457.42E–6

  gcm   0  6 10 99 1.1293E–6

  iee  10  4 dc 183.67E–6

  ioff 0 6 dc .95E–6

  hlim 90  0 vlim 1K

  q1   11  2 13 qx1

  q2   12  1 14 qx2

  r2    6  9 100.00E3

  rc1   3 11 2.1862E3

  rc2   3 12 2.1862E3

  re1  13 10 1.9046E3

  re2  14 10 1.9046E3

  ree  10 99 1.0889E6

  ro1   8  5 10

  ro2   7 99 10

  rp    3  4 2.7199E3

  vb    9  0 dc 0

  vc    3 53 dc 1.5410

  ve   54  4 dc .84403

  vlim  7  8 dc 0

  vlp  91  0 dc 119

  vln   0 92 dc 119

.model dx D(Is=800.00E–18)

.model dy D(Is=800.00E–18 Rs=1m Cjo=10p)

.model qx1 NPN(Is=800.00E–18 Bf=390.79E6)

.model qx2 NPN(Is=800.0000E–18 Bf=390.79E6)

.ends

*$

VDD +

RP

IN –

2

IN +

1

VDD –

VAD

RD1

11

J1

J2

10

RSS

ISS

3

12

RD2

60

VE

54

DE

DP

VC

DC

4

C1

53

R2

6

9

EGND

VB

FB

C2

GCM

GA

VLIM

8

5

RO1

RO2

HLIM

90

DLP

91

DLN

92

VLN

VLP

99

7

Figure 55. Boyle Macromodel and Subcircuit

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MECHANICAL DATA

D (R-PDSO-G**)    

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047 / D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A  MIN

A  MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0

°

– 8

°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

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MECHANICAL INFORMATION

DGN (S-PDSO-G8)    

PowerPAD

 PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

Thermal Pad

(See Note D)

0,15 NOM

Gage Plane

4073271/A 04/98

4,98

0,25

5

3,05

4,78

2,95

8

4

3,05

2,95

1

0,38

0,15

0,05

1,07 MAX

Seating Plane

0,10

0,65

M

0,25

0

°

– 6

°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions include mold flash or protrusions.

D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. 

This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal

pad is 68 mils (height as illustrated) 

×

 70 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package.

E. Falls within JEDEC MO-187

PowerPAD is a trademark of Texas Instruments Incorporated.

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MECHANICAL INFORMATION

DGQ (S-PDSO-G10)    

PowerPAD

 PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

Thermal Pad

(See Note D)

0,15 NOM

Gage Plane

4073273/A 04/98

4,98

0,17

6

3,05

4,78

2,95

10

5

3,05

2,95

1

0,27

0,15

0,05

1,07 MAX

Seating Plane

0,10

0,50

M

0,25

0

°

– 6

°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. 

This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal

pad is 68 mils (height as illustrated) 

×

 70 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package.

PowerPAD is a trademark of Texas Instruments Incorporated.

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MECHANICAL INFORMATION

N (R-PDIP-T**)   

PLASTIC DUAL-IN-LINE PACKAGE

20

0.975

(24,77)

0.940

(23,88)

18

0.920

0.850

14

0.775

0.745

(19,69)

(18,92)

16

0.775

(19,69)

(18,92)

0.745

A  MIN

DIM

A  MAX

PINS **

0.310 (7,87)

0.290 (7,37)

(23.37)

(21.59)

Seating Plane

0.010 (0,25) NOM

14/18 PIN ONLY

4040049/C 08/95

9

8

0.070 (1,78) MAX

A

0.035 (0,89) MAX

0.020 (0,51) MIN

16

1

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

M

0.010 (0,25)

0.100 (2,54)

0

°

– 15

°

16 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

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MECHANICAL INFORMATION

P (R-PDIP-T8)  

PLASTIC DUAL-IN-LINE PACKAGE

4040082 / B 03/95

0.310 (7,87)

0.290 (7,37)

0.010 (0,25) NOM

0.400 (10,60)

0.355 (9,02)

5

8

4

1

0.020 (0,51) MIN

0.070 (1,78) MAX

0.240 (6,10)

0.260 (6,60)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.015 (0,38)

0.021 (0,53)

Seating Plane

M

0.010 (0,25)

0.100 (2,54)

0

°

– 15

°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

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MECHANICAL INFORMATION

PWP (R-PDSO-G**)

PowerPAD

 PLASTIC SMALL-OUTLINE

4073225/F 10/98

0,50

0,75

0,25

0,15 NOM

Thermal Pad

(See Note D)

Gage Plane

28

24

7,70

7,90

20

6,40

6,60

9,60

9,80

6,60

6,20

11

0,19

4,50

4,30

10

0,15

20

A

1

0,30

1,20 MAX

16

14

5,10

4,90

PINS **

4,90

5,10

DIM

A  MIN

A  MAX

0,05

Seating Plane

0,65

0,10

M

0,10

0

°

– 8

°

20 PINS SHOWN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusions.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal

pad is 78 mils (height as illustrated) 

×

 94 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package.

E. Falls within JEDEC MO-153

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

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APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

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BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1999, Texas Instruments Incorporated