background image

TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Extremely Efficient Class-D Stereo

Operation

D

Drives L and R Channels, Plus Stereo

Headphones

D

10-W BTL Output Into 4 

 From 12 V

D

32-W Peak Music Power

D

Fully Specified for 12-V Operation

D

Low Shutdown Current

D

Class-AB Headphone Amplifier

D

Thermally-Enhanced PowerPAD

 Surface-

Mount Packaging

D

Thermal and Under-Voltage Protection

     

description

The TPA032D04 is a monolithic power IC stereo

audio amplifier that operates in extremely efficient

Class-D operation, using the high switching speed

of power DMOS transistors to replicate the analog

input signal through high-frequency switching of

the output stage. This allows the TPA032D04 to

be configured as a bridge-tied load (BTL) amplifier

capable of delivering up to 10 W of continuous

average power into a 4-

 load at 0.5% THD+N

from a 12-V power supply in the high-fidelity audio

frequency range (20 Hz to 20 kHz). A BTL

configuration eliminates the need for external

coupling capacitors on the output. Included is a Class-AB headphone amplifier with interface logic to select

between the two modes of operation. Only one amplifier is active at any given time, and the other is in

power-saving sleep mode. Also, a chip-level shutdown control is provided to limit total supply current to 20 

µ

A,

making the device ideal for battery-powered applications.

The output stage is compatible with a range of power supplies from 8 V to 14 V. Protection circuitry is included

to increase device reliability: thermal and under-voltage shutdown, with a status feedback terminal for use when

any error condition is encountered.

The high switching frequency of the TPA032D04 allows the output filter to consist of three small capacitors and

two small inductors per channel. The high switching frequency also allows for good THD+N performance.

The TPA032D04 is offered in the thermally enhanced 48-pin PowerPAD TSSOP surface-mount package

(designator DCA).

Copyright 

©

 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

 

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments Incorporated.

SHUTDOWN

MUTE

MODE

LINN

LINP

LCOMP

AGND

V

DD

LPV

DD

LOUTP

LOUTP

PGND

PGND

LOUTN

LOUTN

LPV

DD

HPREG

HPLOUT

HPLIN

AGND

PV

DD

VCP

HPDL

CP1

COSC

AGND

AGND

RINN

RINP

RCOMP

FAULT0

FAULT1

RPV

DD

ROUTP

ROUTP

PGND

PGND

ROUTN

ROUTN

RPV

DD

HPV

CC

HPROUT

HPRIN

V2P5

PV

DD

PGND

HPDR

CP2

1

2

3

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DCA PACKAGE

(TOP VIEW)

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TP

A032D04

10-W STEREO CLASS-D 

AUDIO POWER 

AMPLIFIER

SLOS203A

 – DECEMBER 1999 – REVISED MARCH 2000

T

emp

late 

R

e

lease 

D

ate: 

7

11

94

2

POST

 OFFICE BOX 655303     DALLAS, 

TEXAS 

75265

_

+

_

+

LINP

RAMP

GENERATOR

_

+

_

+

GATE

DRIVE

LPVDD

GATE

DRIVE

LPVDD

GATE

DRIVE

RPVDD

GATE

DRIVE

RPVDD

THERMAL

DETECT

VCP-UVLO

DETECT

DOUBLER

CHARGE PUMP

_

+

_

+

CONTROL and

STARTUP

LOGIC

5-V

REGULATOR

and BIASES

HPVCC

PVDD

LINN

LCOMP

COSC

RCOMP

RINP

RINN

RPVDD

AGND

LPVDD

ROUTP

ROUTN

PV

DD

VCP

CP2

CP1

LOUTP

LOUTN

F

AUL

T0

F

AUL

T1

SHUTDOWN

MODE

MUTE

HPREG

V2P5

HPLIN

HPLOUT

HPVCC

HPROUT

HPRIN

LPVDD

RPVDD

PGND

VCP

PVDD

VCP

PVDD

VCP

PVDD

VCP

PVDD

VDD

VDD

10 k

10 k

1.5 V

10 k

10 k

1.5 V

HP

DEPOP

HPDL

HPDR

NOTE A: LPVDD, RPVDD, and PVDD are externally connected. AGND and PGND are externally connected.

schematic

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.

DESCRIPTION

AGND

7, 20,

46, 47

Analog ground for headphone and Class-D analog sections

COSC

48

Connect a capacitor from analog ground to this terminal to set the frequency of the ramp reference signal.

CP1

24

First diode node for charge pump

CP2

25

First inverter switching node for charge pump

FAULT0

42

Logic level fault0 output signal. Lower order bit of the two fault signals with open drain output.

FAULT1

41

Logic level fault1 output signal. Higher order bit of the two fault signals with open drain output.

HPDL

23

Depop control for left headphone

HPDR

26

Depop control for right headphone

HPLIN

19

Headphone amplifier left input

HPLOUT

18

Headphone amplifier left output

HPREG

17

5-V regulator output. This terminal requires a 1-

µ

F capacitor to ground for stability reasons.

HPRIN

30

Headphone amplifier right input

HPROUT

31

Headphone amplifier right output

HPVCC

32

5V supply to headphone amplifier and logic. This terminal is typically connected to HPREG.

LCOMP

6

Compensation capacitor terminal for left-channel Class-D amplifier

LINN

4

Class-D left-channel negative input

LINP

5

Class-D left-channel positive input

LOUTN

14, 15

Class-D amplifier left-channel negative output of H-bridge

LOUTP

10, 11

Class-D amplifier left-channel positive output of H-bridge

LPVDD

9, 16

Class-D amplifier left-channel power supply

MODE

3

TTL logic-level mode input signal. When MODE is held low, the main Class-D amplifier is active. When MODE is

held > high, the head phone amplifier is active.

MUTE

2

Active-low TTL logic-level mute input signal. When MUTE is held low, the selected amplifier is muted. When MUTE

is held > high, the device operates normally. When the Class-D amplifier is muted, the low-side output transistors

are turned on, shorting the load to ground.

PGND

12, 13

Power ground for left-channel H–bridge only

PGND

27

Power ground for charge pump only

PGND

36, 37

Power ground for right-channel H-bridge only

PVDD

21, 28

VDD supply for charge-pump, headphone regulator, and gate drive circuitry

RCOMP

43

Compensation capacitor terminal for right-channel Class-D amplifier

RINN

45

Class-D right-channel negative input

RINP

44

Class-D right-channel positive input

RPVDD

33, 40

Class-D amplifier right-channel power supply

ROUTN

34, 35

Class-D amplifier right-channel negative output of H-bridge

ROUTP

38, 39

Class-D amplifier right-channel positive output of H-bridge

SHUTDOWN

1

Active-low TTL logic-level shutdown input signal. When SHUTDOWN is held low, the device goes into shutdown

mode. When SHUTDOWN is held high, the device operates normally.

V2P5

29

2.5V internal reference bypass. This terminal requires a capacitor to ground.

VCP

22

Connect a capacitor from this terminal to power ground to provide storage for the charge pump output voltage.

VDD

8

VDD bias supply for analog circuitry. This terminal needs to be well filtered to prevent degrading the device

performance.

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Class-D amplifier faults

Table 1. Class-D Amplifier Fault Table

FAULT 0

FAULT 1

DESCRIPTION

1

1

No fault. The device is operating normally.

0

1

Charge pump under-voltage lock-out (VCP-UV) fault. All low-side transistors are turned on, shorting the load to

ground. Once the charge pump voltage is restored, normal operation resumes, but FAULT1 is still active. This is not

a latched fault, however. FAULT1 is cleared by cycling MUTE, SHUTDOWN, or the power supply.

0

0

Thermal fault. All the low-side transistors are turned on, shorting the load to ground. Once the junction temperature

drops 20

°

C, normal operation resumes (not a latched fault). But the FAULTx terminals are still set and are cleared

by cycling MUTE, SHUTDOWN, or the power supply.

headphone amplifier faults

The thermal fault remains active when the device is in head phone mode. This fault operation has exactly the

same as it does for the Class-D amplifier (see Table 1).

If HPV

CC

 drops below approximately 4.5 V, the head phone is disabled. Once HPV

CC

 exceeds approximately

4.5 V, the head phone amplifier is re-enabled. No fault is reported to the user.

AVAILABLE OPTIONS

PACKAGED DEVICES

TA

TSSOP†

(DCA)

– 40

°

C to 125

°

C

TPA032D04DCA

† The DCA package is available in left-ended tape and reel. To order

a taped and reeled part, add the suffix R to the part number (e.g.,

TPA032D04DCAR).

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range, T

C

 = 25

°

C (unless otherwise

noted)

Supply voltage, (V

DD

, PV

DD

, LPV

DD

, RPV

DD

) 14 

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Headphone supply voltage, (HPV

CC

) 5.5 

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage, V

I

 (MUTE, MODE, SHUTDOWN) 

– 0.3 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output current, I

O

 (FAULT0, FAULT1), open drain terminated 

1 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Supply/load voltage, (FAULT0, FAULT1) 

7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Charge pump voltage, V

CP

 PV

DD

 + 20 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous H-bridge output current (1 H-bridge conducting) 

3.5 A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Pulsed H-Bridge output current, each output, I

max

 (see Note 1) 

7 A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous HPREG output current, I

O

 (HPREG) 

150 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous total power dissipation, T

C

 = 25

°

See Dissipation Rating Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating virtual junction temperature range, T

J

  – 40

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating case temperature range, T

C

  – 40

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

  – 65

°

C to 260

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 

260

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Pulse duration = 10 ms, duty cycle 

v

 2%

DISSIPATION RATING TABLE

PACKAGE

TA 

 25

°

C‡

POWER RATING

DERATING FACTOR

ABOVE TA = 25

°

C

TA = 70

°

C

POWER RATING

TA = 85

°

C

POWER RATING

DCA

5.6 W

44.8 mW/

°

C

3.6 W

2.9 W

‡ Please see the Texas Instruments document, PowerPAD Thermally Enhanced Package Application

Report (literature number SLMA002), for more information on the PowerPAD package. The thermal data

was measured on a PCB layout based on the information in the section entitled 

Texas Instruments

Recommended Board for PowerPAD on page 33 of the before mentioned document.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VDD, PVDD, LPVDD, RPVDD

8

14

V

Headphone supply voltage, HPVCC

4.5

5.5

V

High-level input voltage, VIH (MUTE, MODE, SHUTDOWN)

2

VDD + 0.3 V

V

Low-level input voltage, VIL (MUTE, MODE, SHUTDOWN)

– 0.3

0.8

V

Audio inputs, LINN, LINP, RINN, RINP, HPLIN, HPRIN, differential input voltage

1

VRMS

PWM frequency

100

250

500

kHZ

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics Class-D amplifier, V

DD

 = PV

DD

 = LPV

DD

 = RPV

DD

 = 12 V, R

L

 = 4 

 to 8 

,

T

A

 = 25

°

C, See Figure 1 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power supply rejection ratio

VDD = PVDD = xPVDD = 11 V to 13 V

–40

dB

IDD

Supply current

No output filter connected

25

35

mA

IDD(Mute) Supply current, mute mode

MUTE = 0 V

10

18

mA

IDD(S/D)

Supply current, shutdown mode

SHUTDOWN = 0 V

20

30

µ

A

|IIH|

High-level input current (MUTE, MODE,

SHUTDOWN)

VIH = 5.25 V

10

µ

A

|IIL|

Low-level input current (MUTE, MODE,

SHUTDOWN)

VIL = – 0.3 V

10

µ

A

rDS(on)

Static drain-to-source on-state resistance

(high-side + low-side FETs)

IDD = 0.5 A

720

800

m

rDS(on)

Matching, high-side to high-side, low-side to

low-side, same channel

95%

98%

operating characteristics, Class-D amplifier, V

DD

 = PV

DD

 = LPV

DD

 = RPV

DD

 = 12 V, R

L

 = 4 

T

A

 = 25

°

C, See Figure 1 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PO

Output power

f = 1 kHz,

THD = 0.5%, per channel,

Device soldered on PCB,

See Note 2

10

W

Efficiency

PO = 10 W,

f = 1 kHz

77%

AV

Gain

25

dB

Left/right channel gain matching

92%

95%

Noise floor

–60

dB

Dynamic range

80

dB

Crosstalk

f = 1 kHz

–50

dB

Frequency response bandwidth, post output filter, – 3 dB

20

20 000

Hz

BOM

Maximum output power bandwidth

20

kHz

ZI

Input impedance

10

k

NOTE 2: Output power is thermally limited, TA = 23

°

C

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

operating characteristics, Class-D amplifier, V

DD

 = PV

DD

 = LPV

DD

 = RPV

DD

 = 12 V, R

L

 = 8 

T

A

 = 25

°

C, See Figure 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PO

Output power,

THD = 0.5%, per channel,

 Device soldered on PCB,

See Note 2

7.5

W

Efficiency

PO = 7.5 W,

f = 1 kHz

85%

AV

Gain

25

dB

Left/right channel gain matching

92%

95%

Noise floor

–60

dB

Dynamic range

80

dB

Crosstalk

f = 1 kHz

–50

dB

Frequency response bandwidth, post output filter, – 3 dB

20

20 000

Hz

BOM

Maximum output power bandwidth

20

kHz

ZI

Input impedance

10

k

NOTE 2: Output power is thermally limited, TA = 85

°

C

electrical characteristics, headphone amplifier, HPV

CC

 = 5 V, R

L

 = 32 

, T

A

 = 25

°

C, See Figure 3

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power supply rejection ratio

–60

dB

Uncompensated gain range

–1

–10

V/V

IDD

Supply current

9

12

mA

IDD(MUTE) Supply current, mute mode

9

12

mA

IDD(S/D)

Supply current, shutdown mode

20

30

µ

A

operating characteristics, headphone amplifier, HPV

CC

 = 5V, R

L

 = 32 

, gain set at –10V/V,

T

A

 = 25

°

C, See Figure 3 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PO

Output power

THD = 0.5%,

f = 1 kHz

50

mW

Crosstalk

f = 1 kHz

–60

dB

Frequency response bandwidth, post output filter, – 3 dB

20

20

kHz

BOM

Maximum output power bandwidth

20

kHz

ZI

Input impedance

> 1

M

operating characteristics, HPREG 5-V regulator, T

A

 = 25

°

C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VO

Output voltage

VDD = PVDD = LPVDD = RPVDD = 8 V to 14 V,

IO = 0 to 90 mA

4.5

5.5

V

IOS

Short-circuit output current

VDD = PVDD = LPVDD = RPVDD = 8 V to 14 V†

90

mA

† Pulse width must be limited to prevent exceeding the maximum operating virtual junction temperature of 150

°

C.

thermal shutdown

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Thermal shutdown temperature

165

°

C

Thermal shutdown hysteresis

30

°

C

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

LINP

LINN

LCOMP

VDD

COSC

RCOMP

RINP

RINN

RPVDD

AGND

LPVDD

PVDD

SHUTDOWN

HPREG

V2P5

HPLIN

HPLOUT

HPVCC

HPROUT

HPRIN

PGND

15 

µ

H

15 

µ

H

0.22 

µ

F

0.22 

µ

F

µ

F

12 V

µ

F

µ

F

Balanced

Differential 

Input Signal

1000 pF

1000 pF

1000 pF

µ

F

µ

F

Balanced

Differential 

Input Signal

12 V

HPDR

HPDL

CP1

CP2

VCP

FAULT0

FAULT1

MODE

MUTE

HPREG

µ

F

LOUTP

LOUTN

15 

µ

H

15 

µ

H

0.22 

µ

F

0.22 

µ

F

µ

F

ROUTP

ROUTN

47 nF

0.1 

µ

F

42

1

2

3

9,16

5

4

6

43

48

44

45

33,34

7,20,46,47

12,13,27,36,37

21, 28

19

30

32

41

14,15

10,11

29

8

18

31

17

26

23

24

25

22

34,35

38,39

12 V

HPREG

12 V

500 k

100 k

To

HPREG

To HPVCC

0.1 

µ

F

Figure 1. 12-V, 4-

 Test Circuit

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

LINP

LINN

LCOMP

VDD

COSC

RCOMP

RINP

RINN

RPVDD

AGND

LPVDD

PVDD

SHUTDOWN

HPREG

V2P5

HPLIN

HPLOUT

HPVCC

HPROUT

HPRIN

PGND

30 

µ

H

30 

µ

H

0.1 

µ

F

0.1 

µ

F

µ

F

12 V

µ

F

µ

F

Balanced

Differential 

Input Signal

1000 pF

1000 pF

1000 pF

µ

F

µ

F

Balanced

Differential 

Input Signal

12 V

HPDR

HPDL

CP1

CP2

VCP

FAULT0

FAULT1

MODE

MUTE

µ

F

LOUTP

LOUTN

30 

µ

H

30 

µ

H

0.1 

µ

F

0.1 

µ

F

µ

F

ROUTP

ROUTN

47 nF

0.1 

µ

F

42

1

2

3

9,16

5

4

6

43

48

44

45

33,34

7,20,46,47

12,13,27,36,37

21, 28

19

30

32

41

14,15

10,11

29

8

18

31

17

26

23

24

25

22

34,35

38,39

12 V

HPREG

12 V

500 k

100 k

To

HPREG

HPREG

To HPVCC

0.1 

µ

F

Figure 2. 12-V, 8-

 Test Circuit

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

LINP

LINN

LCOMP

VDD

COSC

RCOMP

RINP

RINN

RPVDD

AGND

LPVDD

PVDD

SHUTDOWN

HPREG

V2P5

HPLIN

HPLOUT

HPVCC

HPROUT

HPRIN

PGND

12 V

12 V

1000 pF

470 pF

1000 pF

12 V

HPDR

HPDL

CP1

CP2

VCP

FAULT0

FAULT1

MODE

MUTE

µ

F

LOUTP

LOUTN

ROUTP

ROUTN

47 nF

0.1 

µ

F

42

1

2

3

9,16

5

4

6

43

48

44

45

33,34

7,20,46,47

12,13,27,36,37

21, 28

19

30

32

41

14,15

10,11

29

8

18

31

17

26

23

24

25

22

34,35

38,39

12 V

HPREG

HPREG

Left SE

HP Input

HPLOUT

100 k

100 k

0.1 

µ

F

Right SE

HP Input

100 k

0.1 

µ

F

100

k

500 k

100 k

VDD

To

HPREG

0.1 

µ

F

HPVCC

32 

32 

µ

F

32 

µ

F

32 

HPREG

HPROUT

Figure 3. Headphone Test Circuit

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

11

POST OFFICE BOX 655303 

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APPLICATION INFORMATION

LINP

LINN

LCOMP

VDD

COSC

RCOMP

RINP

RINN

RPVDD

AGND

LPVDD

PVDD

SHUTDOWN

HPREG

V2P5

HPLOUT

HPROUT

PGND

15 

µ

H

15 

µ

H

0.22 

µ

F

0.22 

µ

F

µ

F

12 V

12 V

µ

F

µ

F

Left Class-D Balanced

Differential  Input

Signal

1000 pF

1000 pF

1000 pF

µ

F

µ

F

HPDR

HPDL

CP1

CP2

VCP

FAULT0

FAULT1

MODE

MUTE

µ

F

LOUTP

LOUTN

15 

µ

H

15 

µ

H

0.22 

µ

F

0.22 

µ

F

µ

F

ROUTP

ROUTN

47 nF

0.1 

µ

F

42

1

2

3

9,16

5

4

6

43

48

44

45

33,34

7,20,46,47

12,13,27,36,37

21, 28

41

14,15

10,11

29

8

18

31

17

26

23

24

25

22

34,35

38,39

12 V

HPLIN

HPVCC

HPRIN

19

30

32

Left SE

HP Input

HPLOUT

100 k

100 k

0.1 

µ

F

Right SE

HP Input

100 k

0.1 

µ

F

100

k

500 k

100 k

VDD

To

HPREG

0.1 

µ

F

To System

Control

100 k

µ

F

µ

F

10 

µ

F

Right Class-D Balanced

Differential  Input

Signal

12 V

µ

F

µ

F

10 

µ

F

µ

F

100 k

100 k

To System

Control

µ

F

HPVCC

100 k

HPVCC

MODE

1 k

1 k

NOTE A:          = power ground and          = analog ground

HPROUT

220 

µ

F

220 

µ

F

HPREG

Figure 4. TPA032D04 Typical Configuration Application Circuit

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

12

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

input capacitor, C

I

In the typical application an input capacitor, C

I

, is required to allow the amplifier to bias the input signal to the

proper dc level for optimum operation. In this case, C

I

 and Z

I

, the TPA032D04’s input resistance forms a

high-pass filter with the corner frequency determined in equation 8.

(8)

f

c(highpass)

+

1

2

p

Z

I

C

I

–3 dB

fc

Z

I

 is nominally 10 k

The value of C

I

 is important to consider as it directly affects the bass (low frequency) performance of the circuit.

Consider the example where the specification calls for a flat bass response down to 40 Hz. Equation 8 is

reconfigured as equation 9.

(9)

C

I

+

1

2

p

Z

I

fc

In this example, C

I

 is 0.40 

µ

F so one would likely choose a value in the range of 0.47 

µ

F to 1 

µ

F. A low-leakage

tantalum or ceramic capacitor is the best choice for the input capacitors. When polarized capacitors are used,

the positive side of the capacitor should face the amplifier input, as the dc level there is held at 1.5 V, which is

likely higher than the source dc level. Please note that it is important to confirm the capacitor polarity in the

application.

differential input

The TPA032D04 has differential inputs to minimize distortion at the input to the IC. Since these inputs nominally

sit at 1.5 V, dc-blocking capacitors are required on each of the four input terminals. If the signal source is

single-ended, optimal performance is achieved by treating the signal ground as a signal. In other words,

reference the signal ground at the signal source, and run a trace to the dc-blocking capacitor, which should be

located physically close to the TPA032D04. If this is not feasible, it is still necessary to locally ground the unused

input terminal through a dc-blocking capacitor.

power supply decoupling, C

S

The TPA032D04 is a high-performance Class-D CMOS audio amplifier that requires adequate power supply

decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling

also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling

is achieved by using two capacitors of different types that target different types of noise on the power supply

leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-

resistance (ESR) ceramic capacitor, typically 0.1 

µ

F placed as close as possible to the device’s various V

DD

leads, works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 

µ

F

or greater placed near the audio power amplifier is recommended.

The TPA032D04 has several different power supply terminals. This was done to isolate the noise resulting from

high-current switching from the sensitive analog circuitry inside the IC.

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

13

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

mute and shutdown modes

The TPA032D04 employs both a mute and a shutdown mode of operation designed to reduce supply current,

I

DD

, to the absolute minimum level during periods of non-use for battery-power conservation. The SHUTDOWN

input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN

low causes the outputs to mute and the amplifier to enter a low-current state, I

DD

 = 20 

µ

A.  Mute mode alone

reduces  I

DD

 to 10 mA.

using low-ESR capacitors

Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)

capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this

resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this

resistance the more the real capacitor behaves like an ideal capacitor.

output filter components

The output inductors are key elements in the performance of the class-D audio amplifier system. It is important

that these inductors have a high enough current rating and a relatively constant inductance over frequency and

temperature. The current rating should be higher than the expected maximum current to avoid magnetically

saturating the inductor. When saturation occurs, the inductor loses its functionality and looks like a short circuit

to the PWM signal, which increases the harmonic distortion considerably.

A shielded inductor may be required if the class-D amplifier is placed in an EMI sensitive system; however, the

switching frequency is low for EMI considerations and should not be an issue in most systems. The dc series

resistance of the inductor should be low to minimize losses due to power dissipation in the inductor, which

reduces the efficiency of the circuit.

Capacitors are important in attenuating the switching frequency and high frequency noise, and in supplying

some of the current to the load. It is best to use capacitors with low equivalent-series-resistance (ESR). A low

ESR means that less power is dissipated in the capacitor as it shunts the high-frequency signals. Placing these

capacitors in parallel also parallels their ESR, effectively reducing the overall ESR value. The voltage rating is

also important, and, as a rule of thumb, should be 2 to 3 times the maximum rms voltage expected to allow for

high peak voltages and transient spikes. These output filter capacitors should be stable over temperature since

large currents flow through them.

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

14

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

efficiency of class-D vs linear operation

Amplifier efficiency is defined as the ratio of output power delivered to the load to power drawn from the supply.

In the efficiency equation below, P

L

 is power across the load and P

SUP

 is the supply power.

Efficiency

+ h +

P

L

P

SUP

A high-efficiency amplifier has a number of advantages over one with lower efficiency. One of these advantages

is a lower power requirement for a given output, which translates into less waste heat that must be removed

from the device, smaller power supply required, and increased battery life.

Audio power amplifier systems have traditionally used linear amplifiers, which are well known for being

inefficient. Class-D amplifiers were developed as a means to increase the efficiency of audio power amplifier

systems.

A linear amplifier is designed to act as a variable resistor network between the power supply and the load. The

transistors operate in their linear region and voltage that is dropped across the transistors (in their role as

variable resistors) is lost as heat, particularly in the output transistors.

The output transistors of a class-D amplifier switch from full OFF to full ON (saturated) and then back again,

spending very little time in the linear region in between. As a result, very little power is lost to heat because the

transistors are not operated in their linear region. If the transistors have a low on-resistance, little voltage is

dropped across them, further reducing losses. The ideal class-D amplifier is 100% efficient, which assumes that

both the on-resistance (r

DS(on)

) and the switching times of the output transistors are zero.

the ideal class-D amplifier

To illustrate how the output transistors of a class-D amplifier operate, a half-bridge application is examined first

(see Figure 5).

VDD

VOUT

L

CL

RL

IL

IOUT

+

VA

M2

M1

C

Figure 5. Half-Bridge Class-D Output Stage

Figures 6 and 7 show the currents and voltages of the half-bridge circuit. When transistor M1 is on and M2 is

off, the inductor current is approximately equal to the supply current. When M2 switches on and M1 switches

off, the supply current drops to zero, but the inductor keeps the inductor current from dropping. The additional

inductor current is flowing through M2 from ground. This means that V

A

 (the voltage at the drain of M2, as shown

in Figure 5) transitions between the supply voltage and slightly below ground. The inductor and capacitor form

a low-pass filter, which makes the output current equal to the average of the inductor current. The low pass filter

averages V

A

, which makes V

OUT

 equal to the supply voltage multiplied by the duty cycle.

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

15

POST OFFICE BOX 655303 

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APPLICATION INFORMATION

the ideal class-D amplifier (continued)

Control logic is used to adjust the output power, and both transistors are never on at the same time. If the output

voltage is rising, M1 is on for a longer period of time than M2.

Supply Current

Time

M1 on

M2 off

M1 off

M2 on

M1 on

M2 off

Output Current

Inductor Current

0

Current

Figure 6. Class-D Currents

VDD

VA

VOUT

0

V

oltage

Time

M1 on

M2 off

M1 off

M2 on

M1 on

M2 off

Figure 7. Class-D Voltages

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

16

POST OFFICE BOX 655303 

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APPLICATION INFORMATION

the ideal class-D amplifier (continued)

Given these plots, the efficiency of the class-D device can be calculated and compared to an ideal linear

amplifier device. In the derivation below, a sine wave of peak voltage (V

P

) is the output from an ideal class-D

and linear amplifier and the efficiency is calculated.

V

L(rms)

+

V

P

2

Ǹ

CLASS-D

LINEAR

V

L(rms)

+

V

P

2

Ǹ

P

L

+

V

L

 

I

L

Average

ǒ

I

DD

Ǔ

+

I

L(rms)

 

V

L(rms)

V

DD

P

L

+

V

L(rms)

2

R

L

+

V

P

2

2 R

L

Average

ǒ

I

DD

Ǔ

+

2

p  

V

P

R

L

P

SUP

+

V

DD

 

Average

ǒ

I

DD

Ǔ

P

SUP

+

V

DD

 

Average

ǒ

I

DD

Ǔ

+

V

DD

V

P

R

L

 

2

p

P

SUP

+

V

DD

 

I

L(rms)

 

V

L(rms)

V

DD

Efficiency

+ h +

P

L

P

SUP

Efficiency

+ h +

P

L

P

SUP

Efficiency

+ h +

V

DD

 

V

P

2

2R

L

2

p  

V

P

R

L

Efficiency

+ h +

1

Efficiency

+ h + p

4

 

V

P

V

DD

In the ideal efficiency equations, assume that V

P

 = V

DD

, which is the maximum sine wave magnitude without

clipping. Then, the highest efficiency that a linear amplifier can have without clipping is 78.5%. A class-D

amplifier, however, can ideally have an efficiency of 100% at all power levels.

The derivation above applies to an H-bridge as well as a half-bridge. An H-bridge requires approximately twice

the supply current but only requires half the supply voltage to achieve the same output power—factors that

cancel in the efficiency calculation. The H-bridge circuit is shown in Figure 8.

VDD

VOUT

L

CL

RL

IL

IOUT

+

VA

M2

M1

VDD

L

CL

M4

M3

Figure 8. H-Bridge Class-D Output Stage

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

17

POST OFFICE BOX 655303 

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APPLICATION INFORMATION

losses in a real-world class-D amplifier

Losses make class-D amplifiers nonideal, and reduce the efficiency below 100%. These losses are due to the

output transistors having a nonzero r

DS(on)

, and rise and fall times that are greater than zero.

The loss due to a nonzero r

DS(on)

 is called conduction loss, and is the power lost in the output transistors at

nonswitching times, when the transistor is on (saturated). Any r

DS(on)

 above 0 

 causes conduction loss.

Figure 9 shows an H-bridge output circuit simplified for conduction loss analysis and can be used to determine

new efficiencies with conduction losses included.

VDD = 12 V

RL

0.36

 Ω

0.36

 Ω

rDS(on)

rDS(off)

rDS(off)

rDS(on)

5 M

5 M

Figure 9. Output Transistor Simplification for Conduction Loss Calculation

The power supplied, P

SUP

, is determined to be the power output to the load plus the power lost in the transistors,

assuming that there are always two transistors on.

Efficiency

+ h +

I

2

R

L

I

2

2r

DS(on)

)

I

2

R

L

Efficiency

+ h +

P

L

P

SUP

Efficiency

+ h +

R

L

2r

DS(on)

)

R

L

Efficiency

+ h +

95%

ǒ

at all output levels r

DS(on)

+

0.1

, R

L

+

4

Ǔ

Efficiency

+ h +

85%

ǒ

at all output levels r

DS(on)

+

0.36

, R

L

+

4

Ǔ

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

18

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

losses in a real-world class-D amplifier (continued)

Losses due to rise and fall times are called switching losses. A diagram of the output, showing switching losses,

is shown in Figure 10.

tSWon

+

tSWoff =

tSW

1

f

SW

Figure 10. Output Switching Losses

Rise and fall times are greater than zero for several reasons. One is that the output transistors cannot switch

instantaneously because (assuming a MOSFET) the channel from drain to source requires a specific period

of time to form. Another is that transistor gate-source capacitance and parasitic resistance in traces form RC

time constants that also increase rise and fall times.

Switching losses are constant at all output power levels, which means that switching losses can be ignored at

high power levels in most cases. At low power levels, however, switching losses must be taken into account

when calculating efficiency. Switching losses are dominated by conduction losses at the high output powers,

but should be considered at low powers. The switching losses are automatically taken into account if you

consider the quiescent current with the output filter and load.

class-D effect on power supply

Efficiency calculations are an important factor for proper power supply design in amplifier systems. Table 2

shows Class-D efficiency at a range of output power levels (per channel) with a 1-kHz sine wave input. The

maximum power supply draw from a stereo 10-W per channel audio system with 4-

 loads and a 12-V supply

is almost 26 W. A similar linear amplifier such as the TPA032D04 has a maximum draw of greater than 50 W

under the same circumstances.

Table 2. Efficiency vs Output Power in 12-V 4-

 H-Bridge Systems

Output Power (W)

Efficiency (%)

Peak Voltage (V)

Internal Dissipation (W)

0.5

41.7

2

0.7

2

66.7

4

1.0

5

75.1

6.32

1.66

8

78

8

2.26

10

77.9

8.94†

2.84

† High peak voltages cause the THD to increase

background image

TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

19

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

class-D effect on power supply (continued)

There is a minor power supply savings with a class-D amplifier versus a linear amplifier when amplifying sine

waves. The difference is much larger when the amplifier is used strictly for music. This is because music has

much lower RMS output power levels, given the same peak output power (see Figure 11); and although linear

devices are relatively efficient at high RMS output levels, they are very inefficient at mid-to-low RMS power

levels. The standard method of comparing the peak power to RMS power for a given signal is crest factor, whose

equation is shown below. The lower RMS power for a set peak power results in a higher crest factor

Crest Factor

+

10 log

P

PK

P

rms

Time

PPK

Power

PRMS

Figure 11. Audio Signal Showing Peak and RMS Power

background image

TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

20

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

crest factor and thermal considerations

 A typical music CD requires 12 dB to 15 dB of dynamic headroom to pass the loudest portions without distortion

as compared with the average power output. From the TPA032D04 data sheet, one can see that when the

TPA032D04 is operating from a 12-V supply into a 4-

 speaker that 20-W peaks are available. Converting watts

to dB:

P

dB

+

10 Log

ǒ

P

W

P

ref

Ǔ

+

10Log

ǒ

20

1

Ǔ

+

6 dB

(17)

Subtracting the crest factor restriction to obtain the average listening level without distortion yields:

6.0 dB

*

15 dB

+ *

9 dB (15 dB crest factor)

6.0 dB

*

12 dB

+ *

6 dB (12 dB crest factor)

6.0 dB

*

9 dB

+ *

3 dB (9 dB crest factor)

6.0 dB

*

6 dB

+ *

0 dB (6 dB crest factor)

6.0 dB

*

3 dB

+

3 dB (3 dB crest factor)

6.0 dB

*

18 dB

+ *

12 dB (15 dB crest factor)

Converting dB back into watts:

P

W

+

10

PdB

ń

10

 

P

ref

+

630 mW (15 dB crest factor)

+

1.25 W (12 dB crest factor)

+

2.5 W (9 dB crest factor)

+

5 W (6 dB crest factor)

+

10 W (3 dB crest factor)

(18)

+

315 mW (18 dB crest factor)

This is valuable information to consider when attempting to estimate the heat dissipation requirements for the

amplifier system. Comparing the absolute worst case, which is 10 W of continuous power output with a 3 dB

crest factor, against 12 dB and 15 dB applications drastically affects maximum ambient temperature ratings for

the system. Using the power dissipation curves for a 12-V, 4-

 system, the internal dissipation in the

TPA032D04 and maximum ambient temperatures are shown in Table 3.

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

21

POST OFFICE BOX 655303 

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APPLICATION INFORMATION

crest factor and thermal considerations (continued)

Table 3. TPA032D04 Power Rating, 12-V, 4-

, Stereo

PEAK OUTPUT POWER

AVERAGE OUTPUT POWER

POWER DISSIPATION

MAXIMUM AMBIENT

(W)

AVERAGE OUTPUT POWER

(W/Channel)

TEMPERATURE

20

10 W (3 dB)

2.84

23

°

C

20

5 W (6 dB)

1.66

75

°

C

20

2.5 W (9 dB)

1.12

100

°

C

20

1.25 W (12 dB)

0.87

111

°

C

20

630 mW (15 dB)

0.7

118

°

C

20

315 mW (18 dB)

0.6

123

°

C

The maximum ambient temperature depends on the heatsinking ability of the PCB system. Using the 0 CFM

data from the dissipation rating table, the derating factor for the DCA package with 6.9 in

2

 of copper area on

a multilayer PCB is 44.8 mW/

°

C. Converting this to 

Θ

JA

:

Θ

JA

+

1

Derating

+

1

0.0448

+

22.3

°

C

ń

W

(19)

To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are

per channel so the dissipated heat needs to be doubled for two channel operation. Given 

Θ

JA

, the maximum

allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be

calculated with the following equation. The maximum recommended junction temperature for the TPA032D04

is 150 

°

C. The internal dissipation figures are taken from the Efficiency vs Output Power graphs.

T

A

Max

+

T

J

Max

*

Θ

JA

P

D

+

150

*

22.3 (0.7

 

2)

+

118

°

C (15 dB crest factor)

+

150

*

22.3 (2.84

 

2)

+

23

°

C (3dB crest factor)

(20)

NOTE:

Internal dissipation of 1.4 W is estimated for a 10-W system with a 15 dB crest factor per channel.

The TPA032D04 is designed with thermal protection that turns the device off when the junction temperature

surpasses 150

°

C to prevent damage to the IC. Table 3 was calculated for maximum listening volume without

distortion. When the output level is reduced the numbers in the table change significantly. Also, using 8-

speakers dramatically increases the thermal performance by increasing amplifier efficiency.

background image

TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

22

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

THERMAL INFORMATION

The thermally enhanced DCA package is based on the 56-pin TSSOP, but includes a thermal pad (see Figure 12)

to provide an effective thermal contact between the IC and the PWB.

Traditionally, surface-mount and power have been mutually exclusive terms. A variety of scaled-down TO-220-type

packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages,

however, have only two shortcomings: they do not address the very low profile requirements (< 2 mm) of many of

today’s advanced systems, and they do not offer a terminal-count high enough to accommodate increasing

integration. On the other hand, traditional low-power surface-mount packages require power-dissipation derating that

severely limits the usable range of many high-performance analog circuits.

The PowerPAD package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal

performance comparable to much larger power packages.

The PowerPAD package is designed to optimize the heat transfer to the PWB. Because of the very small size and

limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that

remove heat from the component. The thermal pad is formed using a patented lead-frame design and manufacturing

technique to provide a direct connection to the heat-generating IC. When this pad is soldered or otherwise thermally

coupled to an external heat dissipator, high power dissipation in the ultra-thin, fine-pitch, surface-mount package can

be reliably achieved.

DIE

Side View (a)

End View (b)

Bottom View (c)

DIE

Thermal

Pad

Figure 12. Views of Thermally Enhanced DCA Package

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TPA032D04

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

 

 

SLOS203A – DECEMBER 1999 – REVISED MARCH 2000

23

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL DATA

DCA (R-PDSO-G**)     

PowerPAD

 PLASTIC SMALL-OUTLINE PACKAGE

0,25

0,50

0,75

0,15 NOM

Gage Plane

6,00

6,20

8,30

7,90

Thermal Pad

(See Note D)

64

17,10

56

14,10

Seating Plane

16,90

13,90

4073259/A 01/98

0,27

25

24

A

0,17

48 PINS SHOWN

48

1

48

DIM

PINS **

A  MAX

A  MIN

1,20 MAX

12,40

12,60

0,50

0,10

M

0,08

0

°

– 8

°

0,05

0,15

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments.

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 2000, Texas Instruments Incorporated