background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

1

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

D

CMOS/EEPROM/EPROM Technologies on a

Single Device

–  Mask-ROM Devices for High-Volume

Production

–  One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

–  Reprogrammable EPROM Devices for

Prototyping Purposes

D

Internal System Memory Configurations

–  On-Chip Program Memory Versions

–  ROM: 4K to 48K Bytes

–  EPROM: 16K to 48K Bytes

–  ROM-less

–  Data EEPROM: 256 or 512 Bytes

–  Static RAM: 256 to 3.5K Bytes

–  External Memory / Peripheral Wait States

–  Precoded External Chip-Select Outputs

in Microcomputer Mode

D

Flexible Operating Features

–  Low-Power Modes: STANDBY and HALT

–  Commercial, Industrial, and Automotive

Temperature Ranges

–  Clock Options

–  Divide-by-4 (0.5 MHz – 5 MHz SYSCLK)

–  Divide-by-1 (2 MHz – 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

–  Supply Voltage (V

CC

): 5 V 

±

 10%

D

Eight-Channel 8-Bit Analog-to-Digital

Converter 1 (ADC1)

D

Two 16-Bit General-Purpose Timers

D

On-Chip 24-Bit Watchdog Timer

D

Two Communication Modules

–  Serial Communications Interface 1 (SCI1)

–  Serial Peripheral Interface (SPI)

D

Flexible Interrupt Handling

D

TMS370 Series Compatibility

D

CMOS/Package /TTL-Compatible I / O Pins

–  64-Pin Plastic and Ceramic Shrink

Dual-In-Line Packages / 44 Bidirectional,

9 Input Pins

–  68-Pin Plastic and Ceramic Leaded Chip

Carrier Packages / 46 Bidirectional,

9 Input Pins

–  All Peripheral Function Pins Are

Software Configurable for Digital I / O

D

Workstation/PC-Based Development

System

–  C Compiler and C Source Debugger

–  Real-Time In-Circuit Emulation

–  Extensive Breakpoint / Trace Capability

–  Software Performance Analysis

–  Multi-Window User Interface

–  Microcontroller Programmer

     

 

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright 

©

 1997, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FN / FZ PACKAGE

( TOP VIEW )

V

SS1

B7

C2

C1

MC

C0

B6

T2AIC1/CR

SCICLK

SCIRXD

SCITXD

XT

AL2/CLKIN

XT

AL1

C3

C4

C5

C6

C7

SPISOMI

SPICLK

SPISIMO

T1IC/CR

T1PWM

T1EVT

9 8 7 6 5 4 3

10

11

12

13

14

15

16

B5

B0

B4

B3

B2

B1

D0

/

CSE2

/

OCF

V

CC2

V

SS2

V

CC1

2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

V

CC3

V

SS3

V

CC1

17

18

19

20

21

22

23

24

25

26

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

V

CC2

V

SS2

A0

A1

A2

A3

A4

A5

A6

A7

T2AEVT

T2AIC2/PWM

INT1

INT2

INT3

D1 / CSH3

D2 / CSH2

D3 / SYSCLK

D4 / R / W

D5 / CSPF

D6/CSH1/EDS

D7/CSE1/WAIT

RESET

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

JN / NM PACKAGE

( TOP VIEW )

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

B5

B6

B7

C0

MC

C1

C2

V

SS1

C3

C4

C5

C6

C7

AN0

A0

A1

A2

A3

A4

A5

A6

A7

T2AEVT

T2AIC2 / PWM

T2AIC1 / CR

SCICLK

SCIRXD

SCITXD

XTAL2 / CLKIN

XTAL1

V

CC1

V

CC3

B4

B3

B2

B1

B0

D0 / CSE2 / OCF

V

SS1

V

CC1

D1 / CSH3

D3 / SYSCLK

D4 / R / W

D6 / CSH1 / EDS

D7 / CSE1 / WAIT

RESET

INT1

INT2

INT3

SPISOMI

SPISIMO

SPICLK

T1IC / CR

T1PWM

AN7

T1EVT

V

SS1

AN6

AN5

AN4

AN3

AN1

AN2

V

SS3

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

2

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

Pin Descriptions

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PIN

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

NAME

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ALTERNATE

FUNCTION

ÁÁÁ

ÁÁÁ

SDIP

(64)

ÁÁÁ

ÁÁÁ

LCC

(68)

ÁÁ

ÁÁ

I/O†

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION‡

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

A0

A1

A2

A3

A4

A5

A6

A7

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

15

16

17

18

19

20

21

22

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

17

18

19

20

21

22

23

24

ÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Single-chip mode: Port A is a general-purpose bidirectional I/O port.

Expansion mode: Port A can be individually programmed as the external

bidirectional data bus (DATA0 – DATA7).

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

B0

B1

B2

B3

B4

B5

B6

B7

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

60

61

62

63

64

1

2

3

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

65

66

67

68

1

2

3

4

ÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Single-chip mode: Port B is a general-purpose bidirectional I/O port.

Expansion mode: Port B can be individually programmed as the low-order address

output bus (ADDR0 – ADDR7).

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

C0

C1

C2

C3

C4

C5

C6

C7

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

4

6

7

9

10

11

12

13

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

5

7

8

10

11

12

13

14

ÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Single-chip mode: Port C is a general-purpose bidirectional I/O port.

Expansion mode: Port C can be individually programmed as the high-order address

output bus (ADDR8 – ADDR15).

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INT1

INT2

INT3

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

NMI

ÁÁÁ

Á

Á

Á

Á

Á

Á

ÁÁÁ

50

49

48

ÁÁÁ

Á

Á

Á

Á

Á

Á

ÁÁÁ

52

51

50

ÁÁ

Á

Á

Á

Á

ÁÁ

I

I / O

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

External (nonmaskable or maskable) interrupt/general-purpose input pin

External maskable interrupt input/general-purpose bidirectional pin

External maskable interrupt input/general-purpose bidirectional pin

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

E0

E1

E2

E3

E4

E5

E6

E7

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

14

34

35

36

37

38

39

42

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

36

37

38

39

40

41

42

43

ÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ADC1 analog input (AN0 – AN7) or positive reference pins (AN1 – AN7)

Port E can be individually programmed as general-purpose input pins if not used

as ADC1 analog input or positive reference input.

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

VCC3

VSS3

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

32

33

ÁÁÁ

Á

Á

Á

ÁÁÁ

34

35

ÁÁ

Á

Á

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ADC1 positive-supply voltage and optional positive-reference input pin

ADC1 ground reference pin

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

RESET

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

51

ÁÁÁ

Á

Á

Á

ÁÁÁ

53

ÁÁ

Á

Á

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

System reset bidirectional pin. RESET, as an input, initializes the microcontroller;

as open-drain output, RESET indicates an internal failure was detected by the

watchdog or oscillator fault circuit.

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

MC

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

5

ÁÁÁ

Á

Á

Á

ÁÁÁ

6

ÁÁ

Á

Á

ÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode control (MC) pin. MC enables EEPROM write-protection override (WPO)

mode, also EPROM VPP.

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

XTAL2/CLKIN

XTAL1

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

29

30

ÁÁÁ

Á

Á

Á

ÁÁÁ

31

32

ÁÁ

Á

Á

ÁÁ

I

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Internal oscillator crystal input / external clock source input

Internal oscillator output for crystal

ÁÁÁÁÁ

ÁÁÁÁÁ

VCC1

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

31, 57

ÁÁÁ

ÁÁÁ

33,

61

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Positive supply voltage

ÁÁÁÁÁ

ÁÁÁÁÁ

VCC2

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

15,63

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Positive supply voltage

† I = input, O = output

‡ Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

3

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

Pin Descriptions (Continued)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PIN

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

NAME

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ALTERNATE

FUNCTION

ÁÁÁ

Á

Á

Á

ÁÁÁ

SDIP

(64)

ÁÁÁ

Á

Á

Á

ÁÁÁ

LCC

(68)

ÁÁ

ÁÁ

ÁÁ

I/O†

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION‡

ÁÁÁÁÁ

ÁÁÁÁÁ

VSS1

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

8,

58,40

ÁÁÁ

ÁÁÁ

9

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ground reference for digital logic

ÁÁÁÁÁ

ÁÁÁÁÁ

VSS2

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

16,62

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ground reference for digital I / O logic

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

FUNCTION

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁ

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Single-chip mode: Port D is a general-purpose bidirectional I / O port. Each of

the port D pins can be individually configured as a general-purpose I / O pin,

primary memory control signal (function A) or secondary memory control

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

A

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

B

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁ

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

primary  memory  control  signal  (function  A),  or  secondary  memory  control

signal (function B). All chip selects are independent and can be used for

memory bank switching. Refer to Table 1 for function A memory accesses.

ÁÁÁÁÁ

ÁÁÁÁÁ

D0

ÁÁÁ

ÁÁÁ

CSE2

ÁÁÁÁ

ÁÁÁÁ

OCF

ÁÁÁ

ÁÁÁ

59

ÁÁÁ

ÁÁÁ

64

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select eighth output 2 goes low during memory accesses

I / O pin B: Opcode fetch goes low during the opcode fetch memory cycle.

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

D1

ÁÁÁ

Á

Á

Á

ÁÁÁ

CSH3

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

56

ÁÁÁ

Á

Á

Á

ÁÁÁ

60

ÁÁ

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select half output 3 goes low during memory accesses.

I / O pin B: Reserved

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

D2

ÁÁÁ

Á

Á

Á

ÁÁÁ

CSH2

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

59

ÁÁ

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select half output 2 goes low during memory accesses.

I / O pin B: Reserved

ÁÁÁÁÁ

D3

ÁÁÁ

SYSCLK

ÁÁÁÁ

SYSCLK

ÁÁÁ

55

ÁÁÁ

58

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A, B: Internal clock signal is 1 / 1 (PLL) or 1 / 4 XTAL2 / CLKIN frequency.

ÁÁÁÁÁ

ÁÁÁÁÁ

D4

ÁÁÁ

ÁÁÁ

R / W

ÁÁÁÁ

ÁÁÁÁ

R / W

ÁÁÁ

ÁÁÁ

54

ÁÁÁ

ÁÁÁ

57

ÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A, B: Read / write output pin

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

D5

ÁÁÁ

Á

Á

Á

ÁÁÁ

CSPF

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

56

ÁÁ

ÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select peripheral output for peripheral file goes low during

memory accesses.

I / O pin B: Reserved

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

D6

ÁÁÁ

Á

Á

Á

Á

Á

Á

ÁÁÁ

CSH1

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

EDS

ÁÁÁ

Á

Á

Á

Á

Á

Á

ÁÁÁ

53

ÁÁÁ

Á

Á

Á

Á

Á

Á

ÁÁÁ

55

ÁÁ

ÁÁ

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select half output 1 goes low during memory accesses.

I / O pin B: External data strobe output goes low during memory accesses from

external memory and has the same timings as the five chip selects.

ÁÁÁÁÁ

ÁÁÁÁÁ

D7

ÁÁÁ

ÁÁÁ

CSE1

ÁÁÁÁ

ÁÁÁÁ

WAIT

ÁÁÁ

ÁÁÁ

52

ÁÁÁ

ÁÁÁ

54

ÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select eighth output goes low during memory accesses.

I / O pin B: Wait input pin extends bus signals.

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCITXD

SCIRXD

SCICLK

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

SCIIO1

SCIIO2

SCIIO3

ÁÁÁ

Á

Á

Á

ÁÁÁ

28

27

26

ÁÁÁ

Á

Á

Á

ÁÁÁ

30

29

28

ÁÁ

ÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SCI transmit data output pin / general-purpose bidirectional pin (see Note 1)

SCI receive data input pin / general-purpose bidirectional pin

SCI bidirectional serial clock pin / general-purpose bidirectional pin

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T1IC / CR

T1PWM

T1EVT

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

T1IO1

T1IO2

T1IO3

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

44

43

41

ÁÁÁ

Á

Á

Á

Á

Á

Á

Á

Á

Á

ÁÁÁ

46

45

44

ÁÁ

ÁÁ

ÁÁ

ÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Timer1 input capture / counter reset input pin / general-purpose bidirectional

pin

Timer1 pulse-width-modulation (PWM) output pin / general-purpose

bidirectional pin

Timer1 external event input pin / general-purpose bidirectional pin

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AIC1 / CR

T2AIC2 / PWM

T2AEVT

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

T2AIO1

T2AIO2

T2AIO3

ÁÁÁ

Á

Á

Á

Á

Á

Á

ÁÁÁ

25

24

23

ÁÁÁ

Á

Á

Á

Á

Á

Á

ÁÁÁ

27

26

25

ÁÁ

ÁÁ

ÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Timer2A input capture 1 / counter reset input pin / general-purpose bidirectional

pin

Timer2A input capture 2 / PWM output pin / general-purpose bidirectional pin

Timer2A external event input pin / general-purpose bidirectional pin

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SPISOMI

SPISIMO

SPICLK

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

SPIIO1

SPIIO2

SPIIO3

ÁÁÁ

Á

Á

Á

ÁÁÁ

47

46

45

ÁÁÁ

Á

Á

Á

ÁÁÁ

49

48

47

ÁÁ

ÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SPI slave output pin, master input pin / general-purpose bidirectional pin

SPI slave input pin, master output pin / general-purpose bidirectional pin

SPI bidirectional serial clock pin / general-purpose bidirectional pin

† I = input, O = output

‡ Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK.

NOTE 1: The three-pin configuration SCI is referred to as SCI1.

Table 1. Function A: Memory Accesses Locations for ‘x5x Devices

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

FUNCTION A

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

‘X50, ‘X52, ‘X53, AND ‘X56

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

‘X58

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

‘X59

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

CSEx

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

2000h – 3FFFh (8K bytes)

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

A000h – BFFFh (8K bytes)

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

E000h – EFFFh (4K bytes)

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

CSHx

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

8000h – FFFFh (32K bytes)

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

C000h – FFFFh (16K bytes)

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

F000h – FFFFh (4K bytes)

ÁÁÁÁÁÁÁÁÁ

CSPF

ÁÁÁÁÁÁÁÁÁ

10C0h – 10FFh (64 bytes)

ÁÁÁÁÁÁÁÁÁ

10C0h – 10FFh (64 bytes)

ÁÁÁÁÁÁÁÁÁ

10C0h – 10FFh (64 bytes)

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

4

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

functional block diagram

Program Memory

ROM: 4K, 8K, 12K, 16K,

32K, or 48K Bytes

EPROM: 16K, 32K, or

48K Bytes

VSS1

VCC1

RESET

MC

XTAL2/

CLKIN

XTAL1

INT3

INT2

INT1

E0 – E7

or

AN0 – AN7

VCC2

VSS2

Data EEPROM

0, 256, or 512 Bytes

RAM

256, 512, 1K, 1.5K, or

3.5K Bytes

CPU

Port D†

Port C

Port B

Watchdog

Timer 1

Timer 2A

Serial

Communications

Interface 1

Serial

Peripheral

Interface

Analog-to-Digital

Converter 1

System Control

Clock Options:

Divide-by-4 or

Divide-by-1(PLL)

T1PWM

T1EVT

T1IC / CR

T2AIC2 / PWM

T2AEVT

T2AIC1 / CR

SCICLK

SCITXD

SCIRXD

SPICLK

SPISIMO

SPISOMI

VSS3

VCC3

Port A

Interrupts

8/6

8

8

8

Memory Expansion

Data

Address LSbyte

Address MSbyte

Control

† For the 64-pin devices, there are only six pins for port D.

description

The TMS370Cx5x family of single-chip 8-bit microcontrollers provides cost-effective real-time system control

through integration of advanced peripheral function modules and various on-chip memory configurations. The

TMS370Cx5x family presently consists of twenty-one devices which are grouped into seven main sub-families:

the TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and

SE370C75x.

The TMS370Cx5x family of devices is implemented using high-performance silicon-gate CMOS EPROM and

EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of

CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the

TMS370Cx5x devices attractive in system designs for automotive electronics, industrial motor control,

computer peripheral control, telecommunications, and consumer application. Table 2 provides a memory

configuration overview of the TMS370Cx5x devices.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

5

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

description (continued)

Table 2. Memory Configurations

DEVICE

PROGRAM

MEMORY 

(BYTES)

OFF-CHIP

MEMORY

EXP (BYTES)

DATA MEMORY

(BYTES)

OPERATING

MODES

PACKAGES

68 PIN PLCC/CLCC, OR

64 PIN PSDIP/CSDIP

ROM

EPROM

EXP. (BYTES)

RAM

EEPROM

µ

C

µ

P

64 PIN PSDIP/CSDIP

TMS370Cx50: TMS370C050, TMS370C150, TMS370C250, AND TMS370C350

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C050A

ÁÁÁ

ÁÁÁ

4K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C150A

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

56K

ÁÁÁ

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C250A

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

56K

ÁÁÁ

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C350A

ÁÁÁ

ÁÁÁ

4K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

TMS370Cx52: TMS370C052, TMS370C352, AND TMS370C452

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C052A

ÁÁÁ

ÁÁÁ

8K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

ÁÁÁÁÁÁÁÁ

TMS370C352A

ÁÁÁ

8K

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C452A‡

ÁÁÁ

ÁÁÁ

8K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

TMS370Cx53: TMS370C353

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C353A

ÁÁÁ

ÁÁÁ

12K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

1.5K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

TMS370Cx56: TMS370C056, TMS370C156, TMS370C256, TMS370C356, TMS370C456, AND TMS370C756

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C056A

ÁÁÁ

ÁÁÁ

16K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

512

ÁÁÁÁ

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C156A

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

56K

ÁÁÁ

ÁÁÁ

512

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C256A

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

56K

ÁÁÁ

ÁÁÁ

512

ÁÁÁÁ

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C356A

ÁÁÁ

ÁÁÁ

16K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

512

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

ÁÁÁÁÁÁÁÁ

TMS370C456A‡

ÁÁÁ

16K

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

512

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C756A

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

16K

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

512

ÁÁÁÁ

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

TMS370Cx58: TMS370C058, TMS370C358, AND TMS370C758

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C058A

ÁÁÁ

ÁÁÁ

32K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

64K

ÁÁÁ

ÁÁÁ

1K

ÁÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C358A

ÁÁÁ

ÁÁÁ

32K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

64K

ÁÁÁ

ÁÁÁ

1K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

TMS370C758A,

TMS370C758B

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

32K

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

64K

ÁÁÁ

Á

Á

Á

ÁÁÁ

1K

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

256

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

FN – PLCC / NM –PSDIP

TMS370Cx59: TMS370C059 AND TMS370C759

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C059A§

ÁÁÁ

ÁÁÁ

48K

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

20K

ÁÁÁ

ÁÁÁ

3.5K

ÁÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C759A§

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

48K

ÁÁÁÁÁ

ÁÁÁÁÁ

20K

ÁÁÁ

ÁÁÁ

3.5K

ÁÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN – PLCC

EPROM DEVICE: SE370C756, SE370C758, and SE370C759

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

SE370C756A¶

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

16K

ÁÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

ÁÁÁ

512

ÁÁÁÁ

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FZ – CLCC / JN –CSDIP

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

SE370C758A¶,

SE370C758B¶

ÁÁÁ

Á

Á

Á

ÁÁÁÁ

Á

ÁÁ

Á

32K

ÁÁÁÁÁ

Á

ÁÁÁ

Á

64K

ÁÁÁ

Á

Á

Á

1K

ÁÁÁÁ

Á

ÁÁ

Á

256

ÁÁÁ

Á

Á

Á

ÁÁÁ

Á

Á

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

FZ – CLCC / JN –CSDIP

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

SE370C759A§¶

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

48K

ÁÁÁÁÁ

ÁÁÁÁÁ

20K

ÁÁÁ

ÁÁÁ

3.5K

ÁÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FZ – CLCC

µ

C – Microcomputer mode

µ

P – Microprocessor mode

‡ TMS370C45x support ROM memory security. Refer to the program ROM section.

§ Only operate up to 3 MHz SYSCLK

¶ System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

6

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

description (continued)

The suffix letter (A or B) appended to the device names shown in the device column of Table 2 indicates the

configuration of the device. ROM or an EPROM devices have different configurations as indicated in Table 3.

ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 3. Suffix Letter Configuration

DEVICE†

WATCHDOG TIMER

CLOCK

LOW-POWER MODE

EPROM A

Standard

Divide-by-4 (Standard oscillator)

Enabled

EPROM B

Hard

Divide-by-1 (PLL)

Enabled

Standard

ROM A

Hard

Divide-by-4 or Divide-by-1 (PLL)

Enabled or disabled

Simple

ROM-less A

Standard

Divide-by-4

Enabled

† Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.

Unless otherwise noted, the terms TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58,

TMS370Cx59, and SE370C75x refer to the individual devices listed in Table 2 and described in this data sheet.

All TMS370Cx5x devices contain the following on-chip peripheral modules:

D

Eight-channel, 8-bit analog-to-digital converter 1 (ADC1)

D

Serial communications interface 1 (SCI1)

D

Serial peripheral interface (SPI)

D

One 24-bit general-purpose watchdog timer

D

Two 16-bit general-purpose timers (one with an 8-bit prescaler)

TMS370C756, TMS370C758, and TMS370C759 are one-time programmable (OTP) devices that are available

in plastic packages. This microcomputer is effective to use for immediate production updates for other members

of the TMS370Cx5x family or for low-volume production runs when the mask charge or cycle time for low-cost

mask ROM devices is not practical.

The SE370C756, SE370C758, and SE370C759 have windowed ceramic packages to allow reprogramming of

the program EPROM memory during the development / prototyping phase of design. The SE370C75x devices

allow quick updates to breadboards and prototype systems while iterating initial designs.

The TMS370Cx5x family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no

instructions are executed). In the STANDBY mode, the internal oscillator and the general-purpose timer remain

active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral

configuration bits throughout both low-power modes.

The TMS370Cx5x features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370Cx5x family is fully

instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller

family.

The SPI and the two operational modes of the SCI1 give three methods of serial communications. The SCI1

allows standard RS-232-C communications interface between other common data transmission equipment,

while the SPI gives high-speed communications between simpler shift-register type devices, such as display

drivers, ADC1 converter, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

7

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

description (continued)

For large memory applications, the TMS370Cx5x family provides an external bus with non-multiplexed address

and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system

implementations. Wait-state support facilitates performance matching among the CPU, external memory, and

the peripherals. All pins associated with memory expansion interface are individually software configurable for

general purpose digital input/output (I / O) pins when operating in the microcomputer mode.

The TMS370Cx5x family provides the system designer with very economical, efficient solution to real-time

control applications. The TMS370 family extended development system (XDS

) and compact development

tool (CDT

) solve the challenge of efficiently developing the software and hardware required to design the

TMS370Cx5x into an ever-increasing number of complex applications. The application source code can be

written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family

XDS development tools communicate through a standard RS-232-C interface with an existing personal

computer. This allows the use of the personal computer editors and software utilities already familiar to the

designer. The TMS370 family XDS emphasizes ease-of-use through extensive use of menus and screen

windowing so that a system designer with minimal training can begin developing software. Precise real-time

in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware

implementation as well as reduced time-to-market cycle.

The TMS370Cx5x family together with the TMS370 family XDS/22, CDT370, design kit, starter kit, software

tools, the SE370C75x reprogrammable devices, comprehensive product documentation, and customer support

provide a complete solution to the needs of the system designer.

modes

The TMS370Cx5x has four operating modes, two basic modes with each mode having two memory

configurations. The basic operating modes are the microcomputer and microprocessor modes, which are

selected by the voltage level applied to the dedicated MC pin two cycles before RESET goes inactive. The two

memory configurations then are selected through software programming of the internal system configuration

registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion,

microprocessor without internal program memory, and microprocessor with internal program memory. These

modes are described in the following list.

D

Microcomputer single chip mode:

Operates as a self-contained microcomputer with all memory and peripherals on-chip.

Maximizes the general-purpose I/O capability for real-time control applications.

D

Microcomputer with external expansion mode:

Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM,

EPROM, and data EEPROM) remains active.

Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port

control, to become external memory as follows:

Port A: 8-bit data memory

Port B and C: 16-bit address memory

Port D: 8-bit control memory (pin not used as function A or B can be configured as I/O)

Utilizes the pins available (not used for address, data, or control memory) as general-purpose

input/output by programming them individually.

Lowers the system cost by not requiring an external address/data latch (address memory and data

memory are nonmultiplexed).

XDS and CDT are trademarks of Texas Instruments Incorporated.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

8

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

modes (continued)

Reduces external interface decode logic by using the precoded chip select outputs that provide direct

memory/peripheral chip select or chip enable functions.

Function A maps up to 112K bytes of external memory into the address space by using CSE1, CSE2,

CSH1, CSH2, and CSH3 as memory-bank selects under software control.

Function B maps up to 40K bytes of external memory into the address space by using EDS under

software control.

D

Microprocessor without internal program memory mode:

Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses

for interface to external memory and peripherals.

On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled.

Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations.

D

Microprocessor with internal program memory mode:

Configured as the microprocessor without internal program memory mode with respect to the external

bus interface.

Application program in external memory enables the internal program ROM or EPROM to be active in

the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control

register accomplishes this.)

memory/peripheral wait operation

The TMS370Cx5x enhances interface flexibility by providing WAIT-state support, decoupling the cycle time of

the CPU from the read/write access of the external memory or peripherals. External devices can extend the

read/write accesses indefinitely by placing an active low on the WAIT-input pin. The CPU continues to wait as

long as WAIT remains active.

Programmable automatic wait-state generation also is provided by the TMS370Cx5x on-chip bus controller.

Following a hardware reset, the TMS370Cx5x is configured to add one wait state to all external bus transactions

and memory and peripheral accesses automatically, thus making every external access a minimum of three

system-clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE

bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended

independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait

states

 

can be used in conjunction with the external WAIT pin. In applications where the external device

read/write access can interface with the TMS370Cx5x CPU using one wait state, the automatic wait-state

generation can eliminate external WAIT interface logic, lowering system cost.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

9

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

CPU

The CPU used on TMS370Cx5x devices is the high-performance 8-bit TMS370 CPU module. The ’x5x

implements an efficient register-to-register architecture that eliminates the conventional accumulator

bottleneck. The complete ’x5x instruction set is summarized in Table 23. Figure 1 illustrates the CPU registers

and memory blocks.

0000h

0200h

0400h

1000h

10C0h

1100h

1F00h

Interrupts and Reset Vectors;

Trap Vectors

0600h

FFFFh

0

RAM (Includes 256-Byte Registers File)

0

15

Program Counter

7

Legend:

Z=Zero

IE1=Level1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level2 interrupts Enable

IE1

IE2

Z

N

C

0

1

2

3

4

5

6

7

V

Status Register (ST)

Stack Pointer (SP)

R0(A)

R1(B)

R3

R127

0000h

0001h

0002h

007Fh

R255

0003h

R2

00FFh

Reserved†

16K-Byte ROM / EPROM (4000h – 7FFFh)

1E00h

0100h

0E00h

12K-Byte ROM (5000h – 7FFFh)

8K-Byte ROM (6000h – 7FFFh)

32K-Byte ROM / EPROM (2000h – 9FFFh)

48K-Byte ROM / EPROM (2000h – DFFFh)

Memory Expansion

2000h

4000h

5000h

6000h

7000h

7FC0h

8000h

A000h

E000h

256-Byte RAM (0000h – 00FFh)

512-Byte RAM (0000h – 01FFh)

1K-Byte RAM (0000h – 03FFh)

1.5K-Byte RAM (0000h – 05FFh)

3.5K-Byte RAM (0000h – 0DFFh)

Peripheral File

Peripheral Exp

Reserved†

512-Byte (1E00h – 1FFFh)

Data EEPROM

256-Byte (1F00h – 1FFFh)

4K-Byte ROM (7000h – 7FFFh)

† Reserved means the address space is reserved for future expansion.

Figure 1. Programmer’s Model

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

10

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

CPU (continued)

The ’x5x CPU architecture provides the following components:

D

CPU registers:

A stack pointer that points to the last entry in the memory stack

A status register that monitors the operation of the instructions and contains the global-interrupt-enable

bits

A program counter (PC) that points to the memory location of the next instruction to be executed

D

A memory map that includes :

256-, 512-, 1K-, 1.5K-, or 3.5K-byte general-purpose RAM that can be used for data-memory storage,

program instructions, general-purpose register, or the stack (can be located only in the first 256 bytes)

A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

256- or 512-byte EEPROM module that provides in-circuit programmability and data retention in

power-off conditions

4K-, 8K-, 12K-, 16K-, 32K-, or 48K-byte ROM or 16K-, 32K-, or 48K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. Typically the stack

is used to store the return address on subroutine calls as well as the status-register contents during interrupt

sequences.

The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed

onto the stack and decrements after data is popped from the stack. The stack can be located only in the first

256 bytes of the on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes

four status bits (condition flags) and two interrupt-enable bits:

D

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional-jump instructions) use these status bits to determine program flow.

D

The two interrupt-enable bits control the two interrupt levels.

The ST register, status bit notation, and status bit definitions are shown in Table 4.

Table 4. Status Registers

ÁÁÁÁÁ

ÁÁÁÁÁ

7

ÁÁÁÁÁ

ÁÁÁÁÁ

6

ÁÁÁÁÁ

ÁÁÁÁÁ

5

ÁÁÁÁÁ

ÁÁÁÁÁ

4

ÁÁÁÁÁ

ÁÁÁÁÁ

3

ÁÁÁÁÁ

ÁÁÁÁÁ

2

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

1

ÁÁÁÁÁ

ÁÁÁÁÁ

0

ÁÁÁÁÁ

ÁÁÁÁÁ

C

ÁÁÁÁÁ

ÁÁÁÁÁ

N

ÁÁÁÁÁ

ÁÁÁÁÁ

Z

ÁÁÁÁÁ

ÁÁÁÁÁ

V

ÁÁÁÁÁ

ÁÁÁÁÁ

IE2

ÁÁÁÁÁ

ÁÁÁÁÁ

IE1

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁ

ÁÁÁÁÁ

Reserved

ÁÁÁÁÁ

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

R = read, W = write, 0 = value after reset

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

11

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

CPU (continued)

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists

of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These

registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address.

The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH

(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is

loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of

6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).

Memory

Program Counter (PC)

60

00

PCH

PCL

60

00

0000h

7FFEh

7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx5x architecture is based on the Von Neuman architecture, where the program memory and data

memory share a common address space. All peripheral input/output is memory mapped in this same common

address space. In the expansion mode, external memory peripherals are also memory-mapped into this

common address. As shown in Figure 3, the TMS370Cx5x provides a 16 bit-address range to access internal

or external RAM, ROM, data EEPROM, EPROM input/output pins, peripheral functions, and system-interrupt

vectors.

The peripheral file contains all input/output port control, on- and off-chip peripheral status and control, EPROM,

EEPROM programming, and system-wide control functions. The peripheral file consists of 256 contiguous

addresses located from 1000h to 10FFh. The 256 contiguous addresses are divided logically into 16 peripheral

file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral

control and data information is passed. The TMS370Cx5x has its on-chip peripherals and system control

assigned to peripheral file frames 1 through 7, addresses 1010h through 107Fh.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

12

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

memory map (continued)

Reset

7FFEh–7FFFh

Interrupt 1

7FFCh–7FFDh

Interrupt 2

7FFAh–7FFBh

Interrupt 3

7FF8h–7FF9h

Serial Peripheral I/F

7FF6h–7FF7h

Timer 1

7FF4h–7FF5h

Serial Comm I/F RX 7FF2h–7FF3h

Serial Comm I/F TX

7FF0h–7FF1h

Timer 2A

7FEEh–7FEFh

ADC1

7FECh–7FEDh

7FE0h–7FFBh

Reserved†

7FC0h–7FDFh

Trap 15–0

Vectors

Peripheral File Control

Registers

Reserved†

1080h–108Fh

ADC1 Peripheral

Control

1070h–107Fh

Timer 2A Peripheral

Control

1060h–106Fh

SCI1 Peripheral

Control

1050h–105Fh

Timer 1 Peripheral

Control

1040h–104Fh

SPI Peripheral

Control

1030h–103Fh

Digital Port Control

1020h–102Fh

System Control

1010h–101Fh

1000h–100Fh

Reserved†

External

Reserved†

Ò

Ò

Ò

ŠŠ

ŠŠ

ŠŠ

ÒÒ

ÒÒ

ÒÒ

Š

Š

Š

ÒÒ

ÒÒ

ÒÒ

Š

Š

Š

ŠŠ

ŠŠ

ŠŠ

ÒÒ

ÒÒ

ÒÒ

10C0h

7FC0h

Memory Expansion

48K-Byte ROM

(2000h–DFFFh)

32K-Byte ROM

(2000h–9FFFh)

Interrupts and

Reset Vectors;

Trap Vectors

4K-Byte ROM

(7000h–7FFFh)

8K-Byte ROM

(6000h–7FFFh)

12K-Byte ROM

(5000h–7FFFh)

16K-Byte ROM

(4000h–7FFFh)

256-Byte Data

EEPROM

(1F00h–1FFFh)

512K-Byte Data

EEPROM

(1E00h–1FFFh)

Reserved†

Peripheral Expansion

Peripheral File

Reserved†

3.5K-Byte RAM

(0000h–0DFFh)

1.5K-Byte RAM

(0000h–05FFh)

1K-Byte RAM

(0000h–03FFh)

512-Byte RAM

(0000h–01FFh)

256-Byte RAM

(0000h–00FFh)

(Register File/Stack)

0000h

0100h

0200h

0400h

0E00h

1000h

1100h

1E00h

1F00h

2000h

4000h

6000h

7000h

8000h

A000h

E000h

FFFFh

0600h

5000h

Ú

Ú

Ú

Ú

Ú

ÛÛ

ÛÛ

ÛÛ

Ü

Ü

Ü

’X50

Ò

Ò

ŠŠ

ŠŠ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

Ú

Ú

Ú

ÛÛ

ÛÛ

ÛÛ

ÛÛ

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Microprocessor Mode¶

’X52

’X53

’X56

’X58

’X59

Reserved†

External

Reserved†

ÒÒ

ÒÒ

ÒÒ

ÒÒ

ÒÒ

Š

Š

Š

Š

Š

Š

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

Ú

Ú

Ú

Ú

Ú

Ú

Ú

Ú

Ú

Ú

Ú

Ú

Ú

Ú

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

’X50

ÒÒ

ÒÒ

Š

Š

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

Ú

Ú

Ú

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

Microprocessor With

Internal Program

Memory

’X52

’X53

’X56

’X58

’X59

Reserved†

External

Reserved†

Reserved†

Reserved†

’X59

’X58

’X56

’X53

’X52

Microcomputer

Mode With External

Expansion

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

Û

Û

Û

Û

ÚÚ

ÚÚ

ÚÚ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

Š

Š

ÒÒ

ÒÒ

’X50

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

ÜÜ

Û

Û

Û

Û

Û

Û

Û

Û

Û

Û

Û

Û

Û

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

ÙÙ

Š

Š

Š

Š

Š

Š

ÒÒ

ÒÒ

ÒÒ

ÒÒ

ÒÒ

5000h

ÒÒ

ÒÒ

ÒÒ

ÒÒ

ÒÒ

ŠŠ

ŠŠ

ŠŠ

ŠŠ

ŠŠ

ŠŠ

Ù

Ù

Ù

Ù

Ù

Ù

Ù

Ù

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÚÚ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Ü

’X50

0600h

ÒÒ

ÒÒ

ŠŠ

ŠŠ

Ù

Ù

Ù

Ù

Ù

Ù

ÚÚ

ÚÚ

ÚÚ

ÛÛ

ÛÛ

ÛÛ

ÛÛ

Ü

Ü

Ü

Ü

Ü

Ü

Ü

Microcomputer

Single Chip Mode

FFFFh

E000h

A000h

8000h

7000h

6000h

4000h

2000h

1F00h

1E00h

1100h

10C0h

1000h

0E00h

0400h

0200h

0100h

0000h

’X52

’X53

’X56

’X58

’X59

Not Available‡

Not Avail-

able‡

(N / A)

Reserved†

ÒÒ

ÙÙ

ŠŠ

ÚÚ

ÛÛ

ÜÜ

On-Chip For TMS370Cx59 Devices

On-Chip For TMS370Cx58 Devices

On-Chip For TMS370Cx56 Devices

On-Chip For TMS370Cx53 Devices

On-Chip For TMS370Cx52 Devices

On-Chip For TMS370Cx50 Devices

Ü

Ü

ÛÛ

ÛÛ

ÚÚ

ÚÚ

Ù

Ù

ÒÒ

ÒÒ

ŠŠ

ŠŠ

ÜÜ

ÜÜ

Û

Û

ÚÚ

ÚÚ

ÙÙ

ÙÙ

ÒÒ

ÒÒ

Š

Š

ÜÜ

ÜÜ

ÛÛ

ÛÛ

Ú

Ú

ÙÙ

ÙÙ

ÒÒ

ÒÒ

Š

Š

Ü

Ü

ÛÛ

ÛÛ

Ú

Ú

ÙÙ

ÙÙ

Ò

Ò

ŠŠ

ŠŠ

N / A‡

N / A‡

N / A‡

External

External§

External

External§

External§

† Reserved = the address space is reserved for future expansion.

‡ Not available (N /A) = address space unavailable in the mode illustrated.

§ Precoded chip select outputs available on external expansion bus.

¶ Microprocessor mode is designed for ROM-less devices (’x50 and ’x56). ROM and EPROM devices can also be used in this mode but all on-chip

memory is ignored.

Figure 3. TMS370Cx5x Memory Map

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

13

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

RAM / register file (RF)

Locations within RAM address space can serve as either register file or general-purpose read/write memory,

program memory, or stack instructions. The TMS370Cx50 and TMS370Cx52 devices contain 256 bytes of

internal RAM, mapped beginning at location 0000h and continuing through location 00FFh which is shown in

Table 5 along with other ’x5x devices.

Table 5. RAM Memory Map

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

‘x50 and ‘x52

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

‘x56

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

‘x58

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

‘x53

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

‘x59

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

RAM Size

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

256 Bytes

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

512 Bytes

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1K Bytes

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

1.5K Bytes

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

3.5K Bytes

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

Memory Mapped

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

0000h – 00FFh

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

0000h – 01FFh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

0000h – 03FFh

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

0000h – 05FFh

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

0000h – 0DFFh

The first 256 bytes of RAM (0000h – 00FFh) are register files, R0 through R255 (see Figure 1). The first two

registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A

or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer

is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx5x control registers contain all the registers necessary to operate the system and peripheral

modules on the device. The instruction set includes some instructions that access the PF directly. These

instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal

designator or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at

address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 6

shows the TMS370Cx5x peripheral files.

Table 6. TMS370Cx5x Peripheral File Address map

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

ADDRESS RANGE

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

PERIPHERAL FILE

DESIGNATOR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1000h – 100Fh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P000 – P00F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved for factory test

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1010h – 101Fh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P010 – P01F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

System and EEPROM/EPROM control registers

ÁÁÁÁÁÁÁ

1020h – 102Fh

ÁÁÁÁÁÁÁ

P020 – P02F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Digital I/O port control registers

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1030h – 103Fh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P030 – P03F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Serial peripheral interface registers

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1040h – 104Fh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P040 – P04F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Timer 1 registers

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1050h – 105Fh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P050 – P05F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Serial communication interface 1 registers

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1060h – 106Fh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P060 – P06F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Timer 2A registers

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1070h – 107Fh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P070 – P07F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Analog-to-digital converter 1 registers

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

1080h – 10BFh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P080 – P0BF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

10C0h – 10FFh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

P0C0 – P0FF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

External peripheral control

data EEPROM

The TMS370Cx56 devices contain 512 bytes of data EEPROM, which are memory mapped beginning at

location 1E00h and continuing through location 1FFFh as shown in Table 7 along with other ‘x5x devices.

Table 7. Data-EEPROM Memory Map

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

‘x50, ‘x52, ‘x58, and ‘x59

ÁÁÁÁÁÁÁÁÁÁÁ

‘x56

ÁÁÁÁÁÁÁ

‘X53

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Data-EEPROM Size

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

256 Bytes

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

512 Bytes

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

None

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Memory Mapped

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

1F00h – 1FFFh

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

1E00h – 1FFFh

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

None

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

14

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

data EEPROM (continued)

Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the

write-protection register (WPR). Programming algorithm examples are available in the 

TMS370 Family User’s

Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). The

data EEPROM features include the following:

D

Programming:

Bit, byte, and block write/erase modes

Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.

Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A.

In-circuit programming capability: There is no need to remove the device to program it.

D

Write-protection: Writes to the data EEPROM are disabled during the following conditions:

Reset: All programming of the data EEPROM module is halted.

Write protection active: There is one write-protect bit per 32-byte EEPROM block.

Low-power mode operation

D

Write protection can be overridden by applying 12 V to MC.

Table 8 shows the memory map of the control registers.

Table 8. Data EEPROM and Program EPROM Control Registers Memory Map

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ADDRESS

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

SYMBOL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

NAME

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P014

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

EPCTLH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Program EPROM control register – high array

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P015 – P016

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P017

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

INT1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

External interrupt 1 control register

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P018

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

INT2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

External interrupt 2 control register

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P019

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

INT3

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

External interrupt 3 control register

ÁÁÁÁÁÁÁÁ

P01A

ÁÁÁÁÁÁÁÁ

DEECTL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data EEPROM control register

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P01B

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P01C

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

EPCTLM

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Program EPROM control register – middle array

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P01D

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

P01E

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

EPCTLL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Program EPROM control register – low array

For the 16K-byte EPROM device, program memory is controlled by P01C; for the 32K-byte EPROM device,

the program memory is controlled by P01C and P01E; for the 48K-byte EPROM device, the program memory

is controlled by P014, P01C, and P01E.

program EPROM

The ‘370C756 consists of a 16K-byte array of EPROM at address locations 4000h through 7FFFh. The

‘370C758 consists of 32K bytes made up of two 16K-byte arrays of EPROM; the first 16K-bytes array is located

at address locations 2000h through 5FFFh, and the second 16K byte array is located at address locations 6000h

through 9FFFh. The ’370C759 consists of 48K bytes that is made up of three 16K byte arrays of EPROM; the

first 16K bytes array is located at address locations 2000h through 5FFFh, the second 16K-byte array is located

at address locations 6000h through 9FFFh, the third 16K-byte array is located at address locations A000h

through DFFFh (see Figure 3).

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

15

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

program EPROM

 

(continued)

The EPROM memory map in Table 9 expresses the following:

D

The programming control register for program EPROM (EPCTLM) for 16K-byte EPROM is located at

address 101Ch (P01C).

D

For the 32K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the

second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C).

D

For the 48K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the

second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C); the third 16K-byte array is

controlled by EPCTLH, located at 1014h (P014).

Table 9. EPROM Memory Map

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

’756

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

’758

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

’759

ÁÁÁÁÁ

ÁÁÁÁÁ

EPROM size

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

16K Bytes

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

32K Bytes

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

48K Bytes

ÁÁÁÁÁ

ÁÁÁÁÁ

Memory Mapped

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

16K

4000h – 7FFFh

ÁÁÁÁÁ

ÁÁÁÁÁ

First 16K

2000h – 5FFFh

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

Second 16K

6000h – 9FFFh

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

First 16K

2000h – 5FFFh

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

Second 16K

6000h – 9FFFh

ÁÁÁÁÁ

ÁÁÁÁÁ

Third 16K

A000h – DFFFh

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Contol Registers

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

EPCTLM

P01C

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

EPCTLL

P01E

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

EPCTLM

P01C

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

EPCTLL

P01E

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

EPCTLM

P01C

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

EPCTLH

P014

Reading the program-EPROM modules is identical to reading other internal memory. During programming, the

EPROM is controlled by the EPCTL. The program EPROM modules’ features include:

D

Programming

In-circuit programming capability if V

PP

 is applied to MC

Control register: Program EPROM programming is controlled by the program EPROM control registers

(EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 8.

Programming one EPROM module while executing the other

D

Write protection: Writes to the program EPROM are disabled under the following conditions:

Reset: All programming to the EPROM module is halted.

Low-power modes

13 V not applied to MC

program ROM

The program ROM consists of 4K to 48K bytes of mask-programmable ROM. The program ROM is used for

permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device

fabrication. ROM security is a feature of the ‘45x devices, which inhibits reading of the data using the

programmer.

Table 10. ROM Memory Map

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

‘x50

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

‘x52

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

‘x53

ÁÁÁÁÁ

ÁÁÁÁÁ

‘x56

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

‘x58

ÁÁÁÁÁ

ÁÁÁÁÁ

‘x59

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ROM Size

ÁÁÁÁÁ

ÁÁÁÁÁ

4K Bytes

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

8K Bytes

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

12K Bytes

ÁÁÁÁÁ

ÁÁÁÁÁ

16K Bytes

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

32K Bytes

ÁÁÁÁÁ

ÁÁÁÁÁ

48K Bytes

ÁÁÁÁÁÁ

Memory Mapped

ÁÁÁÁÁ

7000h – 7FFFh

ÁÁÁÁÁÁ

6000h – 7FFFh

ÁÁÁÁÁÁ

5000h – 7FFFh

ÁÁÁÁÁ

4000h – 7FFFh

ÁÁÁÁÁÁ

3000h – 9FFFh

ÁÁÁÁÁ

2000h – DFFFh

† Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI

), and addresses 7FECh through 7FFFh are reserved for

interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh.

TI is a trademark of Texas Instruments Incorporated.

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

16

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx5x CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

internally generated, while one (RESET) is controlled externally. These actions are as follows:

D

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key

register, or if the re-initialization does not occur before the watchdog timer timeout . See the 

TMS370 User’s

Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B)

for more information.

D

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See

the 

TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature

number SPNS014B) for more information.

D

External RESET Pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number

SPNS014B) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x5x device to reset external system components. Additionally, if a cold-start condition

(V

CC 

is off for several hundred milliseconds) occurs, oscillator failure occurs, or RESET pin is held low, then the

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag

(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source

of the reset. A reset does not clear these flags. Table 11 lists the reset sources.

Table 11. Reset Sources

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

REGISTER

ÁÁÁÁÁ

ÁÁÁÁÁ

ADDRESS

ÁÁÁÁÁ

ÁÁÁÁÁ

PF

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT NO.

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

CONTROL BIT

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

SOURCE OF RESET

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

SCCR0

ÁÁÁÁÁ

ÁÁÁÁÁ

1010h

ÁÁÁÁÁ

ÁÁÁÁÁ

P010

ÁÁÁÁÁ

ÁÁÁÁÁ

7

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

COLD START

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Cold (power-up)

ÁÁÁÁÁÁ

SCCR0

ÁÁÁÁÁ

1010h

ÁÁÁÁÁ

P010

ÁÁÁÁÁ

4

ÁÁÁÁÁÁÁÁÁ

OSC FLT FLAG

ÁÁÁÁÁÁÁÁÁ

Oscillator out of range

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

T1CTL2

ÁÁÁÁÁ

ÁÁÁÁÁ

104Ah

ÁÁÁÁÁ

ÁÁÁÁÁ

P04A

ÁÁÁÁÁ

ÁÁÁÁÁ

5

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

WD OVRFL INT FLAG

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1.

The CPU registers initialize: ST = 00h, SP = 01h (reset state).

2.

Registers A and B initialize to 00h (no other RAM is changed).

3.

The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4.

The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5.

Program execution begins with an opcode fetch from the address pointed to by the PC.

The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control

register bits are initialized to their reset state. During RESET, the two basic operating modes which are the

microcomputer and microprocessor modes can be selected by applying the desired voltage level to the

dedicated MC pin two cycles before RESET goes inactive (refer to page 7 for operating modes description).

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

17

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt

configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure

incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt

level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of

the status register.

Each system interrupt is configured independently to either the high- or low-priority chain by the application

program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of

the system interrupt. However, since each system interrupt is configured selectively on either the high- or

low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.

Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending

interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and

priority conditions.

The TMS370Cx5x has nine hardware system interrupts (plus RESET) as shown in Table 12. Each system

interrupt has a dedicated vector located in program memory through which control is passed to the interrupt

service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt

sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the

associated PF. Each interrupt source FLAG bit is individually readable for software polling or determining which

interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in

Figure 4.

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

18

POST OFFICE BOX 1443 

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interrupts (continued)

TIMER 2A

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT

Level 2 INT

T2A PRI

Priority

Overflow

Compare1

Ext Edge

Compare2

Input Capture 1

Input Capture 2

EXT INT 3

INT3 PRI

INT 3

STATUS REG

EXT INT1

INT1 PRI

INT1

SPI INT

SPI PRI

SPI

EXT INT 2

INT2 PRI

INT 2

AD INT

AD PRI

A / D

TIMER 1

T1 PRI

Overflow

Compare1

Ext Edge

Compare2

Input Capture 1

Watchdog

SCI INT

RX

BRKDT

RXRDY

TX

TXRDY

TXPRI

RXPRI

Figure 4. Interrupt Control

On-chip peripheral functions generate six of the system interrupts. Three external interrupts also are supported.

Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers

in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling

edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or

non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or

global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should

be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts

INT2 and INT3 can be software configured as general purpose input/output pins if the interrupt function is not

required (INT1 can be similarly configured as an input pin). Table 12 shows the interrupt vector sources,

corresponding addresses, and hardware priorities.

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

19

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

interrupts (continued)

Table 12. Hardware System Interrupts

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

INTERRUPT SOURCE

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

INTERRUPT FLAG

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

SYSTEM

INTERRUPT

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

VECTOR

ADDRESS

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

PRIORITY†

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

External RESET

Watchdog overflow

Oscillator fault detect

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

COLD START

WD OVRFL INT FLAG

OSC FLT FLAG

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

RESET‡

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

7FFEh, 7FFFh

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

1

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

External INT1

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

INT1 FLAG

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

INT1‡

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

7FFCh, 7FFDh

ÁÁÁÁÁ

ÁÁÁÁÁ

2

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

External INT2

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

INT2 FLAG

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

INT2‡

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

7FFAh, 7FFBh

ÁÁÁÁÁ

ÁÁÁÁÁ

3

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

External INT3

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

INT3 FLAG

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

INT3‡

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

7FF8h, 7FF9h

ÁÁÁÁÁ

ÁÁÁÁÁ

4

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

SPI RX/TX complete

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

SPI INT FLAG

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

SPIINT

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

7FF6h, 7FF7h

ÁÁÁÁÁ

ÁÁÁÁÁ

5

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Timer 1 overflow

Timer 1 compare 1

Timer 1 compare 2

Timer 1 external edge

Timer 1 input capture 1

Watchdog overflow

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

T1 OVRFL INT FLAG

T1C1 INT FLAG

T1C2 INT FLAG

T1EDGE INT FLAG

T1IC1 INT FLAG

WD OVRFL INT FLAG

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

T1INT§

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

Á

ÁÁÁÁÁ

Á

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

7FF4h, 7FF5h

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

6

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

SCI RX data register full

SCI RX break detect

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

RXRDY FLAG

BRKDT FLAG

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

RXINT‡

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

7FF2h,7FF3h

ÁÁÁÁÁ

ÁÁÁÁÁ

7

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

SCI TX data register empty

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

TXRDY FLAG

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

TXINT

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

7FF0h, 7FF1h

ÁÁÁÁÁ

ÁÁÁÁÁ

8

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Timer 2A overflow

Timer 2A compare 1

Timer 2A compare 2

Timer 2A external edge

Timer 2A input capture 1

Timer 2A input capture 2

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

T2A OVRFL INT FLAG

T2AC1 INT FLAG

T2AC2 INT FLAG

T2AEDGE INT FLAG

T2AIC1 INT FLAG

T2AIC2 INT FLAG

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

T2AINT

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

Á

ÁÁÁÁÁ

Á

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

7FEEh, 7FEFh

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

9

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

A/D conversion complete

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

AD INT FLAG

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ADINT

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

7FECh, 7FEDh

ÁÁÁÁÁ

ÁÁÁÁÁ

10

† Relative priority within an interrupt level

‡ Releases microcontroller from STANDBY and HALT low-power modes.

§ Releases microcontroller from STANDBY low-power mode.

privileged operation and EEPROM write-protection override

The TMS370Cx5x family has significant flexibility to enable the designer to software-configure the system and

peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation

ensures the integrity of the system configuration, once it is defined for an application. Following a hardware

reset, the TMS370Cx5x operates in the privileged mode, where all peripheral file registers have unrestricted

read/write access, and the application program configures the system during the initialization sequence

following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set

to 1 to enter the nonprivileged mode; disabling write operations to specific configuration control bits within the

peripheral file. Table 13 displays the system configuration bits that are write-protected during the nonprivileged

mode and must be configured by software prior to exiting the privileged mode.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

20

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

privileged operation and EEPROM write-protection override (continued)

Table 13. Privileged Bits

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

REGISTER†

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

CONTROL BIT

ÁÁÁÁ

ÁÁÁÁ

NAME

ÁÁÁÁÁ

ÁÁÁÁÁ

LOCATION

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

CONTROL BIT

ÁÁÁÁ

Á

ÁÁÁ

ÁÁÁÁ

SCCRO

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

P010.5

P010.6

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

PF AUTOWAIT

OSC POWER

ÁÁÁÁ

ÁÁÁÁ

SCCR1

ÁÁÁÁÁ

ÁÁÁÁÁ

P011.2

P011.4

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

MEMORY DISABLE

AUTOWAIT DISABLE

ÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

ÁÁÁÁ

SCCR2

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN/IDLE

HALT/STANDBY

ÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

ÁÁÁÁ

SPIPRI

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

P03F.5

P03F.6

P03F.7

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

SPI ESPEN

SPI PRIORITY

SPI STEST

ÁÁÁÁ

Á

ÁÁÁ

ÁÁÁÁ

SCIPRI

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

P05F.4

P05F.5

P05F.6

P05F.7

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

SCI ESPEN

SCIRX PRIORITY

SCITX PRIORITY

SCI STEST

ÁÁÁÁ

Á

ÁÁÁ

ÁÁÁÁ

T1PRI

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

P04F.6

P04F.7

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

T1 PRIORITY

T1 STEST

ÁÁÁÁ

Á

ÁÁÁ

ÁÁÁÁ

T2APRI

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

P06F.6

P06F.7

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

T2A PRIORITY

T2A STEST

ÁÁÁÁ

Á

ÁÁÁ

ÁÁÁÁ

ADPRI

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

P07F.5

P07F.6

P07F.7

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

AD ESPEN

AD PRIORITY

AD STEST

† The privileged bits are shown in a bold typeface in Table 15.

The write-protect override (WPO) mode provides an external hardware method for overriding the

write-protection registers of data EEPROM on the TMS370Cx5x. The WPO mode is entered by applying a 12-V

input to MC after RESET input goes high (logic 1). The high voltage on MC during the WPO mode is not the

programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages are

generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data

EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC

pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx5x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time when the mask is manufactured.

The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The

HALT / STANDBY bit in SCCR2 controls which low-power mode is entered.

In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;

however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial

communications interface remain active. System processing is suspended until a qualified interrupt (hardware

RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial

communications interface 1) is detected.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

21

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

low-power and IDLE modes (continued)

In the HALT mode (HALT/STANDBY = 1), the TMS370Cx5x is placed in its lowest power consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level

on the receive pin of the serial communications interface 1) is detected. The low-power mode selection bits are

summarized in Table 14.

Table 14. Low-Power/Idle Control Bits

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

POWER-DOWN CONTROL BITS

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

PWRDWN/IDLE

(SCCR2.6)

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

HALT/STANDBY

(SCCR2.7)

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

MODE SELECTED

ÁÁÁÁÁ

ÁÁÁÁÁ

1

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

0

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

STANDBY

ÁÁÁÁÁ

ÁÁÁÁÁ

1

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

1

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

HALT

ÁÁÁÁÁ

ÁÁÁÁÁ

0

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

X

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6–7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This

means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status

registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the

STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ‘x5x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard

oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of

a TMS370 microcontroller. The ‘x5x ROM-masked devices offer both options to meet system engineering

requirements. Only one of the two clock options is allowed on each ROM device. The ‘75xA EPROM has only

the standard divide-by-4, while the ‘75xB EPROM has the divide-by-1.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 provides a 1-to-1 match of the external resonator frequency to the internal system clock

(SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external

resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock

module then divides the resulting signal by four to provide the four-phased internal system clock signals. The

resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows

Divide-by-4 option : SYSCLK

+

external resonator frequency

4

+

CLKIN

4

Divide-by-1 option : SYSCLK

+

external resonator frequency

 

4

4

+

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of

low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators.

The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a

steeper decay of emissions produced by the oscillator.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

22

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

system configuration registers

Table 15 contains system configuration and control functions and registers for controlling EEPROM

programming. The privileged bits are shown in a bold typeface and shaded.

Table 15. Peripheral File Frame 1: System Configuration Registers

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

PF

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 7

ÁÁÁÁ

ÁÁÁÁ

BIT 6

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 5

ÁÁÁÁ

ÁÁÁÁ

BIT 4

ÁÁÁÁ

ÁÁÁÁ

BIT 3

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 2

ÁÁÁÁ

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

ÁÁÁÁ

REG

ÁÁÁ

Á

Á

Á

ÁÁÁ

P010

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

COLD

START

OSC

POWER

PF AUTO

WAIT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

OSC FLT

FLAG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

MC PIN

WPO

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

MC PIN

DATA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

µ

P

/

µ

C

MODE

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCCR0

ÁÁÁ

ÁÁÁ

P011

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

AUTOWAIT

DISABLE

ÁÁÁÁ

ÁÁÁÁ

MEMORY

DISABLE

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

SCCR1

ÁÁÁ

Á

Á

Á

ÁÁÁ

P012

HALT/

STANDBY

PWRDWN/

IDLE

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

BUS

STEST

CPU

STEST

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INT1

NMI

PRIVILEGE

DISABLE

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCCR2

ÁÁÁ

ÁÁÁ

P013

Reserved

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

P014

ÁÁÁÁÁ

ÁÁÁÁÁ

BUSY

ÁÁÁÁ

ÁÁÁÁ

VPPS

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

W0

ÁÁÁÁÁ

ÁÁÁÁÁ

EXE

ÁÁÁÁ

ÁÁÁÁ

EPCTLH

ÁÁÁ

Á

Á

Á

ÁÁÁ

P015

to

P016

Reserved

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

P017

ÁÁÁÁÁ

ÁÁÁÁÁ

INT1

FLAG

ÁÁÁÁ

ÁÁÁÁ

INT1

PIN DATA

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

INT1

POLARITY

ÁÁÁÁ

ÁÁÁÁ

INT1

PRIORITY

ÁÁÁÁÁ

ÁÁÁÁÁ

INT1

ENABLE

ÁÁÁÁ

ÁÁÁÁ

INT1

ÁÁÁ

Á

Á

Á

ÁÁÁ

P018

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INT2

FLAG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT2

PIN DATA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT2

DATA DIR

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT2

DATA OUT

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INT2

POLARITY

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT2

PRIORITY

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INT2

ENABLE

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT2

ÁÁÁ

Á

Á

Á

ÁÁÁ

P019

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INT3

FLAG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT3

PIN DATA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT3

DATA DIR

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT3

DATA OUT

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INT3

POLARITY

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT3

PRIORITY

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INT3

ENABLE

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

INT3

ÁÁÁ

P01A

ÁÁÁÁÁ

BUSY

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

AP

ÁÁÁÁ

W1W0

ÁÁÁÁÁ

EXE

ÁÁÁÁ

DEECTL

ÁÁÁ

ÁÁÁ

P01B

Reserved

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

P01C

ÁÁÁÁÁ

ÁÁÁÁÁ

BUSY

ÁÁÁÁ

ÁÁÁÁ

VPPS

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

W0

ÁÁÁÁÁ

ÁÁÁÁÁ

EXE

ÁÁÁÁ

ÁÁÁÁ

EPCTLM

ÁÁÁ

ÁÁÁ

P01D

Reserved

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

P01E

ÁÁÁÁÁ

ÁÁÁÁÁ

BUSY

ÁÁÁÁ

ÁÁÁÁ

VPPS

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

W0

ÁÁÁÁÁ

ÁÁÁÁÁ

EXE

ÁÁÁÁ

ÁÁÁÁ

EPCTLL

ÁÁÁ

ÁÁÁ

P01F

Reserved

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

23

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 16 lists the specific

addresses, registers, and control bits within this peripheral file frame.

Table 16. Peripheral File Frame 2: Digital Port Control Registers

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

PF

ÁÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 6

ÁÁÁÁ

ÁÁÁÁ

BIT 5

ÁÁÁÁ

ÁÁÁÁ

BIT 4

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 3

ÁÁÁÁ

ÁÁÁÁ

BIT 2

ÁÁÁÁ

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

ÁÁÁÁ

REG

ÁÁÁ

ÁÁÁ

P020

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

ÁÁÁÁ

APORT1

ÁÁÁ

ÁÁÁ

P021

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Control Register 2

ÁÁÁÁ

ÁÁÁÁ

APORT2

ÁÁÁ

ÁÁÁ

P022

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Data

ÁÁÁÁ

ÁÁÁÁ

ADATA

ÁÁÁ

ÁÁÁ

P023

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Direction

ÁÁÁÁ

ÁÁÁÁ

ADIR

ÁÁÁ

ÁÁÁ

P024

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

ÁÁÁÁ

BPORT1

ÁÁÁ

P025

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port B Control Register 2

ÁÁÁÁ

BPORT2

ÁÁÁ

ÁÁÁ

P026

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port B Data

ÁÁÁÁ

ÁÁÁÁ

BDATA

ÁÁÁ

ÁÁÁ

P027

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port B Direction

ÁÁÁÁ

ÁÁÁÁ

BDIR

ÁÁÁ

ÁÁÁ

P028

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

ÁÁÁÁ

CPORT1

ÁÁÁ

ÁÁÁ

P029

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port C Control Register 2

ÁÁÁÁ

ÁÁÁÁ

CPORT2

ÁÁÁ

ÁÁÁ

P02A

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port C Data

ÁÁÁÁ

ÁÁÁÁ

CDATA

ÁÁÁ

ÁÁÁ

P02B

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port C Direction

ÁÁÁÁ

ÁÁÁÁ

CDIR

ÁÁÁ

ÁÁÁ

P02C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port D Control Register 1

ÁÁÁÁ

ÁÁÁÁ

DPORT1

ÁÁÁ

ÁÁÁ

P02D

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port D Control Register 2†

ÁÁÁÁ

ÁÁÁÁ

DPORT2

ÁÁÁ

P02E

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port D Data

ÁÁÁÁ

DDATA

ÁÁÁ

ÁÁÁ

P02F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port D Direction

ÁÁÁÁ

ÁÁÁÁ

DDIR

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

† To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

24

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

digital port control registers (continued)

Table 17. Port Configuration Register Setup

INPUT

OUTPUT

FUNCTION A

FUNCTION B

(

µ

P MODE)

PORT

PIN

XPORT1 = 0†

XPORT2 = 0

XDATA = y

XDIR = 0

XPORT1 = 0†

XPORT2 = 0

XDATA = q

XDIR = 1

XPORT1 = 0†

XPORT2 = 1

XDATA = x

XDIR = x

XPORT1 = 1†

XPORT2 = 1

XDATA = x

XDIR = x

A

0 – 7

Data In y

Data Out q

Data Bus

Reserved

B

0 – 7

Data In y

Data Out q

Low ADDR

Reserved

C

0 – 7

Data In y

Data Out q

Hi ADDR

Reserved

D

0

1

2

3

4

5

6

7

Data In y

Data Out q

CSE2

CSH3

CSH2

SYSCLK

R / W

CSPF

CSH1

CSE1

OCF

SYSCLK

R/W

EDS

WAIT

XPORT1 = 1

XPORT2 =0

XDATA = x

XDIR = x

Not defined

† DPORT only

timer 1 module

The programmable timer 1 (T1) module of the TMS370Cx5x provides the designer with the enhanced timer

resources required to perform realtime system control. The T1 module contains the general-purpose timer and

the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock

sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input capture and

compare) for special timer function control. The T1 module includes three external device pins that can be used

for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. T1 module is

shown in Figure 5.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

25

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

T1IC/CR

Edge

Select

16-Bit

Counter

T1EVT

MUX

MUX

16-Bit

Register

T1PWM

PWM

Toggle

16

16-Bit

WatchdogCounter

(Aux. Timer)

Interrupt

Logic

Capt/Comp

16-Bit

Register

Compare

Interrupt

Logic

8-Bit

Prescaler

Figure 5. Timer 1 Block Diagram

D

Three T1 I/O pins:

T1IC/CR: T1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin

T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin

T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin

D

Two operation modes:

Dual-compare mode: Provides PWM signal

Capture/compare mode: Provides input capture pin

D

One 16-bit general-purpose resettable counter

D

One 16-bit compare register with associated compare logic

D

One 16-bit capture / compare register, which, depending on the mode of operation, operates as either a

capture or compare register

D

One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if

watchdog feature is not needed.

D

Prescaler / clock sources that determine one of eight clock sources for general-purpose timer

D

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on

the input capture pins (T1IC/CR)

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

26

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

D

Interrupts that can be generated on the occurrence of:

A capture

A compare equal

A counter overflow

An external edge detection

D

Sixteen T1 module control registers located in the PF frame, beginning at address P040

Table 18 shows the T1 module control register.

Table 18. T1 Module Register Memory Map

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

PF

ÁÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 6

ÁÁÁÁ

ÁÁÁÁ

BIT 5

ÁÁÁÁ

ÁÁÁÁ

BIT 4

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 3

ÁÁÁÁ

ÁÁÁÁ

BIT 2

ÁÁÁÁ

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

ÁÁÁÁ

REG

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Modes: Dual-Compare and Capture/Compare

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

P040

ÁÁÁÁ

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T1 Counter MSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 8

ÁÁÁÁ

ÁÁÁÁ

T1CNTR

ÁÁÁÁ

ÁÁÁÁ

P041

ÁÁÁÁ

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T1 Counter LSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 0

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

P042

ÁÁÁÁ

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Compare Register MSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 8

ÁÁÁÁ

ÁÁÁÁ

T1C

ÁÁÁÁ

ÁÁÁÁ

P043

ÁÁÁÁ

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Compare Register LSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 0

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

P044

ÁÁÁÁ

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Capture/Compare Register MSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 8

ÁÁÁÁ

ÁÁÁÁ

T1CC

ÁÁÁÁ

ÁÁÁÁ

P045

ÁÁÁÁ

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Capture/Compare Register LSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 0

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

P046

ÁÁÁÁ

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Watchdog Counter MSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 8

ÁÁÁÁ

ÁÁÁÁ

WDCNTR

ÁÁÁÁ

ÁÁÁÁ

P047

ÁÁÁÁ

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Watchdog Counter LSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 0

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

P048

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Watchdog Reset Key

ÁÁÁÁÁ

Bit 0

ÁÁÁÁ

WDRST

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

P049

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

WD OVRFL

TAP SEL†

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

WD

INPUT

SELECT2†

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

WD

INPUT

SELECT1†

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

WD

INPUT

SELECT0†

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

T1

INPUT

SELECT2

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

T1

INPUT

SELECT1

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T1 INPUT

SELECT0

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

T1CTL1

ÁÁÁÁ

ÁÁÁÁ

P04A

ÁÁÁÁ

ÁÁÁÁ

WD OVRFL

RST ENA†

ÁÁÁÁÁ

ÁÁÁÁÁ

WD OVRFL

INT ENA

ÁÁÁÁ

ÁÁÁÁ

WD OVRFL

INT FLAG

ÁÁÁÁ

ÁÁÁÁ

T1 OVRFL

INT ENA

ÁÁÁÁÁ

ÁÁÁÁÁ

T1 OVRFL

INT FLAG

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

T1 SW

RESET

ÁÁÁÁ

ÁÁÁÁ

T1CTL2

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode: Dual-Compare

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

P04B

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1EDGE

INT FLAG

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T1C2

INT FLAG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1C1

INT FLAG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1EDGE

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1C2

INT ENA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T1C1

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1CTL3

ÁÁÁÁ

ÁÁÁÁ

P04C

ÁÁÁÁ

ÁÁÁÁ

T1

MODE = 0

ÁÁÁÁÁ

ÁÁÁÁÁ

T1C1

OUT ENA

ÁÁÁÁ

ÁÁÁÁ

T1C2

OUT ENA

ÁÁÁÁ

ÁÁÁÁ

T1C1

RST ENA

ÁÁÁÁÁ

ÁÁÁÁÁ

T1CR

OUT ENA

ÁÁÁÁ

ÁÁÁÁ

T1EDGE

POLARITY

ÁÁÁÁ

ÁÁÁÁ

T1CR

RST ENA

ÁÁÁÁÁ

ÁÁÁÁÁ

T1EDGE

DET ENA

ÁÁÁÁ

ÁÁÁÁ

T1CTL4

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode: Capture/Compare

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

P04B

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1EDGE

INT FLAG

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1C1

INT FLAG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1EDGE

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T1C1

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1CTL3

ÁÁÁÁ

ÁÁÁÁ

P04C

ÁÁÁÁ

ÁÁÁÁ

T1

MODE = 1

ÁÁÁÁÁ

ÁÁÁÁÁ

T1C1

OUT ENA

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

T1C1

RST ENA

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

T1EDGE

POLARITY

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

T1EDGE

DET ENA

ÁÁÁÁ

ÁÁÁÁ

T1CTL4

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Modes: Dual-Compare and Capture/Compare

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

P04D

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T1EVT

DATA IN

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1EVT

DATA OUT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1EVT

FUNCTION

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T1EVT

DATA DIR

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1PC1

ÁÁÁÁ

ÁÁÁÁ

P04E

ÁÁÁÁ

ÁÁÁÁ

T1PWM

DATA IN

ÁÁÁÁÁ

ÁÁÁÁÁ

T1PWM

DATA OUT

ÁÁÁÁ

ÁÁÁÁ

T1PWM

FUNCTION

ÁÁÁÁ

ÁÁÁÁ

T1PWM

DATA DIR

ÁÁÁÁÁ

ÁÁÁÁÁ

T1IC/CR

DATA IN

ÁÁÁÁ

ÁÁÁÁ

T1IC/CR

DATA OUT

ÁÁÁÁ

ÁÁÁÁ

T1IC/CR

FUNCTION

ÁÁÁÁÁ

ÁÁÁÁÁ

T1IC/CR

DATA DIR

ÁÁÁÁ

ÁÁÁÁ

T1PC2

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

P04F

T1 STEST

T1

PRIORITY

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T1PRI

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

† Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard

watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT

SELECT2 bits are ignored.

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

27

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

The T1 capture/compare mode block diagram is illustrated in Figure 6. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,

bit 0, in the T1CTL2 register.

T1CTL4.2

16

Compare=

Edge

Select

T1IC/CR

T1EDGE POLARITY

T1EDGE DET ENA

Prescale

Clock

Source

16-Bit

Counter

MSB

LSB

T1CNTR.15-0

Reset

T1C1

RST ENA

T1 SW

RESET

T1CTL2.0

T1CTL4.4

T1PC2.3-0

T1CTL4.0

T1EDGE INT FLAG

T1EDGE INT ENA

T1CTL3.7

T1CTL3.2

T1 OVRFL INT FLAG

T1 OVRFL INT ENA

T1CTL2.3

T1CTL2.4

T1C1 INT FLAG

T1C1 INT ENA

T1CTL3.5

T1CTL3.0

T1C1

OUT ENA

T1PWM

T1CTL4.6

T

oggle

T1PC2.7-4

16-Bit

Capt/Comp

MSB

LSB

Register

T1CC.15-0

T1C.15-0

16-Bit

Compare

MSB

LSB

Register

T1 PRIORITY

ÏÏÏÏ

T1PRI.6

Level 1 Int

Level  2 Int

0

1

 

Figure 6. Capture/Compare Mode

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

28

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

The T1 dual-compare mode block diagram is illustrated in Figure 7. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,

bit 0, in the T1CTL2 register.

T1CTL4.1

T1CTL4.4

Prescaler

Clock

Source

16-Bit

Counter

16-Bit

16

Compare=

Compare=

Reset

T1C1

RST ENA

T1 SW

RESET

Edge

Select

T1EDGE DET ENA

Output

Enable

Capt/Comp

Register MSB

LSB

MSB

LSB

T1CR OUT ENA

T1IC/CR

T1EDGE POLARITY

T

oggle

16-Bit

Compare

MSB

LSB

Register

T1CC.15-0

T1C1 INT FLAG

T1CTL3.0

T1CTL3.5

T1C1 INT ENA

T1C2 INT FLAG

T1CTL3.1

T1CTL3.6

T1C2 INT ENA

T1 OVRFL INT FLAG

T1CTL2.4

T1CTL2.3

T1 OVRFL INT ENA

T1EDGE INT FLAG

T1CTL3.2

T1CTL3.7

T1EDGE INT ENA

T1 PRIORITY

T1C2 OUT ENA

T1C1 OUT ENA

T1CTL4.3

T1CTL4.6

T1CTL4.5

T1PWM

T1PC2.7-4

T1PRI.6

T1C.15-0

T1CNTR.15-0

T1CTL2.0

T1CR

RST ENA

T1PC2.3-0

T1CTL4.0

T1CTL4.2

Level 1 Int

Level 2 Int

0

1

 

 

Figure 7. Dual-Compare Mode

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

29

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

The TMS370Cx5x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be

software-programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not

desired. The WD function is to monitor software and hardware operation and to implement a system reset when

the WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect

value). The WD can be configured as one of the three mask options: standard watchdog, hard watchdog, or

simple counter.

D

Standard watchdog configuration (see Figure 8) – for ’C75xA EPROM and mask-ROM devices

Watchdog mode

Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

Non-watchdog mode

Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

WD OVRFL

RST ENA

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.7

T1CTL2.5

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

WD OVRFL

INT FLAG

Figure 8. Standard Watchdog

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

30

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

D

Hard watchdog configuration (see Figure 9) – for ‘C75xB EPROM and mask-ROM devices

Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK.

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

Automatic activation of the WD timer upon power-up reset

INT1 is enabled as nonmaskable interrupt during low-power modes

A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVRFL

INT FLAG

Figure 9. Hard Watchdog

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

31

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

D

Simple-counter configuration (see Figure 10) – for mask-ROM devices only

The simple counter can be configured as an event counter, pulse accumulator, or an interval timer

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVFL

INT FLAG

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

Figure 10. Simple Counter

timer 2A module

The 16-bit general-purpose timer 2A (T2A) module is composed of a 16-bit resettable counter, 16-bit compare

register with associated compare logic, 16-bit capture register, and a 16-bit register that functions as a capture

register in one mode and as a compare register in the other mode. The T2A module adds an additional timer

that provides an event count, input capture, and compare functions. The T2A module includes three external

device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2A module is

shown in Figure 11.

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TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

32

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

16–Bit

Register

16

INT

Logic

Capt/Comp 

16–Bit

Capture

Edge

Detect

T2AEVT

PWM

Toggle

T2AIC2/PWM

(Dual-Compare Mode)

Edge

Detect

T2AIC1/CR

T2AIC2/PWM

Register

16–Bit

Register

Compare

16–Bit

Counter

Clock

Select

(Dual-Capture Mode)

Figure 11. Timer 2A Block Diagram

The T2A module features include the following:

D

Three T2A I/O pins:

T2AIC1/CR: T2A input-capture 1 / counter-reset input pin, or general-purpose bidirectional I/O pin

T2AIC2/PWM: T2A input-capture 2 / pulse-width-modulation (PWM) output pin, or general-purpose

bidirectional I/O pin

T2AEVT: Timer 2A event-input pin, or general-purpose bidirectional I/O pin

D

Two operational modes:

Dual-compare mode: Provides PWM signal

Dual-capture mode: Provides input-capture pin

D

One 16-bit general-purpose resettable counter

D

One 16-bit compare register with associated compare logic

D

One 16-bit capture register with associated capture logic

D

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a

capture or compare register

D

T2A clock sources can be any of the following:

System clock

No clock (the counter is stopped)

External clock synchronized to the system clock (event counter)

System clock while external input is high (pulse accumulation)

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

33

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

D

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on

the input capture pins (T2AIC1/CR)

D

Interrupts that can be generated on the occurrence of:

A compare equal to dedicated compare register

A compare equal to capture-compare register

A counter overflow

An external edge 1 detection

An external edge 2 detection

D

Fourteen T2A module-control registers: Located in the PF frame beginning at address P060

The T2A module-control registers are illustrated in Table 19.

Table 19. Timer 2A Module Register Memory Map

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

PF

ÁÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 6

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 5

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 4

ÁÁÁÁ

ÁÁÁÁ

BIT 3

ÁÁÁÁ

ÁÁÁÁ

BIT 2

ÁÁÁÁ

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 0

ÁÁÁ

ÁÁÁ

REG

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Modes: Dual-Compare and Dual-Capture

ÁÁÁ

ÁÁÁ

ÁÁÁ

P060

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T2A Counter MSbyte

ÁÁÁÁÁ

Bit 8

ÁÁÁ

T2ACNTR

ÁÁÁ

ÁÁÁ

P061

ÁÁÁÁ

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T2A Counter LSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 0

ÁÁÁ

ÁÁÁ

T2ACNTR

ÁÁÁ

ÁÁÁ

P062

ÁÁÁÁ

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Compare Register MSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 8

ÁÁÁ

ÁÁÁ

T2AC

ÁÁÁ

ÁÁÁ

P063

ÁÁÁÁ

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Compare Register LSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 0

ÁÁÁ

ÁÁÁ

T2AC

ÁÁÁ

ÁÁÁ

P064

ÁÁÁÁ

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Capture/Compare Register MSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 8

ÁÁÁ

ÁÁÁ

T2ACC

ÁÁÁ

ÁÁÁ

P065

ÁÁÁÁ

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Capture/Compare Register LSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 0

ÁÁÁ

ÁÁÁ

T2ACC

ÁÁÁ

ÁÁÁ

P066

ÁÁÁÁ

ÁÁÁÁ

Bit 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Capture Register 2 MSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 8

ÁÁÁ

ÁÁÁ

T2AIC

ÁÁÁ

ÁÁÁ

P067

ÁÁÁÁ

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Capture Register 2 LSbyte

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 0

ÁÁÁ

ÁÁÁ

T2AIC

ÁÁÁ

Á

Á

Á

ÁÁÁ

P06A

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2A OVRFL

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2A

OVRFL INT

FLAG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2A

INPUT

SELECT1

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2A INPUT

SELECT0

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2A SW

RESET

ÁÁÁ

Á

Á

Á

ÁÁÁ

T2ACTL1

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode: Dual-Compare

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

P06B

ÁÁÁÁ

ÁÁÁÁ

T2AEDGE1

INT FLAG

ÁÁÁÁÁ

ÁÁÁÁÁ

T2AC2

INT FLAG

ÁÁÁÁÁ

ÁÁÁÁÁ

T2AC1

INT FLAG

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

T2AEDGE1

INT ENA

ÁÁÁÁ

ÁÁÁÁ

T2AC2

INT ENA

ÁÁÁÁÁ

ÁÁÁÁÁ

T2AC1

INT ENA

ÁÁÁ

ÁÁÁ

T2ACTL2

ÁÁÁ

Á

Á

Á

ÁÁÁ

P06C

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2A

MODE = 0

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AC1

OUT ENA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AC2

OUT ENA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AC1

RST ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE1

OUT ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE1

POLARITY

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE1

RST ENA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AEDGE1

DET ENA

ÁÁÁ

Á

Á

Á

ÁÁÁ

T2ACTL3

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode: Dual-Capture

ÁÁÁ

ÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

P06B

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE1

INT FLAG

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AEDGE2

INT FLAG

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AC1

INT FLAG

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE1

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE2

INT ENA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AC1

INT ENA

ÁÁÁ

Á

Á

Á

ÁÁÁ

T2ACTL2

ÁÁÁ

Á

Á

Á

ÁÁÁ

P06C

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2A

MODE = 1

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AC1

RST ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE2

POLARITY

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE1

POLARITY

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEDGE2

DET ENA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AEDGE1

DET ENA

ÁÁÁ

Á

Á

Á

ÁÁÁ

T2ACTL3

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Modes: Dual-Compare and Dual-Capture

ÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

P06D

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEVT

DATA IN

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEVT

DATA OUT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

T2AEVT

FUNCTION

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

T2AEVT

DATA DIR

ÁÁÁ

Á

Á

Á

ÁÁÁ

T2APC1

ÁÁÁ

ÁÁÁ

P06E

ÁÁÁÁ

ÁÁÁÁ

T2AIC2 / PWM

DATA IN

ÁÁÁÁÁ

ÁÁÁÁÁ

T2AIC2 / PWM

DATA OUT

ÁÁÁÁÁ

ÁÁÁÁÁ

T2AIC2 / PWM

FUNCTION

ÁÁÁÁÁ

ÁÁÁÁÁ

T2AIC2 / PWM

DATA DIR

ÁÁÁÁ

ÁÁÁÁ

T2AIC1/CR

DATA IN

ÁÁÁÁ

ÁÁÁÁ

T2AIC1/CR

DATA OUT

ÁÁÁÁ

ÁÁÁÁ

T2AIC1/CR

FUNCTION

ÁÁÁÁÁ

ÁÁÁÁÁ

T2AIC1/CR

DATA DIR

ÁÁÁ

ÁÁÁ

T2APC2

ÁÁÁ

Á

Á

Á

ÁÁÁ

P06F

T2A STEST

T2A

PRIORITY

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

T2APRI

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

34

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

The T2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,

bit 0, in the T2ACTL2 register.

T2AC.15-0

T2ACTL2.1

T2ACTL3.2

T2ACTL3.1

T2ACTL3.5

T2ACTL3.3

Clock

Source

16-Bit

Counter

16-Bit

16

Compare=

Compare=

Reset

T2AC1

RST ENA

T2A SW

RESET

Edge 1

Select

T2AEDGE1 DET ENA

Output

Enable

Capt/Comp

Register

MSB

LSB

MSB

LSB

T2AEDGE1

OUT ENA

T2AIC1/CR

T2AEDGE1 POLARITY

T

oggle

16-Bit

Compare

MSB

LSB

Register

T2ACC.15-0

T2AC1 INT FLAG

T2ACTL2.0

T2ACTL2.5

T2AC1 INT ENA

T2AC2 INT FLAG

T2ACTL2.6

T2AC2 INT ENA

T2A OVRFL INT FLAG

T2ACTL1.4

T2ACTL1.3

T2A OVRFL INT ENA

T2AEDGE1 INT FLAG

T2ACTL2.2

T2ACTL2.7

T2AEDGE1 INT ENA

T2A PRIORITY

T2AC2 OUT ENA

T2AC1 OUT ENA

T2ACTL3.6

T2AIC2/PWM

T2APC2.7-4

T2APRI.6

T2ACNTR.15-0

T2ACTL1.0

T2ACTL3.4

T2AEDGE1

RST ENA

T2APC2.3-0

T2ACTL3.0

Level 1 Int

Level 2 Int

0

1

 

 

Figure 12. Dual-Compare Mode

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

35

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

The T2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,

bit 0, in the T2ACTL2 register.

0

Capt/Comp

T2APC2.3–0

Compare =

Clock

Source

16-Bit

Counter

MSB

LSB

T2ACNTR.15–0

Reset

T2AC1

RST ENA

T2ACTL1.0

T2ACTL3.4

T2ACTL2.6

T2ACTL2.1

T2ACTL2.7

T2ACTL2.2

T2ACTL2.5

T2ACTL2.0

16-Bit

MSB

LSB

Register 1

T2ACC.15–0

T2AC.15–0

16-Bit

Compare

MSB

LSB

Register

T2A PRIORITY

Level 1 Int

Level 2 Int

1

T2ACTL1.3

T2ACTL1.4

16-Bit

Capture

MSB

LSB

Register 2

T2AIC.15–0

Edge 2

Select

T2AIC2/PWM

T2APC2.7–4

T2ACTL3.1

Edge1

Select

T2AIC1/CR

T2ACTL3.3

T2ACTL3.2

T2ACTL3.0

16

T2AEDGE1 POLARITY

T2AEDGE1 DET ENA

T2AEDGE2 DET ENA

T2AEDGE2 POLARITY

T2AC1 INT FLAG

T2AC1 INT ENA

T2A OVRFL INT FLAG

T2A OVRFL INT ENA

T2AEDGE1 INT FLAG

T2AEDGE1 INT ENA

T2AEDGE2 INT ENA

T2AEDGE2 INT FLAG

T2APRI.6

T2A SW

RESET

Figure 13. Dual-Capture Mode

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

36

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

serial peripheral interface (SPI) module

The SPI is a high-speed, synchronous, serial I/O port that allows a serial bit stream of programmed length

(1 to 8 bits) to be shifted into, and out of, the device at a programmable bit-transfer rate.The SPI is used normally

for communications between the microcontroller and external peripherals or another microcontroller. Typical

applications include external I/O or peripheral expansion through devices such as shift registers, display drivers,

and analog-to-digital converters. The master/slave operation of the SPI supports multi-device communications.

The SPI module features include the following:

D

Three external pins:

SPISOMI: SPI slave output/master input pin or general purpose bidirectional I/O pin

SPISIMO: SPI slave input/master output pin or general purpose bidirectional I/O pin

SPICLK: SPI serial clock pin or general purpose bidirectional I/O pin

D

Two operational modes: master and slave

D

Baud rate: Eight different programmable rates

Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK

SPI BAUD RATE

+

SYSCLK

2

 

2

b

Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK.

For maximum slave SPI BAUD RATE < SYSCLK/8

where b = bit rate in SPICCR.5-3 (range 0–7)

D

Data word format: one to eight data bits

D

Simultaneous receive and transmit operation (transmit function can be disabled in software)

D

Transmitter and receiver operations are accomplished through either interrupt driven or polled algorithms.

D

Seven SPI module control registers located in control register frame beginning at address P030h

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

37

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

serial peripheral interface (SPI) module (continued)

The SPI module control registers are illustrated in Table 20.

Table 20. SPI Module Control Register Memory Map

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

PF

ÁÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 6

ÁÁÁÁ

ÁÁÁÁ

BIT 5

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 4

ÁÁÁÁ

ÁÁÁÁ

BIT 3

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 2

ÁÁÁÁ

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 0

ÁÁÁ

ÁÁÁ

REG

ÁÁÁ

ÁÁÁ

P030

ÁÁÁÁ

ÁÁÁÁ

SPI SW

RESET

ÁÁÁÁÁ

ÁÁÁÁÁ

CLOCK

POLARITY

ÁÁÁÁ

ÁÁÁÁ

SPI BIT

RATE2

ÁÁÁÁÁ

ÁÁÁÁÁ

SPI BIT

RATE1

ÁÁÁÁ

ÁÁÁÁ

SPI BIT

RATE0

ÁÁÁÁÁ

ÁÁÁÁÁ

SPI

CHAR2

ÁÁÁÁ

ÁÁÁÁ

SPI

CHAR1

ÁÁÁÁÁ

ÁÁÁÁÁ

SPI

CHAR0

ÁÁÁ

ÁÁÁ

SPICCR

ÁÁÁ

Á

Á

Á

ÁÁÁ

P031

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

RECEIVER

OVERRUN

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SPI INT

FLAG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

MASTER/

SLAVE

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

TALK

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SPI INT

ENA

ÁÁÁ

ÁÁ

Á

ÁÁÁ

SPICTL

ÁÁÁ

Á

Á

Á

ÁÁÁ

P032

to

P036

Reserved

ÁÁÁ

ÁÁ

Á

ÁÁÁ

ÁÁÁ

ÁÁÁ

P037

ÁÁÁÁ

ÁÁÁÁ

RCVD7

ÁÁÁÁÁ

ÁÁÁÁÁ

RCVD6

ÁÁÁÁ

ÁÁÁÁ

RCVD5

ÁÁÁÁÁ

ÁÁÁÁÁ

RCVD4

ÁÁÁÁ

ÁÁÁÁ

RCVD3

ÁÁÁÁÁ

ÁÁÁÁÁ

RCVD2

ÁÁÁÁ

ÁÁÁÁ

RCVD1

ÁÁÁÁÁ

ÁÁÁÁÁ

RCVD0

ÁÁÁ

ÁÁÁ

SPIBUF

ÁÁÁ

ÁÁÁ

P038

Reserved

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

P039

ÁÁÁÁ

ÁÁÁÁ

SDAT7

ÁÁÁÁÁ

ÁÁÁÁÁ

SDAT6

ÁÁÁÁ

ÁÁÁÁ

SDAT5

ÁÁÁÁÁ

ÁÁÁÁÁ

SDAT4

ÁÁÁÁ

ÁÁÁÁ

SDAT3

ÁÁÁÁÁ

ÁÁÁÁÁ

SDAT2

ÁÁÁÁ

ÁÁÁÁ

SDAT1

ÁÁÁÁÁ

ÁÁÁÁÁ

SDAT0

ÁÁÁ

ÁÁÁ

SPIDAT

ÁÁÁ

Á

Á

Á

ÁÁÁ

P03A

to

P03C

Reserved

ÁÁÁ

ÁÁ

Á

ÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

P03D

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SPICLK

DATA IN

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SPICLK

DATA OUT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SPICLK

FUNCTION

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SPICLK

DATA DIR

ÁÁÁ

ÁÁ

Á

ÁÁÁ

SPIPC1

ÁÁÁ

ÁÁÁ

P03E

ÁÁÁÁ

ÁÁÁÁ

SPISIMO

DATA IN

ÁÁÁÁÁ

ÁÁÁÁÁ

SPISIMO

DATA OUT

ÁÁÁÁ

ÁÁÁÁ

SPISIMO

FUNCTION

ÁÁÁÁÁ

ÁÁÁÁÁ

SPISIMO

DATA DIR

ÁÁÁÁ

ÁÁÁÁ

SPISOMI

DATA IN

ÁÁÁÁÁ

ÁÁÁÁÁ

SPISOMI

DATA OUT

ÁÁÁÁ

ÁÁÁÁ

SPISOMI

FUNCTION

ÁÁÁÁÁ

ÁÁÁÁÁ

SPISOMI

DATA DIR

ÁÁÁ

ÁÁÁ

SPIPC2

ÁÁÁ

Á

Á

Á

ÁÁÁ

P03F

SPI

STEST

SPI

PRIORITY

SPI

ESPEN

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁ

ÁÁ

Á

ÁÁÁ

SPIPRI

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

38

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

serial peripheral interface (SPI) module (continued)

The SPI block diagram is illustrated in Figure 14.

SPIBUF Buffer

Register

SPIDAT

Data Register

SPIBUF.7-0

State Control

SPI CHAR

SPI BIT RATE

CLOCK POLARITY

SPI INT FLAG

SPICTL.6

SPIINT ENA

SPICTL.0

RECEIVER

OVERRUN

8

SPIDAT.7-0

SPICTL.1

TALK

2

0

1

3

4

5

SPICCR.2-0

SPICCR.5-3

System

Clock

SPICCR.6

SPICLK

MASTER/SLAVE†

SPICTL.7

Level 2 INT

SPIPRI.6

1

SPIPC2.7-4

SPISIMO

SPICTL.2

SPIPC1.3-0

SPISOMI

SPIPC2.3-0

Level 1 INT

0

† The diagram is shown in slave mode.

Figure 14. SPI Block Diagram

serial communications interface 1 (SCI1) module

The TMS370x5x devices include a serial communications interface (SCI1) module. The SCI1 module supports

digital communications between the TMS370 devices and other asynchronous peripherals and uses the

standard non-return-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and

each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in

the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun,

and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a

16-bit baud-select register.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

39

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) module (continued)

Features of the SCI1 module include:

D

Three external pins:

SCITXD: SCI transmit output pin or general-purpose bidirectional I/O pin

SCIRXD: SCI receive input pin or general-purpose bidirectional I/O pin

SCICLK: SCI bidirectional serial clock pin, or general-purpose bidirectional I/O pin

D

Two communications modes: asynchronous and isosynchronous

D

Baud rate: 64K different programmable rates

Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK

ASYNCHRONOUS BAUD

+

SYSCLK

(BAUD REG

)

1)

 

32

Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK

ISOSYNCHRONOUS BAUD

+

SYSCLK

(BAUD REG

)

1)

 

2

D

Data-word format

One start bit

Data-word length programmable from 1 to 8 bits

Optional even/odd/no parity bit

One or two stop bits

D

Four error-detection flags: parity, overrun, framing, and break detection

D

Two wake-up multiprocessor modes: Idle-line and address bit

D

Half or full-duplex operation

D

Double-buffered receive and transmit functions

D

Interrupt driven or polled algorithms with status flags accomplish transmitter (TX) and receiver (RX)

operations.

Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX

EMPTY flag (transmitter shift register is empty)

Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break

condition occurred), and RX ERROR monitoring four interrupt conditions

Separate enable bits for transmitter and receiver interrupts

NRZ (non return-to-zero) format

D

Eleven SCI1 module control registers are located in control register frame beginning at address P050h.

† Isosynchronous = Isochronous

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

40

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) module (continued)

The SCI1 module control registers are illustrated in Table 21.

Table 21. SCI1 Module Control Register Memory Map

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

PF

ÁÁÁÁÁ

BIT 7

ÁÁÁÁ

BIT 6

ÁÁÁÁÁ

BIT 5

ÁÁÁÁ

BIT 4

ÁÁÁÁ

BIT 3

ÁÁÁÁÁ

BIT 2

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

REG

ÁÁÁ

Á

Á

Á

ÁÁÁ

P050

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

STOP BITS

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

EVEN/ODD

PARITY

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

PARITY

ENABLE

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ASYNC/

ISOSYNC

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ADDRESS/

IDLE WUP

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCI CHAR2

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCI CHAR1

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCI CHAR0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCICCR

ÁÁÁ

Á

Á

Á

ÁÁÁ

P051

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCI SW

RESET

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

CLOCK

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

TXWAKE

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SLEEP

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

TXENA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

RXENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCICTL

ÁÁÁ

ÁÁÁ

P052

ÁÁÁÁÁ

ÁÁÁÁÁ

BAUDF

(MSB)

ÁÁÁÁ

ÁÁÁÁ

BAUDE

ÁÁÁÁÁ

ÁÁÁÁÁ

BAUDD

ÁÁÁÁ

ÁÁÁÁ

BAUDC

ÁÁÁÁ

ÁÁÁÁ

BAUDB

ÁÁÁÁÁ

ÁÁÁÁÁ

BAUDA

ÁÁÁÁ

ÁÁÁÁ

BAUD9

ÁÁÁÁÁ

ÁÁÁÁÁ

BAUD8

ÁÁÁÁ

ÁÁÁÁ

BAUD MSB

ÁÁÁ

Á

Á

Á

ÁÁÁ

P053

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

BAUD7

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

BAUD6

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

BAUD5

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

BAUD4

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

BAUD3

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

BAUD2

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

BAUD1

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

BAUD0

(LSB)

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

BAUD LSB

ÁÁÁ

ÁÁÁ

P054

ÁÁÁÁÁ

ÁÁÁÁÁ

TXRDY

ÁÁÁÁ

ÁÁÁÁ

TX EMPTY

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

SCI TX

INT ENA

ÁÁÁÁ

ÁÁÁÁ

TXCTL

ÁÁÁ

Á

Á

Á

ÁÁÁ

P055

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

RX

ERROR

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

RXRDY

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

BRKDT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

FE

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

OE

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

PE

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

RXWAKE

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCI RX

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

RXCTL

ÁÁÁ

ÁÁÁ

P056

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁ

P057

ÁÁÁÁÁ

ÁÁÁÁÁ

RXDT7

ÁÁÁÁ

ÁÁÁÁ

RXDT6

ÁÁÁÁÁ

ÁÁÁÁÁ

RXDT5

ÁÁÁÁ

ÁÁÁÁ

RXDT4

ÁÁÁÁ

ÁÁÁÁ

RXDT3

ÁÁÁÁÁ

ÁÁÁÁÁ

RXDT2

ÁÁÁÁ

ÁÁÁÁ

RXDT1

ÁÁÁÁÁ

ÁÁÁÁÁ

RXDT0

ÁÁÁÁ

ÁÁÁÁ

RXBUF

ÁÁÁ

ÁÁÁ

P058

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

P059

ÁÁÁÁÁ

TXDT7

ÁÁÁÁ

TXDT6

ÁÁÁÁÁ

TXDT5

ÁÁÁÁ

TXDT4

ÁÁÁÁ

TXDT3

ÁÁÁÁÁ

TXDT2

ÁÁÁÁ

TXDT1

ÁÁÁÁÁ

TXDT0

ÁÁÁÁ

TXBUF

ÁÁÁ

Á

Á

Á

ÁÁÁ

P05A

P05B

P05C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

Á

Á

ÁÁÁ

P05D

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCICLK

DATA IN

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCICLK

DATA OUT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCICLK

FUNCTION

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCICLK

DATA DIR

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCIPC1

ÁÁÁ

Á

Á

Á

ÁÁÁ

P05E

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCITXD

DATA IN

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCITXD

DATA OUT

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCITXD

FUNCTION

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCITXD

DATA DIR

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCIRXD

DATA IN

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCIRXD

DATA OUT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCIRXD

FUNCTION

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

SCIRXD

DATA DIR

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SCIPC2

ÁÁÁ

ÁÁÁ

P05F

SCI STEST

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

SCIPRI

ÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

The SCI1 module block diagram is illustrated in Figure 15.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

41

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) module (continued)

RXCTL.4 – 2

FE OE PE

RX ERROR

SCICTL.3

TXWAKE

SCICCR.6 SCICCR.5

EVEN / ODD ENABLE

PARITY

Frame Format and Mode

WUT

TXBUF.7 – 0

Transmit Data 

Buffer Reg.

TXSHF Reg.

TXCTL.7

TXCTL.6

TXRDY

TX EMPTY

SCI TX Interrupt

TXCTL.0

TXENA

8

SCICTL.4

BAUD MSB. 7 – 0

Baud Rate

MSbyte Reg.

BAUD LSB. 7 – 0

Baud Rate

LSbyte Reg.

CLOCK

SCICTL.1

SCITXD

SCI TX INT ENA

RXCTL.7

ERR

RXSHF Reg.

RXCTL.1

8

Receive Data

Buffer Reg.

RXBUF.7 – 0

RXENA

RXCTL.6

RXCTL.5

RXRDY

BRKDT

SCI RX Interrupt

RXCTL.0

SCI RX INT ENA

ÏÏÏ

ÏÏÏ

SCIPRI.6

ÏÏÏÏ

ÏÏÏÏ

SCIPRI.5

Level 1 INT

Level 2 INT

Level 1 INT

Level 2 INT

SCITX PRIORITY

SCIRX PRIORITY

SCITXD

SCIPC2.7 – 4

SCICLK

SCIPC1.3 – 0

SCIRXD

SCIRXD

SCIPC2.3 – 0

SCICTL.0

RXWAKE

1

SYSCLK

0

1

0

1

Figure 15. SCI1 Block Diagram

analog-to-digital converter 1 (ADC1) module

The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal

sample-and-hold circuitry. The module has eight multiplexed analog input channels that allow the processor to

convert the voltage levels from up to eight different sources. The ADC1 module features include the following:

D

Minimum conversion time: 32.8 

µ

s at 5-MHz SYSCLK

D

Ten external pins:

Eight analog input channels (AN0 – AN7), any of which can be software configured as digital inputs

(E0 – E7) if not needed as analog channels

AN1 – AN7 can also be configured as positive-input voltage reference.

V

CC3

: A/D module high-voltage reference input

V

SS3

: A/D module low-voltage reference input

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

42

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

analog-to-digital converter 1 (ADC1) module (continued)

D

The ADDATA register, which contains the digital result of the last ADC1 conversion

D

ADC1 operations can be accomplished through either interrupt driven or polled algorithms.

D

Six ADC1 module control registers are located in the control-register frame beginning at address 1070h.

The ADC1 module control registers are illustrated in Table 22.

Table 22. ADC1 Module Control Register Memory Map

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

PF

ÁÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁ

ÁÁÁÁ

BIT 6

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 5

ÁÁÁÁ

ÁÁÁÁ

BIT 4

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 3

ÁÁÁÁ

ÁÁÁÁ

BIT 2

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 1

ÁÁÁÁ

ÁÁÁÁ

BIT 0

ÁÁÁÁ

ÁÁÁÁ

REG

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

P070

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

CONVERT

START

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

SAMPLE

START

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

REF VOLT

SELECT2

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

REF VOLT

SELECT1

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

REF VOLT

SELECT0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

AD INPUT

SELECT2

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

AD INPUT

SELECT1

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

AD INPUT

SELECT0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ADCTL

ÁÁÁÁ

ÁÁÁÁ

P071

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

AD READY

ÁÁÁÁÁ

ÁÁÁÁÁ

AD INT

FLAG

ÁÁÁÁ

ÁÁÁÁ

AD INT

ENA

ÁÁÁÁ

ÁÁÁÁ

ADSTAT

ÁÁÁÁ

ÁÁÁÁ

P072

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A-to-D Conversion Data Register

ÁÁÁÁ

ÁÁÁÁ

ADDATA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

P073

to

P07C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

P07D

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port E Data Input Register

ÁÁÁÁ

ÁÁÁÁ

ADIN

ÁÁÁÁ

ÁÁÁÁ

P07E

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port E Input Enable Register

ÁÁÁÁ

ÁÁÁÁ

ADENA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

P07F

AD STEST

AD

PRIORITY

AD ESPEN

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ADPRI

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

43

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

analog-to-digital converter 1 (ADC1) module (continued)

The ADC1 module block diagram is illustrated in Figure 16.

ADCTL.5 – 3

5

4

3

ADENA.0

REF VOLTS SELECT

ADCTL.2 – 0

2

1

0

AD INPUT SELECT

ADIN.0

Port E Input

ENA 0

Port E Data

AN 0

AN0

ADENA.1

ADIN.1

Port E Input

ENA 1

Port E Data

AN 1

AN1

ADENA.2

ADIN.2

Port E Input

ENA 2

Port E Data

AN 2

AN2

ADENA.3

ADIN.3

Port E Input

ENA 3

Port E Data

AN 3

AN3

ADENA.4

ADIN.4

Port E Input

ENA 4

Port E Data

AN 4

AN4

ADENA.5

ADIN.5

Port E Input

ENA 5

Port E Data

AN 5

AN5

ADENA.6

ADIN.6

Port E Input

ENA 6

Port E Data

AN 6

AN6

ADENA.7

ADIN.7

Port E Input

ENA 7

Port E Data

AN 7

AN7

VCC3

VSS3

ADCTL.6

SAMPLE

START

ADCTL.7

CONVERT

START

ADDATA.7 – 0

A-to-D

Conversion

Data Register

ADSTAT.2

AD READY

AD PRIORITY

ADPRI.6

0

1

Level 1 INT

Level 2 INT

AD INT FLAG

ADSTAT.1

AD INT ENA

ADSTAT.0

ADC1

Figure 16. ADC1 Block Diagram

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

 

 

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

44

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

instruction set overview

Table 23 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the

‘370Cx5x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode

while the numbers at the left side of the table represent the least significant nibble. The instruction of these two

opcode nibbles contains the mnemonic, operands, and byte / cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes

in eight SYSCLK cycles.

background image

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUAR

Y

 1997

POST

 OFFICE BOX 1443    HOUST

ON, 

TEXAS 

 77251–1443

45

Table 23. TMS370 Family Opcode/Instruction Map

MSN

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

JMP

#ra

2/7

INCW

#ra,Rd

3/11

MOV

Ps,A

2/8

CLRC  /

TST A

1/9

MOV

A,B

1/9

MOV

A,Rd

2/7

TRAP

15

1/14

LDST

n

2/6

1

JN

ra

2/5

MOV

A,Pd

2/8

MOV

B,Pd

2/8

MOV

Rs,Pd

3/10

MOV

Ps,B

2/7

MOV

B,Rd

2/7

TRAP

14

1/14

MOV

#ra[SP],A

2/7

2

JZ

ra

2/5

MOV

Rs,A

2/7

MOV

#n,A

2/6

MOV

Rs,B

2/7

MOV

Rs,Rd

3/9

MOV

#n,B

2/6

MOV

B,A

1/8

MOV

#n,Rd

3/8

MOV

Ps,Rd

3/10

DEC

A

1/8

DEC

B

1/8

DEC

Rd

2/6

TRAP

13

1/14

MOV

A,*ra[SP]

2/7

3

JC

ra

2/5

AND

Rs,A

2/7

AND

#n,A

2/6

AND

Rs,B

2/7

AND

Rs,Rd

3/9

AND

#n,B

2/6

AND

B,A

1/8

AND

#n,Rd

3/8

AND

A,Pd

2/9

AND

B,Pd

2/9

AND

#n,Pd

3/10

INC

A

1/8

INC

B

1/8

INC

Rd

2/6

TRAP

12

1/14

CMP

*n[SP],A

2/8

4

JP

ra

2/5

OR

Rs,A

2/7

OR

#n,A

2/6

OR

Rs,B

2/7

OR

Rs,Rd

3/9

OR

#n,B

2/6

OR

B,A

1/8

OR

#n,Rd

3/8

OR

A,Pd

2/9

OR

B,Pd

2/9

OR

#n,Pd

3/10

INV

A

1/8

INV

B

1/8

INV

Rd

2/6

TRAP

11

1/14

extend

inst,2

opcodes

L

S

N

5

JPZ

ra

2/5

XOR

Rs,A

2/7

XOR

#n,A

2/6

XOR

Rs,B

2/7

XOR

Rs,Rd

3/9

XOR

#n,B

2/6

XOR

B,A

1/8

XOR

#n,Rd

3/8

XOR

A,Pd

2/9

XOR

B,Pd

2/9

XOR

#n,Pd

3/10

CLR

A

1/8

CLR

B

1/8

CLR

Rn

2/6

TRAP

10

1/14

N

6

JNZ

ra

2/5

BTJO

Rs,A,ra

3/9

BTJO

#n,A,ra

3/8

BTJO

Rs,B,ra

3/9

BTJO

Rs,Rd,ra

4/11

BTJO

#n,B,ra

3/8

BTJO

B,A,ra

2/10

BTJO

#n,Rd,ra

4/10

BTJO

A,Pd,ra

3/11

BTJO

B,Pd,ra

3/10

BTJO

#n,Pd,ra

4/11

XCHB

A

1/10

XCHB A /

TST B

1/10

XCHB

Rn

2/8

TRAP

9

1/14

IDLE

1/6

7

JNC

ra

2/5

BTJZ

Rs.,A,ra

3/9

BTJZ

#n,A,ra

3/8

BTJZ

Rs,B,ra

3/9

BTJZ

Rs,Rd,ra

4/11

BTJZ

#n,B,ra

3/8

BTJZ

B,A,ra

2/10

BTJZ

#n,Rd,ra

4/10

BTJZ

A,Pd,ra

3/10

BTJZ

B,Pd,ra

3/10

BTJZ

#n,Pd,ra

4/11

SWAP

A

1/11

SWAP

B

1/11

SWAP

Rn

2/9

TRAP

8

1/14

MOV

#n,Pd

3/10

8

JV

ra

2/5

ADD

Rs,A

2/7

ADD

#n,A

2/6

ADD

Rs,B

2/7

ADD

Rs,Rd

3/9

ADD

#n,B

2/6

ADD

B,A

1/8

ADD

#n,Rd

3/8

MOVW

#16,Rd

4/13

MOVW

Rs,Rd

3/12

MOVW

#16[B],Rpd

4/15

PUSH

A

1/9

PUSH

B

1/9

PUSH

Rd

2/7

TRAP

7

1/14

SETC

1/7

9

JL

ra

2/5

ADC

Rs,A

2/7

ADC

#n,A

2/6

ADC

Rs,B

2/7

ADC

Rs,Rd

3/9

ADC

#n,B

2/6

ADC

B,A