background image

 

SN74ALVCH162244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES065D – JANUARY 1996 – REVISED JUNE 1999

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

Output Ports Have Equivalent 26-

 Series

Resistors, So No External Resistors Are

Required

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

NOTE: For tape and reel order entry:

The DGGR package is abbreviated to GR.

description

This 16-bit buffer/driver is designed for 1.65-V to

3.6-V V

CC

 operation.

The SN74ALVCH162244 is designed specifically

to improve the performance and density of 3-state

memory address drivers, clock drivers, and

bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two

8-bit buffers, or one 16-bit buffer. It provides true

outputs and symmetrical active-low output-

enable (OE) inputs.

The outputs, which are designed to sink up to 12 mA, include equivalent 26-

 resistors to reduce overshoot

and undershoot.

To ensure the high-impedance state during power up or power down, OE should be tied to V

CC

 through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162244 is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1OE

1Y1

1Y2

GND

1Y3

1Y4

V

CC

2Y1

2Y2

GND

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

V

CC

4Y1

4Y2

GND

4Y3

4Y4

4OE

2OE

1A1

1A2

GND

1A3

1A4

V

CC

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

V

CC

4A1

4A2

GND

4A3

4A4

3OE

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SN74ALVCH162244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES065D – JANUARY 1996 – REVISED JUNE 1999

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

(each 4-bit buffer)

INPUTS

OUTPUT

OE

A

Y

L

H

H

L

L

L

H

X

Z

logic symbol

47

1A1

46

1A2

44

1A3

43

1A4

1Y1

2

1Y2

3

1Y3

5

1Y4

6

41

2A1

40

2A2

38

2A3

37

2A4

2Y1

8

2Y2

9

2Y3

11

2Y4

12

36

3A1

35

3A2

33

3A3

32

3A4

3Y1

13

3Y2

14

3Y3

16

3Y4

17

30

4A1

29

4A2

27

4A3

26

4A4

4Y1

19

4Y2

20

4Y3

22

4Y4

23

EN1

1

EN4

24

1OE

2OE

3OE

4OE

EN2

48

EN3

25

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1

1

1

1

1

2

3

4

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SN74ALVCH162244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES065D – JANUARY 1996 – REVISED JUNE 1999

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

1OE

1A1

1A2

1A3

1A4

1Y1

1Y2

1Y3

1Y4

1

47

46

44

43

2

3

5

6

2OE

2A1

2A2

2A3

2A4

2Y1

2Y2

2Y3

2Y4

48

41

40

38

37

8

9

11

12

3OE

3A1

3A2

3A3

3A4

3Y1

3Y2

3Y3

3Y4

25

36

35

33

32

13

14

16

17

4OE

4A1

4A2

4A3

4A4

4Y1

4Y2

4Y3

4Y4

24

30

29

27

26

19

20

22

23

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 (see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through each V

CC

 or GND 

±

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 3): DGG package 

89

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

94

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

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SN74ALVCH162244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES065D – JANUARY 1996 – REVISED JUNE 1999

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

1.65

3.6

V

VCC = 1.65 V to 1.95 V

0.65 

×

VCC

VIH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V

VCC = 2.7 V to 3.6 V

2

VCC = 1.65 V to 1.95 V

0.35 

×

VCC

VIL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V

VCC = 2.7 V to 3.6 V

0.8

VI

Input voltage

0

VCC

V

VO

Output voltage

0

VCC

V

VCC = 1.65 V

–2

IOH

High level output current

VCC = 2.3 V

–6

mA

IOH

High-level output current

VCC = 2.7 V

–8

mA

VCC = 3 V

–12

VCC = 1.65 V

2

IOL

Low level output current

VCC = 2.3 V

6

mA

IOL

Low-level output current

VCC = 2.7 V

8

mA

VCC = 3 V

12

t/

v

Input transition rise or fall rate

10

ns/V

TA

Operating free-air temperature

–40

85

°

C

NOTE  4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74ALVCH162244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES065D – JANUARY 1996 – REVISED JUNE 1999

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

IOH = –100 

µ

A

1.65 V to 3.6 V

VCC–0.2

IOH = –2 mA

1.65 V

1.2

IOH = –4 mA

2.3 V

1.9

VOH

IOH = 6 mA

2.3 V

1.7

V

IOH = –6 mA

3 V

2.4

IOH = –8 mA

2.7 V

2

IOH = –12 mA

3 V

2

IOL = 100 

µ

A

1.65 V to 3.6 V

0.2

IOL = 2 mA

1.65 V

0.45

IOL = 4 mA

2.3 V

0.4

VOL

IOL = 6 mA

2.3 V

0.55

V

IOL = 6 mA

3 V

0.55

IOL = 8 mA

2.7 V

0.6

IOL = 12 mA

3 V

0.8

II

VI = VCC or GND

3.6 V

±

5

µ

A

VI = 0.58 V

1.65 V

25

VI = 1.07 V

1.65 V

–25

VI = 0.7 V

2.3 V

45

II(hold)

VI = 1.7 V

2.3 V

–45

µ

A

(

)

VI = 0.8 V

3 V

75

VI = 2 V

3 V

–75

VI = 0 to 3.6 V‡

3.6 V

±

500

IOZ

VO = VCC or GND

3.6 V

±

10

µ

A

ICC

VI = VCC or GND,

IO = 0

3.6 V

40

µ

A

ICC

One input at VCC – 0.6 V,

Other inputs at VCC or GND

3 V to 3.6 V

750

µ

A

Ci

Control inputs

VI = VCC or GND

3 3 V

3

pF

Ci

Data inputs

VI = VCC or GND

3.3 V

6

pF

Co

Outputs

VO = VCC or GND

3.3 V

7

pF

† All typical values are at VCC = 3.3 V, TA = 25

°

C.

‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 1.8 V

VCC = 2.5 V

±

 0.2 V

VCC = 2.7 V

VCC = 3.3 V

±

 0.3 V

UNIT

(INPUT)

(OUTPUT)

TYP

MIN

MAX

MIN

MAX

MIN

MAX

tpd

A

Y

§

1

4.9

4.7

1

4.2

ns

ten

OE

Y

§

1

6.8

6.7

1

5.6

ns

tdis

OE

Y

§

1

6.3

5.7

1

5.5

ns

§ This information was not available at the time of publication.

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SN74ALVCH162244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES065D – JANUARY 1996 – REVISED JUNE 1999

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

operating characteristics, T

= 25

°

C

PARAMETER

TEST CONDITIONS

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

UNIT

PARAMETER

TEST CONDITIONS

TYP

TYP

TYP

UNIT

C d

Power dissipation

Outputs enabled

CL = 50 pF

f = 10 MHz

16

19

pF

Cpd

capacitance

Outputs disabled

CL = 50 pF,

f = 10 MHz

4

5

pF

† This information was not available at the time of publication.

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 1.8 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

1 k

1 k

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2 ns, tf 

 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 1. Load Circuit and Voltage Waveforms

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SN74ALVCH162244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES065D – JANUARY 1996 – REVISED JUNE 1999

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.5 V 

±

 0.2 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500

 Ω

500

 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

  2 ns, tf 

 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 2. Load Circuit and Voltage Waveforms

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SN74ALVCH162244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES065D – JANUARY 1996 – REVISED JUNE 1999

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC 

= 2.7 V AND 3.3 V 

±

 0.3 V

VOH

VOL

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

6 V

Open

GND

500

 Ω

500

 Ω

tPLH

tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

1.5 V

1.5 V

2.7 V

0 V

1.5 V

1.5 V

VOH

VOL

0 V

1.5 V

VOL +0.3 V

1.5 V

VOH –0.3 V

0 V

1.5 V

2.7 V

0 V

1.5 V

1.5 V

0 V

2.7 V

0 V

1.5 V

1.5 V

tw

Input

2.7 V

2.7 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf 

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

Figure 3. Load Circuit and Voltage Waveforms

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Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

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In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

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Copyright 

©

 1999, Texas Instruments Incorporated