background image

 

SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

description

This 18-bit universal bus transceiver is designed

for 1.65-V to 3.6-V V

CC

 operation.

Data flow in each direction is controlled by

output-enable (OEAB and OEBA), latch-enable

(LEAB and LEBA), and clock (CLKAB and

CLKBA) inputs. For A-to-B data flow, the device

operates in the transparent mode when LEAB is

high. When LEAB is low, the A data is latched if

CLKAB is held at a high or low logic level. If LEAB

is low, the A data is stored in the latch/flip-flop on

the low-to-high transition of CLKAB. When OEAB

is high, the outputs are active. When OEAB is low,

the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are

complementary (OEAB is active high and OEBA is active low).

To ensure the high-impedance state during power up or power down, OEBA should be tied to V

CC

 through a

pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor

is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16501 is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 2000, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC, UBT, and Widebus are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

DGG OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

OEAB

LEAB

A1

GND

A2

A3

V

CC

A4

A5

A6

GND

A7

A8

A9

A10

A11

A12

GND

A13

A14

A15

V

CC

A16

A17

GND

A18

OEBA

LEBA

GND

CLKAB

B1

GND

B2

B3

V

CC

B4

B5

B6

GND

B7

B8

B9

B10

B11

B12

GND

B13

B14

B15

V

CC

B16

B17

GND

B18

CLKBA

GND

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE†

INPUTS

OUTPUT

OEAB

LEAB

CLKAB

A

B

L

X

X

X

Z

H

H

X

L

L

H

H

X

H

H

H

L

L

L

H

L

H

H

H

L

H

X

B0‡

H

L

L

X

B0§

† A-to-B data flow is shown; B-to-A flow is similar but

uses OEBA, LEBA, and CLKBA.

‡ Output level before the indicated steady-state input

conditions were established, provided that CLKAB

was high before LEAB went low

§ Output level before the indicated steady-state input

conditions were established

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

A2

5

EN1

1

OEAB

2C3

3D

3

A1

B1

54

A14

20

A15

21

A16

23

A17

24

A8

13

A9

14

A10

15

A11

16

A12

17

A3

6

A4

8

A5

9

A6

10

A7

12

B13

38

B14

37

B15

36

B16

34

B17

33

B18

31

6D

4

A18

26

B8

44

B9

43

B10

42

B11

41

B12

40

B3

51

B4

49

B5

48

B6

47

B7

45

B2

52

C6

28

LEBA

G5

30

CLKBA

EN4

27

C3

2

LEAB

G2

55

CLKAB

5C6

OEBA

1

1

1

A13

19

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

1D

C1

CLK

1D

C1

CLK

B1

OEAB

CLKAB

LEAB

LEBA

CLKBA

OEBA

A1

1

55

2

28

30

27

3

54

To 17 Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

: Except I/O ports (see Note 1) 

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

I/O ports (see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 (see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through each V

CC

 or GND 

±

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 3): DGG package 

64

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

56

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

1.65

3.6

V

VCC = 1.65 V to 1.95 V

0.65 

×

VCC

VIH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V

VCC = 2.7 V to 3.6 V

2

VCC = 1.65 V to 1.95 V

0.35 

×

VCC

VIL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V

VCC = 2.7 V to 3.6 V

0.8

VI

Input voltage

0

VCC

V

VO

Output voltage

0

VCC

V

VCC = 1.65 V

–4

IOH

High level output current

VCC = 2.3 V

–12

mA

IOH

High-level output current

VCC = 2.7 V

–12

mA

VCC = 3 V

–24

VCC = 1.65 V

4

IOL

Low level output current

VCC = 2.3 V

12

mA

IOL

Low-level output current

VCC = 2.7 V

12

mA

VCC = 3 V

24

t/

v

Input transition rise or fall rate

10

ns/V

TA

Operating free-air temperature

–40

85

°

C

NOTE  4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

IOH = –100 

µ

A

1.65 V to 3.6 V

VCC–0.2

IOH = –4 mA

1.65 V

1.2

IOH = –6 mA

2.3 V

2

VOH

2.3 V

1.7

V

IOH = –12 mA

2.7 V

2.2

3 V

2.4

IOH = –24 mA

3 V

2

IOL = 100 

µ

A

1.65 V to 3.6 V

0.2

IOL = 4 mA

1.65 V

0.45

VOL

IOL = 6 mA

2.3 V

0.4

V

VOL

IOL = 12 mA

2.3 V

0.7

V

IOL = 12 mA

2.7 V

0.4

IOL = 24 mA

3 V

0.55

II

VI = VCC or GND

3.6 V

±

5

µ

A

VI = 0.58 V

1.65 V

25

VI = 1.07 V

1.65 V

–25

VI = 0.7 V

2.3 V

45

II(hold)

VI = 1.7 V

2.3 V

–45

µ

A

(

)

VI = 0.8 V

3 V

75

VI = 2 V

3 V

–75

VI = 0 to 3.6 V‡

3.6 V

±

500

IOZ§

VO = VCC or GND

3.6 V

±

10

µ

A

ICC

VI = VCC or GND,

IO = 0

3.6 V

40

µ

A

ICC

One input at VCC – 0.6 V,

Other inputs at VCC or GND

3 V to 3.6 V

750

µ

A

Ci

Control inputs

VI = VCC or GND

3.3 V

4

pF

Cio

A or B ports

VO = VCC or GND

3.3 V

8

pF

† All typical values are at VCC = 3.3 V, TA = 25

°

C.

‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

§ For I/O ports, the parameter IOZ includes the input leakage current.

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figures 1 through 3)

VCC = 1.8 V

VCC = 2.5 V

±

 0.2 V

VCC = 2.7 V

VCC = 3.3 V

±

 0.3 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

150

150

150

MHz

t

Pulse duration

LE high

3.3

3.3

3.3

ns

tw

Pulse duration

CLK high or low

3.3

3.3

3.3

ns

Data before CLK

2.2

2.1

1.7

tsu

Setup time

Data

CLK high

1.9

1.6

1.5

ns

before LE

CLK low

1.3

1.1

1

th

Hold time

Data after CLK

0.6

0.6

0.7

ns

th

Hold time

Data after LE

CLK high or low

1.4

1.7

1.4

ns

¶ This information was not available at the time of publication.

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 1.8 V

VCC = 2.5 V

±

 0.2 V

VCC = 2.7 V

VCC = 3.3 V

±

 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MIN

MAX

MIN

MAX

MIN

MAX

fmax

150

150

150

MHz

A or B

B or A

1

4.8

4.5

1

3.9

tpd

LE

A or B

1.1

5.7

5.3

1.3

4.6

ns

CLK

A or B

1.2

6.1

5.6

1.4

4.9

ten

OEAB

B

1

5.8

5.3

1

4.6

ns

tdis

OEAB

B

1.5

6.2

5.7

1.4

5

ns

ten

OEBA

A

1.3

6.3

6

1.1

5

ns

tdis

OEBA

A

1.3

5.3

4.6

1.3

4.2

ns

† This information was not available at the time of publication.

operating characteristics, T

= 25

°

C

PARAMETER

TEST CONDITIONS

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

UNIT

PARAMETER

TEST CONDITIONS

TYP

TYP

TYP

UNIT

C d

Power dissipation

Outputs enabled

CL = 50 pF

f = 10 MHz

44

54

pF

Cpd

capacitance

Outputs disabled

CL = 50 pF,

f = 10 MHz

6

6

pF

† This information was not available at the time of publication.

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 1.8 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

1 k

1 k

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

2 ns, tf 

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 1. Load Circuit and Voltage Waveforms

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.5 V 

±

 0.2 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500

 Ω

500

 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2 ns, tf 

 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 2. Load Circuit and Voltage Waveforms

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SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES024D – JULY 1995 – REVISED MAY 2000

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.7 V AND 3.3 V 

±

 0.3 V

VOH

VOL

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

6 V

Open

GND

500

 Ω

500

 Ω

tPLH

tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

2.7 V

0 V

VOH

VOL

0 V

VOL + 0.3 V

VOH – 0.3 V

0 V

2.7 V

0 V

0 V

2.7 V

0 V

tw

Input

2.7 V

2.7 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

2.5 ns, tf 

2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

Figure 3. Load Circuit and Voltage Waveforms

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