background image

 

SN54ABT162601, SN74ABT162601

18-BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS247G – AUGUST 1992 – REVISED JULY 1998

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

B-Port Outputs Have Equivalent 25-

Series Resistors, So No External Resistors

Are Required

D

State-of-the-Art 

EPIC-

ΙΙ

B

 BiCMOS Design

Significantly Reduces Power Dissipation

D

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, Clocked, or Clock-Enabled Mode

D

Latch-Up Performance Exceeds 500 mA Per

JESD 17

D

Typical V

OLP

 (Output Ground Bounce)

< 0.8 V at V

CC

 = 5 V, T

A

 = 25

°

C

D

High-Impedance State During Power Up

and Power Down

D

Flow-Through Architecture Optimizes PCB

Layout

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

These 18-bit universal bus transceivers combine

D-type latches and D-type flip-flops to allow data

flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by

output-enable (OEAB and OEBA), latch-enable

(LEAB and LEBA), and clock (CLKAB and

CLKBA) inputs. The clock can be controlled by the

clock-enable (CLKENAB and CLKENBA) inputs.

For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the

A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the

latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB is active-low. When OEAB is low,

the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A

is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.

The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-

 series resistors

to reduce overshoot and undershoot.

When V

CC

 is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to V

CC

 through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Copyright 

©

 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Widebus, EPIC-

ΙΙ

B, and UBT are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54ABT162601 . . . WD PACKAGE

SN74ABT162601 . . . DGG OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

OEAB

LEAB

A1

GND

A2

A3

V

CC

A4

A5

A6

GND

A7

A8

A9

A10

A11

A12

GND

A13

A14

A15

V

CC

A16

A17

GND

A18

OEBA

LEBA

CLKENAB

CLKAB

B1

GND

B2

B3

V

CC

B4

B5

B6

GND

B7

B8

B9

B10

B11

B12

GND

B13

B14

B15

V

CC

B16

B17

GND

B18

CLKBA

CLKENBA

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

background image

SN54ABT162601, SN74ABT162601

18-BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS247G – AUGUST 1992 – REVISED JULY 1998

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

description (continued)

The SN54ABT162601 is characterized for operation over the full military temperature range of –55

°

C to 125

°

C.

The SN74ABT162601 is characterized for operation from –40

°

C to 85

°

C.

FUNCTION TABLE†

INPUTS

OUTPUT

CLKENAB

OEAB

LEAB

CLKAB

A

B

X

H

X

X

X

Z

X

L

H

X

L

L

X

L

H

X

H

H

H

L

L

X

X

B0‡

H

L

L

X

X

B0‡

L

L

L

L

L

L

L

L

H

H

L

L

L

L

X

B0‡

L

L

L

H

X

B0§

† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,

LEBA, CLKBA, and CLKENBA.

‡ Output level before the indicated steady-state input conditions

were established

§ Output level before the indicated steady-state input conditions

were established, provided that CLKAB was low before LEAB

went low

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SN54ABT162601, SN74ABT162601

18-BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS247G – AUGUST 1992 – REVISED JULY 1998

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

CE

1D

LE

CLK

CE

1D

LE

CLK

B1

OEAB

CLKENAB

CLKAB

LEAB

LEBA

CLKBA

CLKENBA

OEBA

A1

1

56

55

2

28

30

29

27

3

54

To 17 Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (except I/O ports) (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high or power-off state, V

O

 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . 

Current into any output in the low state, I

O

: SN54ABT162601 (A port)

96 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ABT162601 (A port)

128 mA

. . . . . . . . . . . . . . . . . . . . . . . . . 

B port

30 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK 

(V

< 0) 

–18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK 

(V

< 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA

 (see Note 2): DGG package

81

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

74

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

background image

SN54ABT162601, SN74ABT162601

18-BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS247G – AUGUST 1992 – REVISED JULY 1998

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54ABT162601

SN74ABT162601

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High level output current

A port

–24

–32

mA

IOH

High-level output current

B port

–12

–12

mA

IOL

Low level output current

A port

48

64

mA

IOL

Low-level output current

B port

12

12

mA

t/

v

Input transition rise or fall rate

Outputs enabled

10

10

ns/V

t/

VCC

Power-up ramp rate

200

200

µ

s/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: All unused inputs of the devices must be held at VCC or GND to ensure proper device operation. Refer to the TI application note,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

background image

SN54ABT162601, SN74ABT162601

18-BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS247G – AUGUST 1992 – REVISED JULY 1998

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABT162601

SN74ABT162601

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

–1.2

–1.2

V

VCC = 4.5 V,

IOH = –3 mA

2.5

2.5

2.5

A port

VCC = 5 V,

IOH = –3 mA

3

3

3

A port

VCC = 4 5 V

IOH = –24 mA

2

2

VOH

VCC = 4.5 V

IOH = –32 mA

2*

2

V

VOH

VCC = 4.5 V,

IOH = –1 mA

3.35

3.3

3.35

V

B port

VCC = 5 V,

IOH = –1 mA

3.85

3.8

3.85

B port

VCC = 4 5 V

IOH = –3 mA

3.1

3

3.1

VCC = 4.5 V

IOH = –12 mA

2.6

2.6

A port

VCC = 4 5 V

IOL = 48 mA

0.55

0.55

VOL

A port

VCC = 4.5 V

IOL = 64 mA

0.55*

0.55

V

B port

VCC = 4.5 V,

IOL = 12 mA

0.8

0.8

0.8

Vhys

100

mV

II

Control

inputs

VCC = 0 to 5.5 V, VI = VCC or GND

±

1

±

1

±

1

µ

A

II

A or B ports

VCC = 2.1 V to 5.5 V,

VI = VCC or GND

±

20

±

20

±

20

µ

A

IOZPU

VCC = 0 to 2.1 V,

VO = 0.5 V to 2.7 V, OE = X

±

50

±

50**

±

50

µ

A

IOZPD

VCC = 2.1 V to 0,

VO = 0.5 V to 2.7 V, OE = X

±

50

±

50**

±

50

µ

A

IOZH‡

VCC = 2.1 V to 5.5 V,

VO = 2.7 V, OE 

 2 V

10

10

10

µ

A

IOZL‡

VCC = 2.1 V to 5.5 V,

VO = 0.5 V, OE 

 2 V

–10

–10

–10

µ

A

Ioff

VCC = 0,

VI or VO 

 4.5 V

±

100*

±

100

µ

A

ICEX

VCC = 5.5 V,

VO = 5.5 V

Outputs high

50

50

50

µ

A

IO§

A port

VCC = 5 5 V

VO = 2 5 V

–50

–100

–180

–50

–180

–50

–180

mA

IO§

B port

VCC = 5.5 V,

VO = 2.5 V

–25

–55

–100

–25

–100

–25

–100

mA

VCC = 5.5 V,

Outputs high

3

3

3

ICC

A or B ports

VCC = 5.5 V,

IO = 0,

Outputs low

36

36

36

mA

VI = VCC or GND

Outputs disabled

3

3

3

ICC¶

VCC = 5.5 V, One input at 3.4 V,

Other inputs at VCC or GND

50

50

50

µ

A

Ci

Control

inputs

VI = 2.5 V or 0.5 V

3

pF

Cio

A or B ports

VO = 2.5 V or 0.5 V

9

pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.

** On products compliant to MIL-PRF-38535, this parameter is not production tested.

† All typical values are at VCC = 5 V.

‡ The parameters IOZH and IOZL include the input leakage current.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

background image

SN54ABT162601, SN74ABT162601

18-BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS247G – AUGUST 1992 – REVISED JULY 1998

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)(see Figure 1)

SN54ABT162601

SN74ABT162601

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

0

150

0

150

MHz

t

Pulse duration

LEAB or LEBA high

2.5

2.5

ns

tw

Pulse duration

CLKAB or CLKBA high or low

3.3

3

ns

A before CLKAB

 or B before CLKBA

4.8

4.3

t

Setup time

A before LEAB

or B before LEBA

CLK high

2.5

2.5

ns

tsu

Setup time

A before LEAB

 or B before LEBA

CLK low

1.2

1

ns

CLKEN before CLK

2.7

2.7

A after CLKAB

 or B after CLKBA

0.5

0

th

Hold time

A after LEAB

 or B after LEBA

2

0.5

ns

CLKEN after CLK

0.5

0

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

SN54ABT162601

SN74ABT162601

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fmax

150

150

150

MHz

tPLH

A

B

1.5

2.8

4

1.5

5.1

1.5

4.8

ns

tPHL

A

B

2

3.7

5.2

2

6.1

2

5.7

ns

tPLH

B

A

1

2.5

3.6

1

4.5

1

4

ns

tPHL

B

A

2

3.3

4.5

2

5.1

2

4.9

ns

tPLH

LEBA

A

2

3.3

4.5

2

5.6

2

5

ns

tPHL

LEBA

A

2

3.6

4.7

2

5.4

2

5

ns

tPLH

LEAB

B

2

3.4

4.8

2

6.1

2

5.6

ns

tPHL

LEAB

B

2

3.8

5.2

2

6.4

2

5.9

ns

tPLH

CLKBA

A

1.5

3.1

4.7

1.5

5.4

1.5

5.3

ns

tPHL

CLKBA

A

1.5

3.1

4.3

1.5

5.2

1.5

5

ns

tPLH

CLKAB

B

1.5

3.3

4.7

1.5

6

1.5

5.5

ns

tPHL

CLKAB

B

1.5

3.5

4.8

1.5

5.8

1.5

5.3

ns

tPZH

OEBA

A

2

3.5

4.6

2

5.5

2

5.1

ns

tPZL

OEBA

A

2

3.7

4.7

2

5.8

2

5.4

ns

tPZH

OEAB

B

2

3.8

5.3

1.5

6.6

2

6.1

ns

tPZL

OEAB

B

2

3.6

5.1

2

6.2

2

5.7

ns

tPHZ

OEBA

A

2

3.6

5.4

1.4

6.6

2

6.2

ns

tPLZ

OEBA

A

1.5

3.2

4.7

1.5

5.8

1.5

5.4

ns

tPHZ

OEAB

B

2

3.4

4.8

1.4

5.6

2

5.4

ns

tPLZ

OEAB

B

1.5

3.2

4.5

1.5

5.7

1.5

5.2

ns

background image

SN54ABT162601, SN74ABT162601

18-BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS247G – AUGUST 1992 – REVISED JULY 1998

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

th

tsu

From Output

 Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1998, Texas Instruments Incorporated