background image

 

SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus+

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

UBE

 (Universal Bus Exchanger) Allows

Synchronous Data Exchange

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

description

This 9-bit, 4-port universal bus exchanger is

designed for 1.65-V to 3.6-V V

CC

 operation.

The SN74ALVCH16409 allows synchronous data

exchange between four different buses. Data flow

is controlled by the select (SEL0–SEL4) inputs. A

data-flow state is stored on the rising edge of the

clock (CLK) input if the select-enable (SELEN)

input is low. Once a data-flow state has been

established, data is stored in the flip-flop on the

rising edge of CLK if SELEN is high.

The data-flow control logic is designed to allow

glitch-free data transmission.

When preset (PRE) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To

leave the high-impedance state, both PRE and SELEN must be low and a clock pulse must be applied.

To ensure the high-impedance state during power up or power down, PRE should be tied to V

CC

 through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16409 is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC, UBE, and Widebus+ are trademarks of Texas Instruments Incorporated.

DGG OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PRE

SEL0

1A1

GND

1A2

1A3

V

CC

1A4

1A5

1A6

GND

1A7

1A8

1A9

2A1

2A2

2A3

GND

2A4

2A5

2A6

V

CC

2A7

2A8

GND

2A9

SEL1

SEL2

CLK

SELEN

1B1

GND

1B2

1B3

V

CC

1B4

1B5

1B6

GND

1B7

1B8

1B9

2B1

2B2

2B3

GND

2B4

2B5

2B6

V

CC

2B7

2B8

GND

2B9

SEL4

SEL3

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SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Function Tables

INPUTS

OUTPUT

CLK

SEND PORT

RECEIVE PORT

X

X

B0†

X

L

L

X

H

H

L

L

H

H

H

X

B0†

L

X

B0†

† Output level before the indicated steady-state

input conditions were established

DATA-FLOW CONTROL

INPUTS

DATA FLOW

PRE

SELEN

CLK

SEL0

SEL1

SEL2

SEL3

SEL4

DATA FLOW

H

X

X

X

X

X

X

X

All outputs disabled

L

H

X

X

X

X

X

No change

L

L

0

0

0

0

0

None, all I/Os off

L

L

0

0

0

0

1

Not used

L

L

0

0

0

1

0

Not used

L

L

0

0

0

1

1

Not used

L

L

0

0

1

0

0

Not used

L

L

0

0

1

0

1

Not used

L

L

0

0

1

1

0

Not used

L

L

0

0

1

1

1

Not used

L

L

0

1

0

0

0

2A to 1A and 1B to 2B

L

L

0

1

0

0

1

2A to 1A

L

L

0

1

0

1

0

2B to 1B

L

L

0

1

0

1

1

2A to 1A and 2B to 1B

L

L

0

1

1

0

0

1A to 2A and 1B to 2B

L

L

0

1

1

0

1

1A to 2A

L

L

0

1

1

1

0

1B to 2B

L

L

0

1

1

1

1

1A to 2A and 2B to 1B

L

L

1

0

0

0

0

1A to 1B and 2B to 2A

L

L

1

0

0

0

1

1A to 1B

L

L

1

0

0

1

0

2A to 2B

L

L

1

0

0

1

1

1A to 1B and 2A to 2B

L

L

1

0

1

0

0

1B to 1A and 2A to 2B

L

L

1

0

1

0

1

1B to 1A

L

L

1

0

1

1

0

2B to 2A

L

L

1

0

1

1

1

1B to 1A and 2B to 2A

L

L

1

1

0

0

0

2B to 1A and 2A to 1B

L

L

1

1

0

0

1

1B to 2A

L

L

1

1

0

1

0

2B to 1A

L

L

1

1

0

1

1

2B to 1A and 1B to 2A

L

L

1

1

1

0

0

1A to 2B and 1B to 2A

L

L

1

1

1

0

1

1A to 2B

L

L

1

1

1

1

0

2A to 1B

L

L

1

1

1

1

1

1A to 2B and 2A to 1B

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SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

Flow and Storage Control

One of Nine Channels

3

3

3

3

CLK

CLK

D

D

CLK

CLK

D

D

1Ax

2Ax

1Bx

2Bx

1Ax

1Bx

2Bx

2Ax

1Bx

2Bx

1Ax

2Ax

1Bx

1Ax

2Ax

2Bx

SEL2

SEL3

SEL4

1B

2B

CLK

SELEN

SEL0

SEL1

1A

2A

56

55

2

27

28

29

30

PRE

1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

: Except I/O ports (see Note 1) 

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

I/O ports (see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 (see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through each V

CC

 or GND 

±

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA

 (see Note 3): DGG package

81

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package

74

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

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SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

1.65

3.6

V

VCC = 1.65 V to 1.95 V

0.65 

×

VCC

VIH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V

VCC = 2.7 V to 3.6 V

2

VCC = 1.65 V to 1.95 V

0.35 

×

VCC

VIL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V

VCC = 2.7 V to 3.6 V

0.8

VI

Input voltage

0

VCC

V

VO

Output voltage

0

VCC

V

VCC = 1.65 V

–4

IOH

High level output current

VCC = 2.3 V

–12

mA

IOH

High-level output current

VCC = 2.7 V

–12

mA

VCC = 3 V

–24

VCC = 1.65 V

4

IOL

Low level output current

VCC = 2.3 V

12

mA

IOL

Low-level output current

VCC = 2.7 V

12

mA

VCC = 3 V

24

t/

v

Input transition rise or fall rate

10

ns/V

TA

Operating free-air temperature

–40

85

°

C

NOTE  4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

IOH = –100 

µ

A

1.65 V to 3.6 V

VCC–0.2

IOH = –4 mA

1.65 V

1.2

IOH = –6 mA

2.3 V

2

VOH

2.3 V

1.7

V

IOH = –12 mA

2.7 V

2.2

3 V

2.4

IOH = –24 mA

3 V

2

IOL = 100 

µ

A

1.65 V to 3.6 V

0.2

IOL = 4 mA

1.65 V

0.45

VOL

IOL = 6 mA

2.3 V

0.4

V

VOL

IOL = 12 mA

2.3 V

0.7

V

IOL = 12 mA

2.7 V

0.4

IOL = 24 mA

3 V

0.55

II

VI = VCC or GND

3.6 V

±

5

µ

A

VI = 0.58 V

1.65 V

25

VI = 1.07 V

1.65 V

–25

VI = 0.7 V

2.3 V

45

II(hold)

VI = 1.7 V

2.3 V

–45

µ

A

(

)

VI = 0.8 V

3 V

75

VI = 2 V

3 V

–75

VI = 0 to 3.6 V‡

3.6 V

±

500

IOZ§

VO = VCC or GND

3.6 V

±

10

µ

A

ICC

VI = VCC or GND,

IO = 0

3.6 V

40

µ

A

ICC

One input at VCC – 0.6 V,

Other inputs at VCC or GND

3 V to 3.6 V

750

µ

A

Ci

Control inputs

VI = VCC or GND

3.3 V

4

pF

Cio

A or B ports

VO = VCC or GND

3.3 V

8

pF

† All typical values are at VCC = 3.3 V, TA = 25

°

C.

‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

§ For I/O ports, the parameter IOZ includes the input leakage current.

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SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figures 1 through 3)

VCC = 1.8 V

VCC = 2.5 V

±

 0.2 V

VCC = 2.7 V

VCC = 3.3 V

±

 0.3 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

120

120

120

MHz

tw

Pulse duration, CLK high or low

4.2

4.2

3

ns

A or B before CLK

1.9

1.9

1.4

t

Set p time

SEL before CLK

5.1

4.2

3.5

ns

tsu

Setup time

SELEN before CLK

2.5

2.5

1.8

ns

PRE before CLK

1

1

0.7

A or B after CLK

0.8

0.8

1

th

Hold time

SEL after CLK

0

0

0

ns

SELEN after CLK

0.5

0.5

0.8

† This information was not available at the time of publication.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 1.8 V

VCC = 2.5 V

±

 0.2 V

VCC = 2.7 V

VCC = 3.3 V

±

 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MIN

MAX

MIN

MAX

MIN

MAX

fmax

120

120

120

MHz

tpd

CLK

A or B

1.5

6

5.7

1.5

5.1

ns

ten

CLK

A or B

2.4

6.9

6.3

2

5.7

ns

tdi

CLK

A or B

2.3

7.1

6

2

5.7

ns

tdis

PRE

A or B

2.8

7.5

6.5

2.5

6.1

ns

† This information was not available at the time of publication.

operating characteristics, T

= 25

°

C

PARAMETER

TEST CONDITIONS

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

UNIT

PARAMETER

TEST CONDITIONS

TYP

TYP

TYP

UNIT

C d

Power dissipation

capacitance

All outputs enabled

CL = 50 pF

f = 10 MHz

60

60

pF

Cpd

capacitance

per exchanger

All outputs disabled

CL = 50 pF,

f = 10 MHz

60

60

pF

† This information was not available at the time of publication.

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SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing diagram

CLK

SEL

(0-4)

SELEN

Selected

Input Port

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tsu

th

tsu

th

tsu

th

tpd

CLK to Output

Selected

Output Port

background image

SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 1.8 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

1 k

1 k

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

2 ns, tf 

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 1. Load Circuit and Voltage Waveforms

background image

SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.5 V 

±

 0.2 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500

 Ω

500

 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

2 ns, tf 

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 2. Load Circuit and Voltage Waveforms

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SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

 

SCES022E – JULY 1995 – REVISED FEBRUARY 1999

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.7 V AND 3.3 V 

±

 0.3 V

VOH

VOL

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500

 Ω

500

 Ω

tPLH

tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

2.7 V

0 V

VOH

VOL

0 V

VOL + 0.3 V

VOH – 0.3 V

0 V

2.7 V

0 V

0 V

tw

Input

2.7 V

2.7 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

2.5 ns, tf 

2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

6 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

0 V

2.7 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

Figure 3. Load Circuit and Voltage Waveforms

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©

 1999, Texas Instruments Incorporated