background image

 

©

 

 1997 Microchip Technology Inc.

DS30234D-page  1

 

PIC16C6X

 

8-Bit CMOS Microcontrollers

 

Devices included in this data sheet:

PIC16C6X Microcontroller Core Features:

 

• High performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program 

branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST) 

• Watchdog Timer (WDT) with its own on-chip RC 

oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• PIC16C61

• PIC16C64A

• PIC16C62

• PIC16CR64

• PIC16C62A

• PIC16C65

• PIC16CR62

• PIC16C65A

• PIC16C63

• PIC16CR65

• PIC16CR63

• PIC16C66

• PIC16C64

• PIC16C67

 

• Low-power, high-speed CMOS EPROM/ROM 

technology

• Fully static design

• Wide operating voltage range: 2.5V to 6.0V

• Commercial, Industrial, and Extended

temperature ranges

• Low-power consumption: 

 

 

 < 2 mA @ 5V, 4 MHz

 

 

 15 

 

µ

 

A typical @ 3V, 32 kHz

 

 

 < 1 

 

µ

 

A typical standby current

 

PIC16C6X Peripheral Features:

 

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler, 

can be incremented during sleep via 

external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period 

register, prescaler and postscaler 

• Capture/Compare/PWM (CCP) module(s)

• Capture is 16-bit, max resolution is 12.5 ns,

Compare is 16-bit, max resolution is 200 ns,

PWM max resolution is 10-bit. 

• Synchronous Serial Port (SSP) with SPI

 

 

 and I

 

2

 

C

 

 

• Universal Synchronous Asynchronous Receiver 

Transmitter (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with

external RD, WR and CS controls

• Brown-out detection circuitry for

Brown-out Reset (BOR)

 

PIC16C6X Features

61

62

62A

R62

63

R63

64

64A

R64

65

65A

R65

66

67

 

Program Memory 

(EPROM) x 14

1K

2K

2K

4K

2K

2K

4K

4K

8K

8K

(ROM) x 14

2K

4K

2K

4K

Data Memory (Bytes) x 8

36

128

128

128

192

192

128

128

128

192

192

192

368

368

I/O Pins

13

22

22

22

22

22

33

33

33

33

33

33

22

33

Parallel Slave Port

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Capture/Compare/PWM

Module(s)

1

1

1

2

2

1

1

1

2

2

2

2

2

Timer Modules

1

3

3

3

3

3

3

3

3

3

3

3

3

3

Serial Communication

SPI/

I

 

2

 

C

SPI/

I

 

2

 

C

SPI/

I

 

2

 

C

SPI/I

 

2

 

C,

USART

SPI/I

 

2

 

C,

USART

SPI/

I

 

2

 

C

SPI/

I

 

2

 

C

SPI/

I

 

2

 

C

SPI/I

 

2

 

C,

USART

SPI/I

 

2

 

C,

USART

SPI/I

 

2

 

C,

USART

SPI/I

 

2

 

C,

USART

SPI/I

 

2

 

C,

USART

In-Circuit Serial 

Programming

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Brown-out Reset

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Interrupt Sources

3

7

7

7

10

10

8

8

8

11

11

11

10

11

Sink/Source Current (mA) 25/20 25/25 25/25 25/25 25/25

25/25 25/25 25/25 25/25 25/25

25/25

25/25

25/25

25/25

background image

 

PIC16C6X

 

DS30234D-page  2

 

©

 

 1997 Microchip Technology Inc.

 

Pin Diagrams 

PDIP, SOIC, Windowed CERDIP

18

17

16

15

14

13

12

11

10

1

2

3

4

5

6

7

8

9

PIC16C61

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RC7

RC6

RC5/SDO

RC4/SDI/SDA

MCLR/V

PP

RA0

RA1

RA2

RA3

RA4/T0CKI

RA5/SS

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSI/T1CKI

RC1/T1OSO

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PIC16C62

RC2/CCP1

RC3/SCK/SCL

SDIP, SOIC, SSOP, Windowed CERDIP (300 mil)

RA2

RA3

RA4/T0CKI

MCLR/V

PP

V

SS

RB0/INT

RB1

RB2

RB3

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

V

DD

RB7

RB6

RB5

RB4

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

MCLR/V

PP

RA0

RA1

RA2

RA3

RA4/T0CKI

RA5/SS

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PIC16C63

RC2/CCP1

RC3/SCK/SCL

SDIP, SOIC, Windowed CERDIP (300 mil)

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RC7

RC6

RC5/SDO

RC4/SDI/SDA

MCLR/V

PP

RA0

RA1

RA2

RA3

RA4/T0CKI

RA5/SS

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PIC16C62A

RC2/CCP1

RC3/SCK/SCL

SDIP, SOIC, SSOP, Windowed CERDIP (300 mil)

PIC16CR62

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

MCLR/V

PP

RA0

RA1

RA2

RA3

RA4/T0CKI

RA5/SS

RE0/RD

RE1/WR

RE2/CS

V

DD

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0

RD1/PSP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

PIC16C65

PDIP, Windowed CERDIP

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7

RC6

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

MCLR/V

PP

RA0

RA1

RA2

RA3

RA4/T0CKI

RA5/SS

RE0/RD

RE1/WR

RE2/CS

V

DD

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSI/T1CKI

RC1/T1OSO

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0

RD1/PSP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

PIC16C64

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7

RC6

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

MCLR/V

PP

RA0

RA1

RA2

RA3

RA4/T0CKI

RA5/SS

RE0/RD

RE1/WR

RE2/CS

V

DD

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0

RD1/PSP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

PIC16C64A

PIC16C65A

PIC16CR64

PIC16CR63

PIC16CR65

PIC16C66

PIC16C67

background image

 

©

 

 1997 Microchip Technology Inc.

DS30234D-page  3

 

PIC16C6X

 

Pin Diagrams (Cont.’d)

NC

RC0/T1OSO/T1CKI

OSC2/CLKOUT

OSC1/CLKIN

V

SS

V

DD

RE2/CS

RE1/WR

RE0/RD

RA5/SS

RA4/T0CKI

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

V

SS

V

DD

RB0/INT

RB1

RB2

RB3

RC6/TX/CK

RC5/SDO

RC4/SDI/SD

A

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

NC

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

RA3

RA2

RA1

RA0

MCLR

/V

PP

RB7

RB6

RB5

RB4

NC

NC

44

43

42

41

40

39

38

37

36

35

34

22

21

20

19

18

17

16

15

14

13

12

PIC16C65

MQFP,

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RA4/T0CKI

RA5/SS

RE0/RD

RE1/WR

RE2/CS

V

DD

V

SS

OSC1/CLKIN

OSC2/CLKOUT

NC

RA3

RA2

RA1

RA0

MCLR

/V

PP

NC

RB7

RB6

RB5

RB4

NC

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

NC

RC6/TX/CK

RC5/SDO

RC4/SDI/SD

A

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI

6

5

4

3

2

1

44

43

42

41

40

28

27

26

25

24

23

22

21

20

19

18

PIC16C65

/CCP2

PLCC

RC0/T1OSO/T1CKI

NC

RC0/T1OSO/T1CKI

OSC2/CLKOUT

OSC1/CLKIN

V

SS

V

DD

RE2/CS

RE1/WR

RE0/RD

RA5/SS

RA4/T0CKI

RC7

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

V

SS

V

DD

RB0/INT

RB1

RB2

RB3

RC6

RC5/SDO

RC4/SDI/SD

A

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI

NC

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

RA3

RA2

RA1

RA0

MCLR

/V

PP

RB7

RB6

RB5

RB4

NC

NC

34

35

36

37

38

39

40

41

42

43

44

PIC16C64A

MQFP,

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7

RA4/T0CKI

RA5/SS

RE0/RD

RE1/WR

RE2/CS

V

DD

V

SS

OSC1/CLKIN

OSC2/CLKOUT

NC

RA3

RA2

RA1

RA0

MCLR

/V

PP

NC

RB7

RB6

RB5

RB4

NC

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

NC

RC6

RC5/SDO

RC4/SDI/SD

A

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI

6

5

4

3

2

1

44

43

42

41

40

28

27

26

25

24

23

22

21

20

19

18

PIC16C64A

PLCC

RC0/T1OSO/T1CKI

PIC16CR64

PIC16CR64

PIC16C65A

PIC16C65A

TQFP (PIC16C64A only)

TQFP (Not on PIC16C65)

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7

RA4/T0CKI

RA5/SS

RE0/RD

RE1/WR

RE2/CS

V

DD

V

SS

OSC1/CLKIN

NC

RA3

RA2

RA1

RA0

MCLR

/V

PP

NC

RB7

RB6

RB5

RB4

NC

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

NC

RC6

RC5/SDO

RC4/SDI/SD

A

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSO

6

5

4

3

2

1

44

43

42

41

40

28

27

26

25

24

23

22

21

20

19

18

PIC16C64

PLCC

NC

RC0/T1OSI/T1CKI

OSC2/CLKOUT

OSC1/CLKIN

V

SS

V

DD

RE2/CS

RE1/WR

RE0/RD

RA5/SS

RA4/T0CKI

RC7

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

V

SS

V

DD

RB0/INT

RB1

RB2

RB3

RC6

RC5/SDO

RC4/SDI/SD

A

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSO

NC

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

RA3

RA2

RA1

RA0

MCLR

/V

PP

RB7

RB6

RB5

RB4

NC

NC

44

43

42

41

40

39

38

37

36

35

34

22

21

20

19

18

17

16

15

14

13

12

PIC16C64

MQFP

RC0/T1OSI/T1CKI

OSC2/CLKOUT

22

21

20

19

18

17

16

15

14

13

12

PIC16CR65

PIC16CR65

PIC16C67

PIC16C67

background image

 

PIC16C6X

 

DS30234D-page  4

 

©

 

 1997 Microchip Technology Inc.

 

Table Of Contents

 

1.0 General Description ....................................................................................................................................................................... 5

2.0 PIC16C6X Device Varieties ........................................................................................................................................................... 7

3.0 Architectural Overview ................................................................................................................................................................... 9

4.0 Memory Organization................................................................................................................................................................... 19

5.0 I/O Ports ....................................................................................................................................................................................... 51

6.0 Overview of Timer Modules ......................................................................................................................................................... 63

7.0 Timer0 Module ............................................................................................................................................................................. 65

8.0 Timer1 Module ............................................................................................................................................................................. 71

9.0 Timer2 Module ............................................................................................................................................................................. 75

10.0 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................... 77

11.0 Synchronous Serial Port (SSP) Module ....................................................................................................................................... 83

12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module ....................................................................... 105

13.0 Special Features of the CPU ..................................................................................................................................................... 123

14.0 Instruction Set Summary............................................................................................................................................................ 143

15.0 Development Support ................................................................................................................................................................ 159

16.0 Electrical Characteristics for PIC16C61 ..................................................................................................................................... 163

17.0 DC and AC Characteristics Graphs and Tables for PIC16C61.................................................................................................. 173

18.0 Electrical Characteristics for PIC16C62/64 ................................................................................................................................ 183

19.0 Electrical Characteristics for PIC16C62A/R62/64A/R64 ............................................................................................................ 199

20.0 Electrical Characteristics for PIC16C65 ..................................................................................................................................... 215

21.0 Electrical Characteristics for PIC16C63/65A ............................................................................................................................. 231

22.0 Electrical Characteristics for PIC16CR63/R65........................................................................................................................... 247

23.0 Electrical Characteristics for PIC16C66/67 ................................................................................................................................ 263

24.0 DC and AC Characteristics Graphs and Tables for:

PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A, PIC16CR64, 

PIC16C65A, PIC16C66, PIC16C67 ........................................................................................................................................... 281

25.0 Packaging Information ............................................................................................................................................................... 291

Appendix A:

Modifications .............................................................................................................................................................. 307

Appendix B:

Compatibility .............................................................................................................................................................. 307

Appendix C:

What’s New................................................................................................................................................................ 308

Appendix D:

What’s Changed ........................................................................................................................................................ 308

Appendix E:

  PIC16/17 Microcontrollers ....................................................................................................................................... 309

Pin Compatibility ................................................................................................................................................................................ 315

Index .................................................................................................................................................................................................. 317

List of Equation and Examples........................................................................................................................................................... 326

List of Figures..................................................................................................................................................................................... 326

List of Tables...................................................................................................................................................................................... 330

Reader Response .............................................................................................................................................................................. 334

PIC16C6X Product Identification System........................................................................................................................................... 335

 

For register and module descriptions in this data sheet, device legends show which devices apply to those sections. For

example, the legend below shows that some features of only the PIC16C62A, PIC16CR62, PIC16C63, PIC16C64A,

PIC16CR64, and PIC16C65A are described in this section.

 

Applicable Devices

 

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

 

To Our Valued Customers

 

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional

amount of time to ensure that these documents are correct. However, we realize that we may have missed a few

things. If you find any information that is missing or appears in error, please use the reader response form in the

back of this data sheet to inform us. We appreciate your assistance in making this a better document.

background image

 

©

 

 1997 Microchip Technology Inc.

DS30234D-page  5

 

PIC16C6X

 

1.0

GENERAL DESCRIPTION

 

The PIC16CXX is a family of

 

 

 

low-cost, high-perfor-

mance, CMOS, fully-static, 8-bit microcontrollers.

All PIC16/17 microcontrollers employ an advanced

RISC architecture. The PIC16CXX microcontroller fam-

ily has enhanced core features, eight-level deep stack,

and multiple internal and external interrupt sources.

The separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

separate 8-bit wide data. The two stage instruction

pipeline allows all instructions to execute in a single

cycle, except for program branches (which require two

cycles). A total of 35 instructions (reduced instruction

set) are available. Additionally, a large register set gives

some of the architectural innovations used to achieve a

very high performance.

PIC16CXX microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

The 

 

PIC16C61

 

 device has 36 bytes of RAM and 13 I/O

pins. In addition a timer/counter is available.

The 

 

PIC16C62/62A/R62

 

 devices have 128 bytes of

RAM and 22 I/O pins. In addition, several peripheral

features are available, including: three timer/counters,

one Capture/Compare/PWM module and one serial

port. The Synchronous Serial Port can be configured

as either a 3-wire Serial Peripheral Interface (SPI

 

 

) or

the two-wire Inter-Integrated Circuit (I

 

2

 

C) bus. 

The 

 

PIC16C63/R63

 

 devices have 192 bytes of RAM,

while the 

 

PIC16C66

 

 has 368 bytes. All three devices

have 22 I/O pins. In addition, several peripheral fea-

tures are available, including: three timer/counters, two

Capture/Compare/PWM modules and two serial ports.

The Synchronous Serial Port can be configured as

either a 3-wire Serial Peripheral Interface (SPI) or the

two-wire Inter-Integrated Circuit (I

 

2

 

C) bus. The Univer-

sal Synchronous Asynchronous Receiver Transmitter

(USART) is also know as a Serial Communications

Interface or SCI.

The 

 

PIC16C64/64A/R64

 

 devices have 128 bytes of

RAM and 33 I/O pins. In addition, several peripheral

features are available, including: three timer/counters,

one Capture/Compare/PWM module and one serial

port. The Synchronous Serial Port can be configured

as either a 3-wire Serial Peripheral Interface (SPI) or

the two-wire Inter-Integrated Circuit (I

 

2

 

C) bus. An 8-bit

Parallel Slave Port is also provided.

The 

 

PIC16C65/65A/R65

 

 devices have 192 bytes of

RAM, while the 

 

PIC16C67

 

 has 368 bytes. All four

devices have 33 I/O pins. In addition, several peripheral

features are available, including: three timer/counters,

two Capture/Compare/PWM modules and two serial

ports. The Synchronous Serial Port can be configured

as either a 3-wire Serial Peripheral Interface (SPI) or

the two-wire Inter-Integrated Circuit (I

 

2

 

C) bus. The Uni-

versal Synchronous Asynchronous Receiver Transmit-

ter (USART) is also known as a Serial Communications

Interface or SCI. An 8-bit Parallel Slave Port is also pro-

vided.

The PIC16C6X device family has special features to

reduce external components, thus reducing cost,

enhancing system reliability and reducing power con-

sumption. There are four oscillator options, of which the

single pin RC oscillator provides a low-cost solution,

the LP oscillator minimizes power consumption, XT is a

standard crystal, and the HS is for High Speed crystals.

The SLEEP (power-down) mode offers a power saving

mode. The user can wake the chip from SLEEP

through several external and internal interrupts, and

resets.

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software lock-

up. 

A UV erasable CERDIP packaged version is ideal for

code development, while the cost-effective

One-Time-Programmable (OTP) version is suitable for

production in any volume. 

The PIC16C6X family fits perfectly in applications rang-

ing from high-speed automotive and appliance control

to low-power remote sensors, keyboards and telecom

processors. The EPROM technology makes customi-

zation of application programs (transmitter codes,

motor speeds, receiver frequencies, etc.) extremely

fast and convenient. The small footprint packages

make this microcontroller series perfect for all applica-

tions with space limitations. Low-cost, low-power, high

performance, ease-of-use, and I/O flexibility make the

PIC16C6X very versatile even in areas where no micro-

controller use has been considered before (e.g. timer

functions, serial communication, capture and compare,

PWM functions, and co-processor applications). 

 

1.1

Family and Upward Compatibility

 

Those users familiar with the PIC16C5X family of

microcontrollers will realize that this is an enhanced

version of the PIC16C5X architecture. Please refer to

Appendix A for a detailed list of enhancements. Code

written for PIC16C5X can be easily ported to

PIC16CXX family of devices (Appendix B).

 

1.2

Development Support

 

PIC16C6X devices are supported by the complete line

of Microchip Development tools.

Please refer to Section 15.0 for more details about

Microchip’s development tools.

background image

 

PIC16C6X

 

DS30234D-page  6

 

©

 

 1997 Microchip Technology Inc.

 

TABLE 1-1:

PIC16C6X FAMILY OF DEVICES

 

PIC16C61

PIC16C62A

PIC16CR62

PIC16C63

PIC16CR63

Clock

 

Maximum Frequency 

of Operation (MHz)

20

20

20

20

20

 

Memory

 

EPROM Program Memory 

(x14 words)

1K

2K

4K

ROM Program Memory 

(x14 words)

2K

4K

Data Memory (bytes)

36

128

128

192

192

 

Peripherals

 

Timer Module(s)

TMR0

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

Capture/Compare/

PWM Module(s)

1

1

2

2

Serial Port(s) 

(SPI/I

 

2

 

C, USART)

SPI/I

 

2

 

C

SPI/I

 

2

 

C

SPI/I

 

2

 

C,

USART

SPI/I

 

2

 

C

USART

Parallel Slave Port

 

Features

 

Interrupt Sources

3

7

7

10

10

I/O Pins

13

22

22

22

22

Voltage Range (Volts)

3.0-6.0

2.5-6.0

2.5-6.0

2.5-6.0

2.5-6.0

In-Circuit Serial Programming

Yes

Yes

Yes

Yes

Yes

Brown-out Reset

Yes

Yes

Yes

Yes

Packages

18-pin DIP, SO 28-pin SDIP,

SOIC, SSOP

28-pin SDIP,

SOIC, SSOP

28-pin SDIP,

SOIC

28-pin SDIP,

SOIC

 

PIC16C64A

PIC16CR64

PIC16C65A

PIC16CR65

PIC16C66

PIC16C67

Clock

 

Maximum Frequency 

of Operation (MHz)

20

20

20

20

20

20

 

Memory

 

EPROM Program Memory 

(x14 words)

2K

4K

8K

8K

ROM Program Memory  (x14 

words)

2K

4K

Data Memory (bytes)

128

128

192

192

368

368

 

Peripherals

Timer Module(s)

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

Capture/Compare/PWM Mod-

ule(s)

1

1

2

2

2

2

Serial Port(s) (SPI/I

2

C, USART)

SPI/I

2

C

SPI/I

2

C

SPI/I

2

C, 

USART

SPI/I

2

C, 

USART

SPI/I

2

C,

USART

SPI/I

2

C, 

USART

Parallel Slave Port

Yes

Yes

Yes

Yes

Yes

Features

Interrupt Sources

8

8

11

11

10

11

I/O Pins

33

33

33

33

22

33

Voltage Range (Volts)

2.5-6.0

2.5-6.0

2.5-6.0

2.5-6.0

2.5-6.0

2.5-6.0

In-Circuit Serial Programming

Yes

Yes

Yes

Yes

Yes

Yes

Brown-out Reset

Yes

Yes

Yes

Yes

Yes

Yes

Packages

40-pin DIP;

44-pin PLCC,

MQFP, TQFP

40-pin DIP;

44-pin PLCC,

MQFP, TQFP

40-pin DIP;

44-pin PLCC,

MQFP, TQFP

40-pin DIP;

44-pin 

PLCC, 

MQFP, 

TQFP

28-pin SDIP,

SOIC

40-pin DIP;

44-pin 

PLCC, 

MQFP, 

TQFP

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current

capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  7

PIC16C6X

2.0

PIC16C6X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements, the proper device option can be selected

using the information in the PIC16C6X Product Identifi-

cation System section at the end of this data sheet.

When placing orders, please use that page of the data

sheet to specify the correct part number.

For the PIC16C6X family of devices, there are four

device “types” as indicated in the device number:

1.

C, as in PIC16C64. These devices have

EPROM type memory and operate over the

standard voltage range.

2.

LC, as in PIC16LC64. These devices have

EPROM type memory and operate over an

extended voltage range.

3.

CR, as in PIC16CR64. These devices have

ROM program memory and operate over the

standard voltage range.

4.

LCR, as in PIC16LCR64. These devices have

ROM program memory and operate over an

extended voltage range.

2.1

UV Erasable Devices

The UV erasable version, offered in CERDIP package

is optimal for prototype development and pilot

programs. This version can be erased and

reprogrammed to any of the oscillator modes.

Microchip's PICSTART

®

 Plus and PRO 

MATE

® 

II

programmers both support programming of the

PIC16C6X.

2.2

One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the flexibility for frequent code

updates and small volume applications.

The OTP devices, packaged in plastic packages, per-

mit the user to program them once. In addition to the

program memory, the configuration bits must also be

programmed.

2.3

Quick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for fac-

tory production orders. This service is made available

for users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

lized. The devices are identical to the OTP devices but

with all EPROM locations and configuration options

already programmed by the factory. Certain code and

prototype verification procedures apply before produc-

tion shipments are available. Please contact your local

Microchip Technology sales office for more details.

2.4

Serialized Quick-Turnaround

Production (SQTP

SM

) Devices

Microchip offers a unique programming service where

a few user-defined locations in each device are pro-

grammed with different serial numbers. The serial num-

bers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password, or ID number.

ROM devices do not allow serialization information in

the program memory space. The user may have this

information programmed in the data memory space.

For information on submitting ROM code, please con-

tact your regional sales office.

2.5

Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of

the highest volume parts, thus giving customers a low

cost option for high volume, mature products.

For information on submitting ROM code, please con-

tact your regional sales office.

background image

PIC16C6X

DS30234D-page  8

©

 1997 Microchip Technology Inc.

NOTES:

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  9

PIC16C6X

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be

attributed to a number of architectural features com-

monly found in RISC microprocessors. To begin with,

the PIC16CXX uses a Harvard architecture, in which,

program and data are accessed from separate memo-

ries using separate buses. This improves bandwidth

over traditional von Neumann architecture where pro-

gram and data may be fetched from the same memory

using the same bus. Separating program and data bus-

ses further allows instructions to be sized differently

than 8-bit wide data words. Instruction opcodes are

14-bits wide making it possible to have all single word

instructions. A 14-bit wide program memory access

bus fetches a 14-bit instruction in a single cycle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions (Example 3-1). Consequently, all instructions exe-

cute in a single cycle (200 ns @ 20 MHz) except for

program branches. 

The PIC16C61 addresses 1K x 14 of program memory.

The PIC16C62/62A/R62/64/64A/R64 address 2K x 14 of

program memory, and the PIC16C63/R63/65/65A/R65

devices address 4K x 14 of program memory. The

PIC16C66/67 address 8K x 14 program memory. All

program memory is internal.

The PIC16CXX can directly or indirectly address its

register files or data memory. All special function reg-

isters including the program counter are mapped in

the data memory. The PIC16CXX has an orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of

“special optimal situations” makes programming with

the PIC16CXX simple yet efficient, thus significantly

reducing the learning curve.

The PIC16CXX device contains an 8-bit ALU and work-

ing register (W). The ALU is a general purpose arith-

metic unit. It performs arithmetic and Boolean functions

between data in the working register and any register

file.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift, and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature. In two-operand instructions, typically

one operand is the working register (W register), the

other operand is a file register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending upon the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. Bits C and DC

operate as a borrow and digit  borrow out bit, respec-

tively, in subtraction. See the 

SUBLW

 and 

SUBWF

instructions for examples.

background image

PIC16C6X

DS30234D-page  10

©

 1997 Microchip Technology Inc.

FIGURE 3-1:

PIC16C61 BLOCK DIAGRAM        

EPROM

Program

Memory

1K x 14

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

36 x 8

Direct Addr

7

9

Addr MUX

Indirect

Addr

8

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

V

DD

, V

SS

Timer0

3

PORTA

PORTB

RA1

RA4/T0CKI

RB0/INT

RB7:RB1

8

8

RAM Addr

(1)

Note 1: Higher order bits are from the STATUS register.

RA0

RA2

RA3

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  11

PIC16C6X

FIGURE 3-2:

PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM

EPROM/

Program

Memory

2K x 14

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

128 x 8

Direct Addr

7

RAM Addr

(1)

9

Addr MUX

Indirect

Addr

8

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

V

DD

, V

SS

Synchronous

Serial Port

3

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI

RA5/SS

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI

(4)

RC1/T1OSI

(4)

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6

RC7

RE0/RD

RE1/WR

RE2/CS

RD0/PSP0

8

8

(Note 2)

Brown-out

Reset

(3)

ROM

Timer0

Timer1

Timer2

CCP1

RA1

RA0

RA2

RA3

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

Parallel Slave

Port

Note 1:

Higher order bits are from the STATUS register.

2:

PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C62/62A/R62.

3:

Brown-out Reset is not available on the PIC16C62/64.

4:

Pin functions T1OSI and T1OSO are swapped on the PIC16C62/64.

background image

PIC16C6X

DS30234D-page  12

©

 1997 Microchip Technology Inc.

FIGURE 3-3:

PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM

Synchronous

Serial Port

EPROM

Program

Memory

4K x 14

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

192 x 8

Direct Addr

7

RAM Addr

(1)

9

Addr MUX

Indirect

Addr

8

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

V

DD

, V

SS

3

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI

RA5/SS

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RE0/RD

RE1/WR

RE2/CS

8

8

Brown-out

Reset

(3)

(Note 2)

USART

Timer0

Timer1

Timer2

CCP2

CCP1

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

RA1

RA0

RA2

RA3

Parallel Slave

Port

Note 1:

Higher order bits are from the STATUS register.

2:

PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C63/R63.

3:

Brown-out Reset is not available on the PIC16C65.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  13

PIC16C6X

FIGURE 3-4:

PIC16C66/67 BLOCK DIAGRAM

             

        

Synchronous

Serial Port

EPROM

Program

Memory

8K x 14

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

368 x 8

Direct Addr

7

RAM Addr

(1)

9

Addr MUX

Indirect

Addr

8

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

V

DD

, V

SS

3

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI

RA5/SS

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RE0/RD

RE1/WR

RE2/CS

8

8

Brown-out

Reset

(Note 2)

USART

Timer0

Timer1

Timer2

CCP2

CCP1

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

RA1

RA0

RA2

RA3

Parallel Slave

Port

Note 1:

Higher order bits are from the STATUS register.

2:

PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C66.

background image

PIC16C6X

DS30234D-page  14

©

 1997 Microchip Technology Inc.

TABLE 3-1:

PIC16C61 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SOIC

Pin#

Pin Type

Buffer

Type

Description

OSC1/CLKIN

16

16

I

ST/CMOS

(1)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

15

15

O

Oscillator crystal output. Connects to crystal or resonator in crystal 

oscillator mode. In RC mode, the pin outputs CLKOUT which has 

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR/V

PP

4

4

I/P

ST

Master clear reset input or programming voltage input. This pin is an 

active low reset to the device. 

PORTA is a bi-directional I/O port.

RA0

17

17

I/O

TTL

RA1

18

18

I/O

TTL

RA2

1

1

I/O

TTL

RA3

2

2

I/O

TTL

RA4/T0CKI

3

3

I/O

ST

RA4 can also be the clock input to the Timer0 timer/counter.

Output is open drain type.

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-up on all inputs. 

RB0/INT

6

6

I/O

TTL/ST

(2)

RB0 can also be the external interrupt pin.

RB1

7

7

I/O

TTL

RB2

8

8

I/O

TTL

RB3

9

9

I/O

TTL

RB4

10

10

I/O

TTL

Interrupt on change pin.

RB5

11

11

I/O

TTL

Interrupt on change pin.

RB6

12

12

I/O

TTL/ST

(3)

Interrupt on change pin. Serial programming clock.

RB7

13

13

I/O

TTL/ST

(3)

Interrupt on change pin. Serial programming data.

V

SS

5

5

P

Ground reference for logic and I/O pins.

V

DD

14

14

P

Positive supply for logic and I/O pins.

Legend: I = input

O = output

I/O = input/output

P = power

— = Not used

TTL = TTL input

ST = Schmitt Trigger input

Note 1:

This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

2:

This buffer is a Schmitt Trigger input when configured as the external interrupt.

3:

This buffer is a Schmitt Trigger input when used in serial programming mode.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  15

PIC16C6X

TABLE 3-2:

PIC16C62/62A/R62/63/R63/66 PINOUT DESCRIPTION

Pin Name

Pin#

Pin Type

Buffer

Type

Description

OSC1/CLKIN

9

I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

10

O

Oscillator crystal output. Connects to crystal or resonator in crys-

tal oscillator mode. In RC mode, the pin outputs CLKOUT which 

has 1/4 the frequency of OSC1, and denotes the instruction cycle 

rate.

MCLR/V

PP

1

I/P

ST

Master clear reset input or programming voltage input. This pin is 

an active low reset to the device. 

PORTA is a bi-directional I/O port.

RA0

2

I/O

TTL

RA1

3

I/O

TTL

RA2

4

I/O

TTL

RA3

5

I/O

TTL

RA4/T0CKI

6

I/O

ST

RA4 can also be the clock input to the Timer0 timer/counter.

Output is open drain type.

RA5/SS

7

I/O

TTL

RA5 can also be the slave select for the synchronous serial

port.

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-up on all inputs. 

RB0/INT

21

I/O

TTL/ST

(4)

RB0 can also be the external interrupt pin.

RB1

22

I/O

TTL

RB2

23

I/O

TTL

RB3

24

I/O

TTL

RB4

25

I/O

TTL

Interrupt on change pin.

RB5

26

I/O

TTL

Interrupt on change pin.

RB6

27

I/O

TTL/ST

(5)

Interrupt on change pin. Serial programming clock.

RB7

28

I/O

TTL/ST

(5)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO

(1)

/T1CKI

11

I/O

ST

RC0 can also be the Timer1 oscillator output

(1)

 or Timer1

clock input.

RC1/T1OSI

(1)

/CCP2

(2)

12

I/O

ST

RC1 can also be the Timer1 oscillator input

(1)

 or Capture2

input/Compare2 output/PWM2 output

(2)

.

RC2/CCP1

13

I/O

ST

RC2 can also be the Capture1 input/Compare1 out-

put/PWM1 output.

RC3/SCK/SCL

14

I/O

ST

RC3 can also be the synchronous serial clock input/output

for both SPI and I

2

C modes.

RC4/SDI/SDA

15

I/O

ST

RC4 can also be the SPI Data In (SPI mode) or 

data I/O (I

2

C mode).

RC5/SDO

16

I/O

ST

RC5 can also be the SPI Data Out (SPI mode).

RC6/TX/CK

(2)

17

I/O

ST

RC6 can also be the USART Asynchronous Transmit

(2)

 or

Synchronous Clock

(2)

.

RC7/RX/DT

(2)

18

I/O

ST

RC7 can also be the USART Asynchronous Receive

(2)

 or

Synchronous Data

(2)

.

V

SS

8,19

P

Ground reference for logic and I/O pins.

V

DD

20

P

Positive supply for logic and I/O pins.

Legend: I = input

O = output

I/O = input/output

P = power

— = Not used

TTL = TTL input

ST = Schmitt Trigger input

Note 1:

Pin functions T1OSO and T1OSI are reversed on the PIC16C62.

2:

The USART and CCP2 are not available on the PIC16C62/62A/R62.

3:

This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

4:

This buffer is a Schmitt Trigger input when configured as the external interrupt.

5:

This buffer is a Schmitt Trigger input when used in serial programming mode.

background image

PIC16C6X

DS30234D-page  16

©

 1997 Microchip Technology Inc.

TABLE 3-3:

PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION 

Pin Name

DIP

Pin#

PLCC

Pin#

TQFP

MQFP

Pin#

Pin 

Type

Buffer

Type

Description

OSC1/CLKIN

13

14

30

I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

14

15

31

O

Oscillator crystal output. Connects to crystal or resonator in 

crystal oscillator mode. In RC mode, the pin outputs CLK-

OUT which has 1/4 the frequency of OSC1, and denotes the 

instruction cycle rate.

MCLR/V

PP

1

2

18

I/P

ST

Master clear reset input or programming voltage input. This 

pin is an active low reset to the device. 

PORTA is a bi-directional I/O port.

RA0

2

3

19

I/O

TTL

RA1

3

4

20

I/O

TTL

RA2

4

5

21

I/O

TTL

RA3

5

6

22

I/O

TTL

RA4/T0CKI

6

7

23

I/O

ST

RA4 can also be the clock input to the Timer0

timer/counter. Output is open drain type.

RA5/SS

7

8

24

I/O

TTL

RA5 can also be the slave select for the synchronous

serial port.

PORTB is a bi-directional I/O port. PORTB can be software 

programmed for internal weak pull-up on all inputs. 

RB0/INT

33

36

8

I/O

TTL/ST

(4)

RB0 can also be the external interrupt pin.

RB1

34

37

9

I/O

TTL

RB2

35

38

10

I/O

TTL

RB3

36

39

11

I/O

TTL

RB4

37

41

14

I/O

TTL

Interrupt on change pin.

RB5

38

42

15

I/O

TTL

Interrupt on change pin.

RB6

39

43

16

I/O

TTL/ST

(5)

Interrupt on change pin. Serial programming clock.

RB7

40

44

17

I/O

TTL/ST

(5)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO

(1)

/T1CKI

15

16

32

I/O

ST

RC0 can also be the Timer1 oscillator output

(1) 

or

Timer1 clock input.

RC1/T1OSI

(1)

/CCP2

(2)

16

18

35

I/O

ST

RC1 can also be the Timer1 oscillator input

(1)

 or

Capture2 input/Compare2 output/PWM2 output

(2)

.

RC2/CCP1

17

19

36

I/O

ST

RC2 can also be the Capture1 input/Compare1 out-

put/PWM1 output.

RC3/SCK/SCL

18

20

37

I/O

ST

RC3 can also be the synchronous serial clock input/out-

put for both SPI and I

2

C modes.

RC4/SDI/SDA

23

25

42

I/O

ST

RC4 can also be the SPI Data In (SPI mode) or 

data I/O (I

2

C mode).

RC5/SDO

24

26

43

I/O

ST

RC5 can also be the SPI Data Out (SPI mode).

RC6/TX/CK

(2)

25

27

44

I/O

ST

RC6 can also be the USART Asynchronous Transmit

(2)

or Synchronous Clock

(2)

.

RC7/RX/DT

(2)

26

29

1

I/O

ST

RC7 can also be the USART Asynchronous Receive

(2)

or Synchronous Data

(2)

.

Legend: I = input

O = output

I/O = input/output

P = power

— = Not used

TTL = TTL input

ST = Schmitt Trigger input

Note 1:

Pin functions T1OSO and T1OSI are reversed on the PIC16C64.

2:

CCP2 and the USART are not available on the PIC16C64/64A/R64.

3:

This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

4:

This buffer is a Schmitt Trigger input when configured as the external interrupt.

5:

This buffer is a Schmitt Trigger input when used in serial programming mode.

6:

This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave 

Port mode (for interfacing to a microprocessor bus).

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  17

PIC16C6X

PORTD can be a bi-directional I/O port or parallel slave port 

for interfacing to a microprocessor bus.

RD0/PSP0

19

21

38

I/O

ST/TTL

(6)

RD1/PSP1

20

22

39

I/O

ST/TTL

(6)

RD2/PSP2

21

23

40

I/O

ST/TTL

(6)

RD3/PSP3

22

24

41

I/O

ST/TTL

(6)

RD4/PSP4

27

30

2

I/O

ST/TTL

(6)

RD5/PSP5

28

31

3

I/O

ST/TTL

(6)

RD6/PSP6

29

32

4

I/O

ST/TTL

(6)

RD7/PSP7

30

33

5

I/O

ST/TTL

(6)

PORTE is a bi-directional I/O port.

RE0/RD

8

9

25

I/O

ST/TTL

(6)

RE0 can also be read control for the parallel slave port.

RE1/WR

9

10

26

I/O

ST/TTL

(6)

RE1 can also be write control for the parallel slave port.

RE2/CS

10

11

27

I/O

ST/TTL

(6)

RE2 can also be select control for the parallel slave port.

V

SS

12,31

13,34

6,29

P

Ground reference for logic and I/O pins.

V

DD

11,32

12,35

7,28

P

Positive supply for logic and I/O pins.

NC

1,17,

28,40

12,13,

33,34

These pins are not internally connected. These pins should 

be left unconnected.

TABLE 3-3:

PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION (Cont.’d)

Pin Name

DIP

Pin#

PLCC

Pin#

TQFP

MQFP

Pin#

Pin 

Type

Buffer

Type

Description

Legend: I = input

O = output

I/O = input/output

P = power

— = Not used

TTL = TTL input

ST = Schmitt Trigger input

Note 1:

Pin functions T1OSO and T1OSI are reversed on the PIC16C64.

2:

CCP2 and the USART are not available on the PIC16C64/64A/R64.

3:

This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

4:

This buffer is a Schmitt Trigger input when configured as the external interrupt.

5:

This buffer is a Schmitt Trigger input when used in serial programming mode.

6:

This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave 

Port mode (for interfacing to a microprocessor bus).

background image

PIC16C6X

DS30234D-page  18

©

 1997 Microchip Technology Inc.

3.1

Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3, and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clock and instruction execution flow is

shown in Figure 3-5.

3.2

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3, and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g. 

GOTO

)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-5:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

OSC1

Q1

Q2

Q3

Q4

PC

(Program counter)

OSC2/CLKOUT

(RC mode)

PC

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

Internal

Phase

Clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 

Tcy0

Tcy1

Tcy2

Tcy3

Tcy4

Tcy5

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. CALL  SUB_1

Fetch 3

Execute 3

4. BSF   PORTA, BIT3 (Forced NOP)

Fetch 4

Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  19

PIC16C6X

4.0

MEMORY ORGANIZATION

4.1

Program Memory Organization

The PIC16C6X family has a 13-bit program counter

capable of addressing an 8K x 14 program memory

space. The amount of program memory available to

each device is listed below:

For those devices with less than 8K program memory,

accessing a location above the physically implemented

address will cause a wraparound. 

The reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 4-1:

PIC16C61 PROGRAM 

MEMORY MAP AND STACK 

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Device

Program 

Memory

Address Range

PIC16C61

1K x 14

0000h-03FFh

PIC16C62

2K x 14

0000h-07FFh

PIC16C62A

2K x 14

0000h-07FFh

PIC16CR62

2K x 14

0000h-07FFh

PIC16C63

4K x 14

0000h-0FFFh

PIC16CR63

4K x 14

0000h-0FFFh

PIC16C64

2K x 14

0000h-07FFh

PIC16C64A

2K x 14

0000h-07FFh

PIC16CR64

2K x 14

0000h-07FFh

PIC16C65

4K x 14

0000h-0FFFh

PIC16C65A

4K x 14

0000h-0FFFh

PIC16CR65

4K x 14

0000h-0FFFh

PIC16C66

8K x 14

0000h-1FFFh

PIC16C67

8K x 14

0000h-1FFFh

PC<12:0>

Stack Level 1

Stack Level 8

••

User Memor

y

Space

CALL, RETURN

RETFIE, RETLW

13

0000h

0004h

1FFFh

03FFh

0400h

On-chip Program

Memory

0005h

Reset Vector

Peripheral Interrupt Vector

FIGURE 4-2:

PIC16C62/62A/R62/64/64A/

R64 PROGRAM MEMORY 

MAP AND STACK 

FIGURE 4-3:

PIC16C63/R63/65/65A/R65 

PROGRAM MEMORY MAP 

AND STACK

PC<12:0>

Stack Level 1

Stack Level 8

User Memor

y

Space

CALL, RETURN

RETFIE, RETLW

13

0000h

0004h

1FFFh

07FFh

0800h

On-chip Program

Memory

0005h

Reset Vector

Peripheral Interrupt Vector

••

PC<12:0>

Stack Level 1

Stack Level 8

User Memor

y

Space

CALL, RETURN

RETFIE, RETLW

13

0000h

0004h

1FFFh

07FFh

0FFFh

0800h

1000h

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

0005h

Reset Vector

Peripheral Interrupt Vector

••

background image

PIC16C6X

DS30234D-page  20

©

 1997 Microchip Technology Inc.

FIGURE 4-4:

PIC16C66/67 PROGRAM 

MEMORY MAP AND STACK

4.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits. 

RP1:RP0 (STATUS<6:5>)  

  = 00 

  Bank0

  = 01 

  Bank1

  = 10 

  Bank2

  = 11 

  Bank3

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain special

function registers. Some “high use” special function

registers from one bank may be mirrored in another

bank for code reduction and quicker access. 

4.2.1

GENERAL PURPOSE REGISTERS

These registers are accessed either directly or indi-

rectly through the File Select Register (FSR)

(Section 4.5).

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PC<12:0>

Stack Level 1

Stack Level 8

User Memor

y

Space

CALL, RETURN

RETFIE, RETLW

13

0000h

0004h

0FFFh

1000h

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

0005h

Reset Vector

Peripheral Interrupt Vector

••

07FFh

0800h

On-chip Program

Memory (Page 2)

On-chip Program

Memory (Page 3)

17FFh

1800h

1FFFh

For the PIC16C61, general purpose register locations

8Ch-AFh of Bank 1 are not physically implemented.

These locations are mapped into 0Ch-2Fh of Bank 0.

FIGURE 4-5:

PIC16C61 REGISTER FILE 

MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

2Fh

30h

7Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

AFh

B0h

FFh

Bank 0

Bank 1

INDF

(1)

INDF

(1)

TMR0

OPTION

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

 

General

Purpose

Register

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

Mapped

in Bank 0

(2)

Unimplemented data memory location; read as '0'.

Note 1:

Not a physical register.

2:

These locations are unimplemented in 

Bank 1. Any access to these locations will 

access the corresponding Bank 0 register.

File Address

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  21

PIC16C6X

FIGURE 4-6:

PIC16C62/62A/R62/64/64A/

R64 REGISTER FILE MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

7Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

FFh

Bank 0

Bank 1

INDF

(1)

INDF

(1)

TMR0

OPTION

PCL

STATUS

FSR

PORTA

PORTB

PORTD

(2)

PORTE

(2)

PCLATH

INTCON

PCL

STATUS

FSR

TRISA

TRISB

TRISD

(2)

TRISE

(2)

PCLATH

INTCON

Unimplemented data memory location; read as '0'.

PORTC

TRISC

PIR1

PIE1

TMR1L

PCON

TMR1H

T1CON

TMR2

T2CON

PR2

SSPBUF

SSPADD

SSPSTAT

SSPCON

CCPR1L

CCPR1H

CCP1CON

General

Purpose

Register

0Dh

8Dh

0Eh

8Eh

0Fh

8Fh

10h

90h

11h

91h

12h

92h

13h

93h

14h

94h

15h

95h

16h

96h

17h

97h

18h

98h

1Fh

9Fh

20h

A0h

BFh

C0h

General

Purpose

Register

Note 1:

Not a physical register.

2:

PORTD and PORTE are not available on 

the PIC16C62/62A/R62.

File Address

FIGURE 4-7:

PIC16C63/R63/65/65A/R65 

REGISTER FILE MAP 

File Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

7Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

FFh

Bank 0

Bank 1

INDF

(1)

INDF

(1)

TMR0

OPTION

PCL

STATUS

FSR

PORTA

PORTB

PORTD

(2)

PORTE

(2)

PCLATH

INTCON

PCL

STATUS

FSR

TRISA

TRISB

TRISD

(2)

TRISE

(2)

PCLATH

INTCON

Unimplemented data memory location; read as '0'.

PORTC

TRISC

PIR1

PIE1

PIR2

PIE2

TMR1L

PCON

TMR1H

T1CON

TMR2

T2CON

PR2

SSPBUF

SSPADD

SSPSTAT

SSPCON

CCPR1L

CCPR1H

CCP1CON

CCPR2L

CCPR2H

CCP2CON

RCSTA

TXREG

RCREG

TXSTA

SPBRG

General

Purpose

Register

General

Purpose

Register

0Dh

8Dh

0Eh

8Eh

0Fh

8Fh

10h

90h

11h

91h

12h

92h

13h

93h

14h

94h

15h

95h

16h

96h

17h

97h

18h

98h

19h

99h

1Ah

9Ah

1Bh

9Bh

1Ch

9Ch

1Dh

9Dh

1Eh

9Eh

1Fh

9Fh

20h

A0h

Note 1:

Not a physical register

2:

PORTD and PORTE are not available on 

the PIC16C63/R63.

File Address

background image

PIC16C6X

DS30234D-page  22

©

 1997 Microchip Technology Inc.

FIGURE 4-8:

PIC16C66/67 DATA MEMORY MAP  

Indirect addr.

(*)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PCLATH

INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h

A0h

7Fh

FFh

Bank 0

Bank 1

 

Unimplemented data memory locations, read as '0'.

 *

Not a physical register.

These registers are not implemented on the PIC16C66.

Note:

The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require

relocation of data memory usage in the user application code if upgrading to the PIC16C66/67.

File

Address

Indirect addr.

(*)

Indirect addr.

(*)

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

120h

1A0h

17Fh

1FFh

Bank 2

Bank 3

Indirect addr.

(*)

PORTD

PORTE

TRISD

TRISE

TMR0

OPTION

PIR2

PIE2

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

TXSTA

SPBRG

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

1EFh

1F0h

EFh

F0h

16Fh

170h

General

Purpose

Register

General

Purpose

Register

TRISB

PORTB

96 Bytes

80 Bytes

80 Bytes

80 Bytes

16 Bytes

16 Bytes

(1)

(1)

(1)

(1)

accesses

70h-7Fh

in Bank 0

accesses

70h-7Fh

in Bank 0

accesses

70h-7Fh

in Bank 0

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  23

PIC16C6X

4.2.2

SPECIAL FUNCTION REGISTERS:

The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The special function registers can be classified into two

sets (core and peripheral). The registers associated

with the “core” functions are described in this section

and those related to the operation of the peripheral fea-

tures are described in the section of that peripheral fea-

ture.

TABLE 4-1:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C61

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR

Value on

all other

resets

(3)

   

Bank 0

00h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h

(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

03h

(1)

STATUS

IRP

(4)

RP1

(4)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

04h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

PORTA Data Latch when written: PORTA pins when read

---x xxxx

---u uuuu

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

Unimplemented

08h

Unimplemented

09h

Unimplemented

0Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh

(1)

INTCON

GIE 

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0-00 000x

0-00 000u

   Bank 1

80h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

82h

(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

83h

(1)

STATUS

IRP

(4)

RP1

(4)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

84h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

PORTA Data Direction Register

---1 1111

---1 1111

86h

TRISB

PORTB Data Direction Control Register

1111 1111

1111 1111

87h

Unimplemented

88h

Unimplemented

89h

Unimplemented

8Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

8Bh

(1)

INTCON

GIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0-00 000x  0-00  000u

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented locations read as '0'. 

Shaded locations are unimplemented and read as ‘0’

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose con-

tents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset.

4:

The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.

background image

PIC16C6X

DS30234D-page  24

©

 1997 Microchip Technology Inc.

TABLE 4-2:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62  

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

   

Bank 0

00h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h

(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

03h

(1)

STATUS

IRP

(5)

RP1

(5)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

04h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

PORTA Data Latch when written: PORTA pins when read

--xx xxxx

--uu uuuu

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx

uuuu uuuu

08h

Unimplemented

09h

Unimplemented

0Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh

(1)

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

(6)

(6)

SSPIF

CCP1IF

TMR2IF

TMR1IF

00-- 0000

00-- 0000

0Dh

Unimplemented

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

10h

T1CON

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

--00 0000

--uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000

0000 0000

12h

T2CON

TOUTPS3 TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

-000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

0000 0000

15h

CCPR1L

Capture/Compare/PWM1 (LSB)

xxxx xxxx

uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM1 (MSB)

xxxx xxxx

uuuu uuuu

17h

CCP1CON

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

--00 0000

18h-1Fh

Unimplemented

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

The BOR  bit is reserved on the PIC16C62, always maintain this bit set.

5:

The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear.

6:

PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  25

PIC16C6X

   Bank 1

80h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

82h

(1)

PCL

Program Counter's (PC)   Least Significant Byte

0000 0000

0000 0000

83h

(1)

STATUS

IRP

(5)

RP1

(5)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

84h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

PORTA Data Direction Register

--11 1111

--11 1111

86h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

87h

TRISC

PORTC Data Direction Register

1111 1111

1111 1111

88h

Unimplemented

89h

Unimplemented

8Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

8Bh

(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

8Ch

PIE1

(6)

(6)

SSPIE

CCP1IE

TMR2IE

TMR1IE

00-- 0000

00-- 0000

8Dh

Unimplemented

8Eh

PCON

POR

BOR

(4)

---- --qq

---- --uu

8Fh

Unimplemented

90h

Unimplemented

91h

Unimplemented

92h

PR2

Timer2 Period Register

1111 1111

1111 1111

93h

SSPADD

Synchronous Serial Port (I

2

C mode) Address Register

0000 0000

0000 0000

94h

SSPSTAT

D/A

P

S

R/W

UA

BF

--00 0000

--00 0000

95h-9Fh

Unimplemented

TABLE 4-2:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62  (Cont.’d)

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

The BOR  bit is reserved on the PIC16C62, always maintain this bit set.

5:

The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear.

6:

PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  26

PIC16C6X

TABLE 4-3:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63  

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

   

Bank 0

00h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h

(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

03h

(1)

STATUS

IRP

(4)

RP1

(4)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

04h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

PORTA Data Latch when written: PORTA pins when read

--xx xxxx

--uu uuuu

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx

uuuu uuuu

08h

Unimplemented

09h

Unimplemented

0Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh

(1)

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

(5)

(5)

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

0000 0000

0Dh

PIR2

—–

CCP2IF

---- ---0

---- ---0

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

10h

T1CON

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

--00 0000

--uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000

0000 0000

12h

T2CON

TOUTPS3 TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

-000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

0000 0000

15h

CCPR1L

Capture/Compare/PWM1 (LSB)

xxxx xxxx

uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM1 (MSB)

xxxx xxxx

uuuu uuuu

17h

CCP1CON

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

--00 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

FERR

OERR

RX9D

0000 -00x

0000 -00x

19h

TXREG

USART Transmit Data Register

0000 0000

0000 0000

1Ah

RCREG

USART Receive Data Register

0000 0000

0000 0000

1Bh

CCPR2L

Capture/Compare/PWM2 (LSB)

xxxx xxxx

uuuu uuuu

1Ch

CCPR2H

Capture/Compare/PWM2 (MSB)

xxxx xxxx

uuuu uuuu

1Dh

CCP2CON

CCP2X

CCP2Y

CCP2M3

CCP2M2

CCP2M1

CCP2M0

--00 0000

--00 0000

1Eh-1Fh

Unimplemented

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear.

5:

PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  27

PIC16C6X

   Bank 1

80h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

82h

(1)

PCL

Program Counter's (PC)   Least Significant Byte

0000 0000

0000 0000

83h

(1)

STATUS

IRP

(4)

RP1

(4)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

84h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

PORTA Data Direction Register

--11 1111

--11 1111

86h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

87h

TRISC

PORTC Data Direction Register

1111 1111

1111 1111

88h

Unimplemented

89h

Unimplemented

8Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

8Bh

(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

8Ch

PIE1

(5)

(5)

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

0000 0000

8Dh

PIE2

CCP2IE

---- ---0

---- ---0

8Eh

PCON

POR

BOR

---- --qq

---- --uu

8Fh

Unimplemented

90h

Unimplemented

91h

Unimplemented

92h

PR2

Timer2 Period Register

1111 1111

1111 1111

93h

SSPADD

Synchronous Serial Port (I

2

C mode) Address Register

0000 0000

0000 0000

94h

SSPSTAT

D/A

P

S

R/W

UA

BF

--00 0000

--00 0000

95h

Unimplemented

96h

Unimplemented

97h

Unimplemented

98h

(2)

TXSTA

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

0000 -010

99h

(2)

SPBRG

Baud Rate Generator Register

0000 0000

0000 0000

9Ah

Unimplemented

9Bh

Unimplemented

9Ch

Unimplemented

9Dh

Unimplemented

9Eh

Unimplemented

9Fh

Unimplemented

TABLE 4-3:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63  (Cont.’d)

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear.

5:

PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.

background image

PIC16C6X

DS30234D-page  28

©

 1997 Microchip Technology Inc.

TABLE 4-4:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64  

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

   

Bank 0

00h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h

(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

03h

(1)

STATUS

IRP

(5)

RP1

(5)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

04h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

PORTA Data Latch when written: PORTA pins when read

--xx xxxx

--uu uuuu

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx

uuuu uuuu

08h

PORTD

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx

uuuu uuuu

09h

PORTE

RE2

RE1

RE0

---- -xxx

---- -uuu

0Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh

(1)

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF

(6)

SSPIF

CCP1IF

TMR2IF

TMR1IF

00-- 0000

00-- 0000

0Dh

Unimplemented

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

10h

T1CON

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

--00 0000

--uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000

0000 0000

12h

T2CON

TOUTPS3 TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

-000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

0000 0000

15h

CCPR1L

Capture/Compare/PWM1 (LSB)

xxxx xxxx

uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM1 (MSB)

xxxx xxxx

uuuu uuuu

17h

CCP1CON

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

--00 0000

18h-1Fh

Unimplemented

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

The BOR  bit is reserved on the PIC16C64, always maintain this bit set.

5:

The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear.

6:

PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  29

PIC16C6X

   Bank 1

80h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

82h

(1)

PCL

Program Counter's (PC)   Least Significant Byte

0000 0000

0000 0000

83h

(1)

STATUS

IRP

(5)

RP1

(5)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

84h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

PORTA Data Direction Register

--11 1111

--11 1111

86h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

87h

TRISC

PORTC Data Direction Register

1111 1111

1111 1111

88h

TRISD

PORTD Data Direction Register

1111 1111

1111 1111

89h

TRISE

IBF

OBF

IBOV

PSPMODE

PORTE Data Direction Bits

0000 -111

0000 -111

8Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

8Bh

(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

8Ch

PIE1

PSPIE

(6)

SSPIE

CCP1IE

TMR2IE

TMR1IE

00-- 0000

00-- 0000

8Dh

Unimplemented

8Eh

PCON

POR

BOR

(4)

---- --qq

---- --uu

8Fh

Unimplemented

90h

Unimplemented

91h

Unimplemented

92h

PR2

Timer2 Period Register

1111 1111

1111 1111

93h

SSPADD

Synchronous Serial Port (I

2

C mode) Address Register

0000 0000

0000 0000

94h

SSPSTAT

D/A

P

S

R/W

UA

BF

--00 0000

--00 0000

95h-9Fh

Unimplemented

TABLE 4-4:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64  (Cont.’d)

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

The BOR  bit is reserved on the PIC16C64, always maintain this bit set.

5:

The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear.

6:

PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear.

background image

PIC16C6X

DS30234D-page  30

©

 1997 Microchip Technology Inc.

TABLE 4-5:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65  

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

   

Bank 0

00h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h

(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

03h

(1)

STATUS

IRP

(5)

RP1

(5)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

04h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

PORTA Data Latch when written: PORTA pins when read

--xx xxxx

--uu uuuu

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx

uuuu uuuu

08h

PORTD

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx

uuuu uuuu

09h

PORTE

RE2

RE1

RE0

---- -xxx

---- -uuu

0Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh

(1)

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF

(6)

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

0000 0000

0Dh

PIR2

—–

CCP2IF

---- ---0

---- ---0

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

10h

T1CON

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

--00 0000

--uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000

0000 0000

12h

T2CON

TOUTPS3 TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

-000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

0000 0000

15h

CCPR1L

Capture/Compare/PWM1 (LSB)

xxxx xxxx

uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM1 (MSB)

xxxx xxxx

uuuu uuuu

17h

CCP1CON

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

--00 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

FERR

OERR

RX9D

0000 -00x

0000 -00x

19h

TXREG

USART Transmit Data Register

0000 0000

0000 0000

1Ah

RCREG

USART Receive Data Register

0000 0000

0000 0000

1Bh

CCPR2L

Capture/Compare/PWM2 (LSB)

xxxx xxxx

uuuu uuuu

1Ch

CCPR2H

Capture/Compare/PWM2 (MSB)

xxxx xxxx

uuuu uuuu

1Dh

CCP2CON

CCP2X

CCP2Y

CCP2M3

CCP2M2

CCP2M1

CCP2M0

--00 0000

--00 0000

1Eh-1Fh

Unimplemented

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

The BOR  bit is reserved on the PIC16C65, always maintain this bit set.

5:

The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear.

6:

PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  31

PIC16C6X

   Bank 1

80h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

82h

(1)

PCL

Program Counter's (PC)   Least Significant Byte

0000 0000

0000 0000

83h

(1)

STATUS

IRP

(5)

RP1

(5)

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

84h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

PORTA Data Direction Register

--11 1111

--11 1111

86h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

87h

TRISC

PORTC Data Direction Register

1111 1111

1111 1111

88h

TRISD

PORTD Data Direction Register

1111 1111

1111 1111

89h

TRISE

IBF

OBF

IBOV

PSPMODE

PORTE Data Direction Bits

0000 -111

0000 -111

8Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

8Bh

(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

8Ch

PIE1

PSPIE

(6)

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

0000 0000

8Dh

PIE2

CCP2IE

---- ---0

---- ---0

8Eh

PCON

POR

BOR

(4)

---- --qq

---- --uu

8Fh

Unimplemented

90h

Unimplemented

91h

Unimplemented

92h

PR2

Timer2 Period Register

1111 1111

1111 1111

93h

SSPADD

Synchronous Serial Port (I

2

C mode) Address Register

0000 0000

0000 0000

94h

SSPSTAT

D/A

P

S

R/W

UA

BF

--00 0000

--00 0000

95h

Unimplemented

96h

Unimplemented

97h

Unimplemented

98h

TXSTA

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000

0000 0000

9Ah

Unimplemented

9Bh

Unimplemented

9Ch

Unimplemented

9Dh

Unimplemented

9Eh

Unimplemented

9Fh

Unimplemented

TABLE 4-5:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65  (Cont.’d)

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

The BOR  bit is reserved on the PIC16C65, always maintain this bit set.

5:

The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear.

6:

PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.

background image

PIC16C6X

DS30234D-page  32

©

 1997 Microchip Technology Inc.

TABLE 4-6:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67  

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

   

Bank 0

00h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h

(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

03h

(1)

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

04h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

PORTA Data Latch when written: PORTA pins when read

--xx xxxx

--uu uuuu

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx

uuuu uuuu

08h

(5)

PORTD

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx

uuuu uuuu

09h

(5)

PORTE

RE2

RE1

RE0

---- -xxx

---- -uuu

0Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

0Bh

(1)

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF

(6)

(4)

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

0000 0000

0Dh

PIR2

—–

CCP2IF

---- ---0

---- ---0

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

10h

T1CON

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

--00 0000

--uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000

0000 0000

12h

T2CON

TOUTPS3 TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

-000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

0000 0000

15h

CCPR1L

Capture/Compare/PWM1 (LSB)

xxxx xxxx

uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM1 (MSB)

xxxx xxxx

uuuu uuuu

17h

CCP1CON

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

--00 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

FERR

OERR

RX9D

0000 -00x

0000 -00x

19h

TXREG

USART Transmit Data Register

0000 0000

0000 0000

1Ah

RCREG

USART Receive Data Register

0000 0000

0000 0000

1Bh

CCPR2L

Capture/Compare/PWM2 (LSB)

xxxx xxxx

uuuu uuuu

1Ch

CCPR2H

Capture/Compare/PWM2 (MSB)

xxxx xxxx

uuuu uuuu

1Dh

CCP2CON

CCP2X

CCP2Y

CCP2M3

CCP2M2

CCP2M1

CCP2M0

--00 0000

--00 0000

1Eh-1Fh

Unimplemented

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from any bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.

5:

PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.

6:

PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  33

PIC16C6X

   Bank 1

80h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

82h

(1)

PCL

Program Counter's (PC)   Least Significant Byte

0000 0000

0000 0000

83h

(1)

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

84h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

PORTA Data Direction Register

--11 1111

--11 1111

86h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

87h

TRISC

PORTC Data Direction Register

1111 1111

1111 1111

88h

(5)

TRISD

PORTD Data Direction Register

1111 1111

1111 1111

89h

(5)

TRISE

IBF

OBF

IBOV

PSPMODE

PORTE Data Direction Bits

0000 -111

0000 -111

8Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

8Bh

(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

8Ch

PIE1

PSPIE

(6)

(4)

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

0000 0000

8Dh

PIE2

CCP2IE

---- ---0

---- ---0

8Eh

PCON

POR

BOR

---- --qq

---- --uu

8Fh

Unimplemented

90h

Unimplemented

91h

Unimplemented

92h

PR2

Timer2 Period Register

1111 1111

1111 1111

93h

SSPADD

Synchronous Serial Port (I

2

C mode) Address Register

0000 0000

0000 0000

94h

SSPSTAT

SMP

CKE

D/A

P

S

R/W

UA

BF

0000 0000

0000 0000

95h

Unimplemented

96h

Unimplemented

97h

Unimplemented

98h

TXSTA

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000

0000 0000

9Ah

Unimplemented

9Bh

Unimplemented

9Ch

Unimplemented

9Dh

Unimplemented

9Eh

Unimplemented

9Fh

Unimplemented

TABLE 4-6:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67  (Cont.’d)

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from any bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.

5:

PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.

6:

PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.

background image

PIC16C6X

DS30234D-page  34

©

 1997 Microchip Technology Inc.

   Bank 2

100h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

101h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

102h

(1)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

103h

(1)

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

104h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

105h

Unimplemented

106h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

107h

Unimplemented

108h

Unimplemented

109h

Unimplemented

10Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

10Bh

(1)

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

10Ch-

10Fh

Unimplemented

   

Bank 3

180h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

0000 0000

181h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

182h

(1)

PCL

Program Counter's (PC)   Least Significant Byte

0000 0000

0000 0000

183h

(1)

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx

000q quuu

184h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

185h

Unimplemented

186h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

187h

Unimplemented

188h

Unimplemented

189h

Unimplemented

18Ah

(1,2)

PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

18Bh

(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

18Ch-

19Fh

Unimplemented

TABLE 4-6:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67  (Cont.’d)

Address  Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(3)

Legend:

x

 = unknown, 

u

 = unchanged, 

q

 = value depends on condition, 

-

 = unimplemented location read as '0'. 

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from any bank.

2:

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose 

contents are transferred to the upper byte of the program counter. (PC<12:8>)

3:

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

4:

PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.

5:

PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.

6:

PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.

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©

 1997 Microchip Technology Inc.

DS30234D-page  35

PIC16C6X

4.2.2.1

STATUS REGISTER

The STATUS register, shown in Figure 4-9, contains the

arithmetic status of the ALU, the RESET status and the

bank select bits for data memory.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended. 

For example, 

CLRF STATUS

 will clear the upper-three

bits and set the Z bit.   This leaves the STATUS register

as 

000u u1uu

 (where 

u

 = unchanged).

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

It is recommended, therefore, that only 

BCF, BSF,

SWAPF

 and 

MOVWF

 instructions are used to alter the

STATUS register because these instructions do not

affect the Z, C or DC bits from the STATUS register. For

other instructions, not affecting any status bits, see the

“Instruction Set Summary.” 

Note 1: For those devices that do not use bits IRP

and RP1 (STATUS<7:6>), maintain these

bits clear to ensure  upward compatibility

with future products.

Note 2: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the 

SUBLW

 and 

SUBWF

instructions for examples.

FIGURE 4-9:

STATUS REGISTER

 

(ADDRESS 03h, 83h, 103h, 183h)

R/W-0

R/W-0

R/W-0

R-1

R-1

R/W-x

R/W-x

R/W-x

IRP

RP1

RP0

TO

PD

Z

DC

C

R  = Readable bit

W = Writable bit

- n = Value at POR reset

x = 

unknown

bit7

bit0

bit 7:

IRP: RegIster Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit  6-5:

RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes.

bit  4:

TO: Time-out bit

1 = After power-up, 

CLRWDT

 instruction, or 

SLEEP

 instruction

0 = A WDT time-out occurred

bit  3:

PD: Power-down bit

1 = After power-up or by the 

CLRWDT

 instruction

0 = By execution of the 

SLEEP

 instruction

bit  2:

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit  1:

DC: Digit carry/borrow bit (for 

ADDWF

ADDLW,SUBLW, 

and

 SUBWF

 instructions) (For borrow the polarity is reversed).

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit  0:

C: Carry/borrow bit (for 

ADDWF

ADDLW,SUBLW, 

and

 SUBWF

 instructions)( For borrow the polarity is reversed).

1 = A carry-out from the most significant bit of the result occurred

0 = No carry-out from the most significant bit of the result

Note: a subtraction is executed by adding the two’s complement of the second operand. 

For rotate (

RRF

RLF

) instructions, this bit is loaded with either the high or low order bit of the source register.

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PIC16C6X

DS30234D-page  36

©

 1997 Microchip Technology Inc.

4.2.2.2

OPTION REGISTER

The OPTION register is a readable and writable regis-

ter which contains various control bits to configure the

TMR0/WDT prescaler, the external INT interrupt,

TMR0, and the weak pull-ups on PORTB.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

To achieve a 1:1 prescaler assignment for

TMR0 register, assign the prescaler to the

Watchdog Timer.

FIGURE 4-10: OPTION REGISTER (ADDRESS 81h, 181h)

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit  6:

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit  5:

T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit  4:

T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit  3:

PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit  2-0:

PS2:PS0: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value

TMR0 Rate

WDT Rate

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©

 1997 Microchip Technology Inc.

DS30234D-page  37

PIC16C6X

4.2.2.3

INTCON REGISTER

The INTCON Register is a readable and writable regis-

ter which contains the various enable and flag bits for

the TMR0 register overflow, RB port change and exter-

nal RB0/INT pin interrupts. 

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

FIGURE 4-11: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh 18Bh) 

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-x

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

x

= unknown

bit7

bit0

bit 7:

GIE:

(1)

 Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit  6:

PEIE:

(2)

 Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit  5:

T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit  4:

INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit  3:

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit  2:

T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit  1:

INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit  0:

RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (see Section 5.2 to clear the interrupt)

0 = None of the RB7:RB4 pins have changed state

Note 1:

For the PIC16C61/62/64/65, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may unintentionally 

be re-enabled by the 

RETFIE

 instruction in the user’s Interrupt Service Routine. Refer to Section 13.5 for a detailed 

description.

2:

The PEIE bit (bit6) is unimplemented on the PIC16C61, read as '0'.

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the 

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to 

enabling an interrupt.

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PIC16C6X

DS30234D-page  38

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 1997 Microchip Technology Inc.

4.2.2.4

PIE1 REGISTER

This register contains the individual enable bits for the

peripheral interrupts.

 

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch)

RW-0

R/W-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

SSPIE

CCP1IE

TMR2IE

TMR1IE

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7-6:

Reserved: Always maintain these bits clear.

bit 5-4:

Unimplemented: Read as '0'

bit  3:

SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit  2:

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit  1:

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit  0:

TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

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DS30234D-page  39

PIC16C6X

FIGURE 4-13: PIE1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 8Ch)

FIGURE 4-14: PIE1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 8Ch)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit  7-6:

Reserved: Always maintain these bits clear.

bit  5:

RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit 4:

TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit  3:

SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit  2:

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit  1:

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit  0:

TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

R/W-0

R/W-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

PSPIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit 6:

Reserved: Always maintain this bit clear.

bit 5-4:

Unimplemented: Read as '0'

bit  3:

SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit  2:

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit  1:

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit  0:

TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

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PIC16C6X

DS30234D-page  40

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FIGURE 4-15: PIE1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 8Ch)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

PSPIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit  6:

Reserved: Always maintain this bit clear.

bit  5:

RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit 4:

TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit  3:

SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit  2:

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit  1:

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit  0:

TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

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©

 1997 Microchip Technology Inc.

DS30234D-page  41

PIC16C6X

4.2.2.5

PIR1 REGISTER

This register contains the individual flag bits for the

peripheral interrupts.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

FIGURE 4-16: PIR1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 0Ch)

R/W-0

R/W-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

SSPIF

CCP1IF

TMR2IF

TMR1IF

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit  7-6:

Reserved: Always maintain these bits clear.

bit  5-4:

Unimplemented: Read as '0'

bit  3:

SSPIF: Synchronous Serial Port Interrupt Flag bit 

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit  2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit  1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit  0:

TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register overflow occurred

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the 

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to 

enabling an interrupt.

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PIC16C6X

DS30234D-page  42

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 1997 Microchip Technology Inc.

FIGURE 4-17: PIR1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 0Ch)

R/W-0

R/W-0

R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit  7-6:

Reserved: Always maintain these bits clear.

bit  5:

RCIF: USART Receive Interrupt Flag bit 

1 = The USART receive buffer is full (cleared by reading RCREG)

0 = The USART receive buffer is empty

bit 4:

TXIF: USART Transmit Interrupt Flag bit 

1 = The USART transmit buffer is empty (cleared by writing to TXREG)

0 = The USART transmit buffer is full

bit  3:

SSPIF: Synchronous Serial Port Interrupt Flag bit 

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit  2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit  1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit  0:

TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register overflow occurred

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the 

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to 

enabling an interrupt.

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DS30234D-page  43

PIC16C6X

FIGURE 4-18: PIR1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 0Ch)

R/W-0

R/W-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

PSPIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

PSPIF: Parallel Slave Port Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place

bit  6:

Reserved: Always maintain this bit clear.

bit 5-4:

Unimplemented: Read as '0'

bit  3:

SSPIF: Synchronous Serial Port Interrupt Flag bit 

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit  2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit  1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit  0:

TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register occurred

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the 

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to 

enabling an interrupt.

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PIC16C6X

DS30234D-page  44

©

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FIGURE 4-19: PIR1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 0Ch)

R/W-0

R/W-0

R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

PSPIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

PSPIF: Parallel Slave Port Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place

bit  6:

Reserved: Always maintain this bit clear.

bit  5:

RCIF: USART Receive Interrupt Flag bit 

1 = The USART receive buffer is full (cleared by reading RCREG)

0 = The USART receive buffer is empty

bit 4:

TXIF: USART Transmit Interrupt Flag bit 

1 = The USART transmit buffer is empty  (cleared by writing to TXREG)

0 = The USART transmit buffer is full

bit  3:

SSPIF: Synchronous Serial Port Interrupt Flag bit 

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit  2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit  1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit  0:

TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register overflow occurred

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the 

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to 

enabling an interrupt.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  45

PIC16C6X

4.2.2.6

PIE2 REGISTER

This register contains the CCP2 interrupt enable bit.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 4-20: PIE2 REGISTER (ADDRESS 8Dh)

U-0

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

CCP2IE

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7-1:

Unimplemented: Read as '0'

bit  0:

CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

background image

PIC16C6X

DS30234D-page  46

©

 1997 Microchip Technology Inc.

4.2.2.7

PIR2 REGISTER

This register contains the CCP2 interrupt flag bit. 

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

.

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

FIGURE 4-21: PIR2 REGISTER (ADDRESS 0Dh)

U-0

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

CCP2IF

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7-1:

Unimplemented: Read as '0'

bit  0:

CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the 

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to 

enabling an interrupt.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  47

PIC16C6X

4.2.2.8

PCON REGISTER

The Power Control register (PCON) contains a flag bit

to allow differentiation between a Power-on Reset to an

external MCLR reset or WDT reset. Those devices with

brown-out detection circuitry contain an additional bit to

differentiate a Brown-out Reset condition from a

Power-on Reset condition.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent resets to see if BOR is

clear, indicating a brown-out has occurred.

The BOR status bit is a “don't care” and is

not necessarily predictable if the brown-out

circuit is disabled (by clearing the BODEN

bit in the Configuration word).

FIGURE 4-22:  PCON REGISTER FOR PIC16C62/64/65 (ADDRESS 8Eh)

FIGURE 4-23: PCON REGISTER FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67 

(ADDRESS 8Eh)

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

R/W-q

POR

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

q

= value depends on conditions

bit7

bit0

bit 7-2:

Unimplemented: Read as '0'

bit  1:

POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit  0:

Reserved

This bit should be set upon a Power-on Reset by user software and maintained as set. Use of this bit as a general

purpose read/write bit is not recommended, since this may affect upward compatibility with future products.

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

R/W-q

POR

BOR

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

q

= value depends on conditions

bit7

bit0

bit 7-2:

Unimplemented: Read as '0'

bit  1:

POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit  0:

BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

background image

PIC16C6X

DS30234D-page  48

©

 1997 Microchip Technology Inc.

4.3

PCL and PCLATH

 

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The upper bits (PC<12:8>) are not

readable, but are indirectly writable through the

PCLATH register. On any reset, the upper bits of the PC

will be cleared. Figure 4-24 shows the two situations for

the loading of the PC. The upper example in the figure

shows how the PC is loaded on a write to PCL

(PCLATH<4:0> 

 PCH). The lower example in the fig-

ure shows how the PC is loaded during a 

CALL

 or 

GOTO

instruction (PCLATH<4:3> 

 PCH).

FIGURE 4-24: LOADING OF PC IN 

DIFFERENT SITUATIONS

4.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (

ADDWF PCL

). When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256 word block). Refer to the

application note 

“Implementing a Table Read” (AN556).

4.3.2

STACK

The PIC16CXX family has an 8 deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writable. The PC is PUSHed onto the stack

when a 

CALL

 instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN, RETLW

 or a 

RETFIE

 instruction execution.

PCLATH is not affected by a PUSH or a POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PC

12

8

7

0

5

PCLATH<4:0>

PCLATH

Instruction with

PCL as

ALU

GOTO, CALL

Opcode <10:0>

8

PC

12

11 10

0

11

PCLATH<4:3>

PCH

PCL

8

7

2

PCLATH

PCH

PCL

 destination

4.4

Program Memory Paging

PIC16C6X devices are capable of addressing a contin-

uous 8K word block of program memory. The 

CALL

 and

GOTO

 instructions provide only 11 bits of address to

allow branching within any 2K program memory page.

When doing a 

CALL

 or 

GOTO

 instruction the upper two

bits of the address are provided by PCLATH<4:3>.

When doing a 

CALL

 or 

GOTO

 instruction, the user must

ensure that the page select bits are programmed so

that the desired program memory page is addressed. If

a return from a 

CALL

 instruction (or interrupt) is exe-

cuted, the entire 13-bit PC is pushed onto the stack.

Therefore, manipulation of the PCLATH<4:3> bits are

not required for the return instructions (which POPs the

address from the stack).

Note 1: There are no status bits to indicate stack

overflows or stack underflow conditions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the 

CALL,

RETURN, RETLW,

 and 

RETFIE

 instruc-

tions, or the vectoring to an interrupt

address

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

PIC16C6X devices with 4K or less of pro-

gram memory ignore paging bit

PCLATH<4>. The use of  PCLATH<4> as a

general purpose read/write bit is not rec-

ommended since this may affect upward

compatibility with future products.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  49

PIC16C6X

Example 4-1 shows the calling of a subroutine in

page 1 of the program memory. This example assumes

that the PCLATH is saved and restored by the interrupt

service routine (if interrupts are used).

EXAMPLE 4-1:

CALL OF A SUBROUTINE IN 

PAGE 1 FROM PAGE 0 

ORG 0x500

BSF    PCLATH,3  ;Select page 1 (800h-FFFh)

BCF    PCLATH,4  ;Only on >4K devices

CALL   SUB1_P1   ;Call subroutine in

       :         ;page 1 (800h-FFFh)

       :         

       :

ORG 0x900

SUB1_P1:         ;called subroutine

       :         ;page 1 (800h-FFFh)

       :

RETURN           ;return to Call subroutine

                 ;in page 0 (000h-7FFh)

4.5

Indirect Addressing, INDF and FSR 

Registers

The INDF register is not a physical register.  Address-

ing the INDF register will cause indirect addressing.  

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses the register pointed to by the File Select Reg-

ister, FSR. Reading the INDF register itself indirectly

(FSR = '0') will produce 00h. Writing to the INDF regis-

ter indirectly results in a no-operation (although status

bits may be affected). An effective 9-bit address is

obtained by concatenating the 8-bit FSR register and

the IRP bit (STATUS<7>), as shown in Figure 4-25. 

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 4-2.

EXAMPLE 4-2:

INDIRECT ADDRESSING

          movlw  0x20    ;initialize pointer

          movwf  FSR     ;  to RAM

NEXT      clrf   INDF    ;clear INDF register

          incf   FSR,F   ;inc pointer

          btfss  FSR,4   ;all done?

          goto   NEXT    ;NO, clear next

CONTINUE

          :              ;YES, continue

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 4-25: DIRECT/INDIRECT ADDRESSING

For memory map detail see Figure 4-5, Figure 4-6,  Figure 4-7, and Figure 4-8.

bank select

bank select

location select

location select

Direct Addressing

Indirect Addressing

RP1: RP0

6

0

from opcode

IRP

7

FSR

0

00

01

10

11

Bank 0

Bank 1

Bank 2

Bank 3

FFh

80h

Data 

Memory

7Fh

00h

17Fh

100h

1FFh

180h

background image

PIC16C6X

DS30234D-page  50

©

 1997 Microchip Technology Inc.

NOTES:

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©

 1997 Microchip Technology Inc.

DS30234D-page  51

PIC16C6X

5.0

I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function(s) for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

5.1

PORTA and TRISA Register

All devices have a 6-bit wide PORTA, except for the

PIC16C61 which has a 5-bit wide PORTA. 

Pin RA4/T0CKI is a Schmitt Trigger input and an open

drain output. All other RA port pins have TTL input lev-

els and full CMOS output drivers. All pins have data

direction bits (TRIS registers) which can configure

these pins as output or input. 

Setting a bit in the TRISA register puts the correspond-

ing output driver in a hi-impedance mode. Clearing a bit

in the TRISA register puts the contents of the output

latch on the selected pin.

Reading PORTA register reads the status of the pins

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. There-

fore, a write to a port implies that the port pins are read,

this value is modified, and then written to the port data

latch.

Pin RA4 is multiplexed with Timer0 module clock input

to become the RA4/T0CKI pin. 

EXAMPLE 5-1:

INITIALIZING PORTA

BCF    STATUS, RP0  ;

BCF    STATUS, RP1  ; PIC16C66/67 only

CLRF   PORTA        ; Initialize PORTA by

                    ; clearing output

                    ; data latches

BSF    STATUS, RP0  ; Select Bank 1

MOVLW  0xCF         ; Value used to 

                    ; initialize data 

                    ; direction

MOVWF  TRISA        ; Set RA<3:0> as inputs

                    ; RA<5:4> as outputs

                    ; TRISA<7:6> are always

                    ; read as '0'.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 5-1:

BLOCK DIAGRAM OF THE

RA3:RA0 PINS AND THE RA5 

PIN 

FIGURE 5-2:

BLOCK DIAGRAM OF THE 

RA4/T0CKI PIN

Data

bus

Q

D

Q

CK

Q

D

Q

CK

Q

D

EN

P

N

WR

Port

WR

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

TTL

input

buffer

V

SS

V

DD

I/O pin

(1)

Note 1:

I/O pins have protection diodes to V

DD

 and 

V

SS

.

2:

The PIC16C61 does not have an RA5 pin.

Data

bus

WR

PORT

WR

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

input

buffer

N

V

SS

I/O pin

(1)

TMR0 clock input

Note 1: I/O pin has protection diodes to V

SS

 only.

Q

D

Q

CK

Q

D

Q

CK

EN

Q

D

EN

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PIC16C6X

DS30234D-page  52

©

 1997 Microchip Technology Inc.

TABLE 5-1:

PORTA FUNCTIONS

TABLE 5-2:

REGISTERS/BITS ASSOCIATED WITH PORTA

Name

Bit#

Buffer Type

Function

RA0

bit0

TTL

Input/output

RA1

bit1

TTL

Input/output

RA2

bit2

TTL

Input/output

RA3

bit3

TTL

Input/output

RA4/T0CKI

bit4

ST

Input/output or external clock input for Timer0.

Output is open drain type.

RA5/SS 

(1)

bit5

TTL

Input/output or slave select input for synchronous serial port.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: The PIC16C61 does not have PORTA<5> or TRISA<5>, read as ‘0’.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on all 

other resets

05h

PORTA

RA5

(1)

RA4

RA3

RA2

RA1

RA0

--xx xxxx

--uu uuuu

85h

TRISA

PORTA Data Direction Register

(1)

--11 1111

--11 1111

Legend:

x

 = unknown, 

u

 = unchanged, 

-

 = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

Note 1:

PORTA<5> and TRISA<5> are not implemented on the PIC16C61, read as '0'.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  53

PIC16C6X

5.2

PORTB and TRISB Register

PORTB is an 8-bit wide bi-directional port. The corre-

sponding data direction register is TRISB. Setting a bit

in the TRISB register puts the corresponding output

driver in a hi-impedance mode. Clearing a bit in the

TRISB register puts the contents of the output latch on

the selected pin(s).

EXAMPLE 5-2:

INITIALIZING PORTB

BCF    STATUS, RP0  ;

CLRF   PORTB        ; Initialize PORTB by

                    ; clearing output

                    ; data latches

BSF    STATUS, RP0  ; Select Bank 1

MOVLW  0xCF         ; Value used to 

                    ; initialize data 

                    ; direction

MOVWF  TRISB        ; Set RB<3:0> as inputs

                    ; RB<5:4> as outputs

                    ; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit RBPU (OPTION<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are also

disabled on a Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RB port change

interrupt with flag bit RBIF (INTCON<0>).

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the inter-

rupt in the following manner:

a)

Any read or write of PORTB. This will end the

mismatch condition.

b)

Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with soft-

ware configurable pull-ups on these four pins allow

easy interface to a keypad and make it possible for

wake-up on key-depression. Refer to the Embedded

Control Handbook, Application Note,

 “Implementing

Wake-up on Key Stroke” (AN552).

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-3:

BLOCK DIAGRAM OF THE

RB7:RB4 PINS FOR 

PIC16C61/62/64/65  

Note:

For PIC16C61/62/64/65, if a change on the

I/O pin should occur when a read operation

is being executed (start of the Q2 cycle),

then interrupt flag bit RBIF may not get set.

Data Latch

From other

RBPU

(2)

P

V

DD

I/O

Q

D

CK

Q

D

CK

Q

D

EN

Q

D

EN

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

pin

(1)

Note 1: I/O pins have diode protection to V

DD

 and V

SS

.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RPBU bit (OPTION<7>).

ST

Buffer

RB7:RB6 in serial programming mode

background image

PIC16C6X

DS30234D-page  54

©

 1997 Microchip Technology Inc.

FIGURE 5-4:

BLOCK DIAGRAM OF THE

RB7:RB4 PINS FOR 

PIC16C62A/63/R63/64A/65A/

R65/66/67 

Data Latch

From other

RBPU

(2)

P

V

DD

I/O

Q

D

CK

Q

D

CK

Q

D

EN

Q

D

EN

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

pin

(1)

Note 1: I/O pins have diode protection to V

DD

 and V

SS

.

ST

Buffer

RB7:RB6 in serial programming mode

Q3

Q1

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RPBU bit (OPTION<7>).

FIGURE 5-5:

BLOCK DIAGRAM OF THE

RB3:RB0 PINS 

Data Latch

RBPU

(2)

P

V

DD

Q

D

CK

Q

D

CK

Q

D

EN

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak

pull-up

RD Port

RB0/INT

I/O

pin

(1)

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

Note 1: I/O pins have diode protection to V

DD

 and V

SS

.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RPBU bit (OPTION<7>).

TABLE 5-3:

PORTB FUNCTIONS 

TABLE 5-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name

Bit#

Buffer Type

Function

RB0/INT

bit0

TTL/ST

(1)

Input/output pin or external interrupt input. Internal software programmable 

weak pull-up.

RB1

bit1

TTL

Input/output pin.  Internal software programmable weak pull-up.

RB2

bit2

TTL

Input/output pin.  Internal software programmable weak pull-up.

RB3

bit3

TTL

Input/output pin.  Internal software programmable weak pull-up.

RB4

bit4

TTL

Input/output pin (with interrupt on change). Internal software programmable 

weak pull-up.

RB5

bit5

TTL

Input/output pin (with interrupt on change). Internal software programmable 

weak pull-up.

RB6

bit6

TTL/ST

(2)

 

Input/output pin (with interrupt on change). Internal software programmable 

weak pull-up. Serial programming clock.

RB7

bit7

TTL/ST

(2)

 

Input/output pin (with interrupt on change). Internal software programmable 

weak pull-up. Serial programming data.

Legend:  TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on all 

other resets

06h, 106h PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuuu

86h, 186h TRISB

PORTB Data Direction Register

1111 1111

1111 1111

81h, 181h OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

Legend:

x

 = unknown, 

u

 = unchanged. Shaded cells are not used by PORTB.

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©

 1997 Microchip Technology Inc.

DS30234D-page  55

PIC16C6X

5.3

PORTC and TRISC Register

PORTC is an 8-bit wide bi-directional port. Each pin is

individually configurable as an input or output through

the TRISC register. PORTC is multiplexed with several

peripheral functions (Table 5-5). PORTC pins have

Schmitt Trigger input buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to

make a pin an input. Since the TRIS bit override is in

effect while the peripheral is enabled, read-modify-

write instructions (

BSF, BCF, XORWF

) with TRISC as

destination should be avoided. The user should refer to

the corresponding peripheral section for the correct

TRIS bit settings.

EXAMPLE 5-3:

INITIALIZING PORTC

BCF    STATUS, RP0  ;

BCF    STATUS, RP1  ; PIC16C66/67 only

CLRF   PORTC        ; Initialize PORTC by

                    ; clearing output

                    ; data latches

BSF    STATUS, RP0  ; Select Bank 1

MOVLW  0xCF         ; Value used to 

                    ; initialize data 

                    ; direction

MOVWF  TRISC        ; Set RC<3:0> as inputs

                    ; RC<5:4> as outputs

                    ; RC<7:6> as inputs

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 5-6:

PORTC BLOCK DIAGRAM 

PORT/PERIPHERAL Select

(2)

Data bus

WR

PORT

WR

TRIS

RD 

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Q

D

Q

CK

Q

D

EN

Peripheral Data Out

0

1

Q

D

Q

CK

P

N

V

DD

V

SS

PORT

Peripheral

OE

(3)

Peripheral input

I/O

pin

(1)

Note 1:

I/O pins have diode protection to V

DD

 and V

SS

.

2:

Port/Peripheral select signal selects between port 

data and peripheral output.

3:

Peripheral OE (output enable) is only activated if 

peripheral select is active.

TABLE 5-5:

PORTC FUNCTIONS FOR PIC16C62/64

Name

Bit# Buffer Type Function

RC0/T1OSI/T1CKI

bit0

ST

Input/output port pin or Timer1 oscillator input or Timer1 clock input

RC1/T1OSO

bit1

ST

Input/output port pin or Timer1 oscillator output

RC2/CCP1

bit2

ST

Input/output port pin or Capture1 input/Compare1 output/PWM1 output

RC3/SCK/SCL

bit3

ST

RC3 can also be the synchronous serial clock for both SPI and I

2

C modes.

RC4/SDI/SDA

bit4

ST

RC4 can also be the SPI Data In (SPI mode) or data I/O (I

2

C mode).

RC5/SDO

bit5

ST

Input/output port pin or synchronous serial port data output

RC6

bit6

ST

Input/output port pin

RC7

bit7

ST

Input/output port pin

Legend: ST = Schmitt Trigger input

background image

PIC16C6X

DS30234D-page  56

©

 1997 Microchip Technology Inc.

TABLE 5-6:

PORTC FUNCTIONS FOR PIC16C62A/R62/64A/R64

TABLE 5-7:

PORTC FUNCTIONS FOR PIC16C63/R63/65/65A/R65/66/67

TABLE 5-8:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name

Bit# Buffer Type Function

RC0/T1OSO/T1CKI

bit0

ST

Input/output port pin or Timer1 oscillator output or Timer1 clock input

RC1/T1OSI

bit1

ST

Input/output port pin or Timer1 oscillator input

RC2/CCP1

bit2

ST

Input/output port pin or Capture input/Compare output/PWM1 output

RC3/SCK/SCL

bit3

ST

RC3 can also be the synchronous serial clock for both SPI and I

2

C modes.

RC4/SDI/SDA

bit4

ST

RC4 can also be the SPI Data In (SPI mode) or data I/O (I

2

C mode).

RC5/SDO

bit5

ST

Input/output port pin or synchronous serial port data output

RC6

bit6

ST

Input/output port pin

RC7

bit7

ST

Input/output port pin

Legend: ST = Schmitt Trigger input

Name

Bit# Buffer Type Function

RC0/T1OSO/T1CKI

bit0

ST

Input/output port pin or Timer1 oscillator output or Timer1 clock input

RC1/T1OSI/CCP2

bit1

ST

Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2 

output/PWM2 output

RC2/CCP1

bit2

ST

Input/output port pin or Capture1 input/Compare1 output/PWM1 output

RC3/SCK/SCL

bit3

ST

RC3 can also be the synchronous serial clock for both SPI and I

2

C modes.

RC4/SDI/SDA

bit4

ST

RC4 can also be the SPI Data In (SPI mode) or data I/O (I

2

C mode).

RC5/SDO

bit5

ST

Input/output port pin or synchronous serial port data output

RC6/TX/CK

bit6

ST

Input/output port pin or USART Asynchronous Transmit, or USART Syn-

chronous Clock

RC7/RX/DT

bit7

ST

Input/output port pin or USART Asynchronous Receive, or USART Syn-

chronous Data

Legend: ST = Schmitt Trigger input

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: 

POR,

BOR

Value on all 

other resets

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx

uuuu uuuu

87h

TRISC

PORTC Data Direction Register

1111 1111

1111 1111

Legend:

x

 = unknown, 

u

 = unchanged.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  57

PIC16C6X

5.4

PORTD and TRISD Register

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as input or out-

put.

PORTD can be configured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mode, the input buffers

are TTL. 

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 5-7:

PORTD BLOCK DIAGRAM

(IN I/O PORT MODE)

Data

bus

WR

PORT

WR

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

input

buffer

I/O pin

(1)

Note 1: I/O pins have protection diodes to V

DD

 and V

SS

.

Q

D

CK

Q

D

CK

EN

Q

D

EN

TABLE 5-9:

PORTD FUNCTIONS

TABLE 5-10:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name

Bit#

Buffer Type

Function

RD0/PSP0

bit0

ST/TTL

(1)

Input/output port pin or parallel slave port bit0

RD1/PSP1

bit1

ST/TTL

(1)

Input/output port pin or parallel slave port bit1

RD2/PSP2

bit2

ST/TTL

(1)

Input/output port pin or parallel slave port bit2

RD3/PSP3

bit3

ST/TTL

(1)

Input/output port pin or parallel slave port bit3

RD4/PSP4

bit4

ST/TTL

(1)

Input/output port pin or parallel slave port bit4

RD5/PSP5

bit5

ST/TTL

(1)

Input/output port pin or parallel slave port bit5

RD6/PSP6

bit6

ST/TTL

(1)

Input/output port pin or parallel slave port bit6

RD7/PSP7

bit7

ST/TTL

(1)

Input/output port pin or parallel slave port bit7

Legend:  ST = Schmitt Trigger input, TTL = TTL input 

Note 1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port mode.

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: 

POR,

BOR

Value on all 

other resets

08h

PORTD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx

uuuu uuuu

88h

TRISD

PORTD Data Direction Register

1111 1111

1111 1111

89h

TRISE

IBF

OBF

IBOV

PSPMODE

PORTE Data Direction Bits

0000 -111

0000 -111

Legend:

x

 = unknown, 

u

 = unchanged, 

-

 = unimplemented locations read as '0'. Shaded cells are not used by PORTD.

background image

PIC16C6X

DS30234D-page  58

©

 1997 Microchip Technology Inc.

5.5

PORTE and TRISE Register

PORTE has three pins, RE2/CS, RE1/WR, and

RE0/RD which are individually configurable as inputs

or outputs. These pins have Schmitt Trigger input buff-

ers.

I/O PORTE becomes control inputs for the micropro-

cessor port when bit PSPMODE (TRISE<4>) is set. In

this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are configured as digital

inputs). In this mode the input buffers are TTL.

Figure 5-9 shows the TRISE register, which controls

the parallel slave port operation and also controls the

direction of the PORTE pins.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 5-8:

PORTE BLOCK DIAGRAM

 (IN I/O PORT MODE)

Data

bus

WR

PORT

WR

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

input

buffer

Q

D

CK

Q

D

CK

EN

Q

D

EN

I/O pin

(1)

Note 1: I/O pins have protection diodes to V

DD

 and V

SS

.

FIGURE 5-9:

TRISE REGISTER (ADDRESS 89h)

R-0

R-0

R/W-0

R/W-0

U-0

R/W-1

R/W-1

R/W-1

IBF

OBF

IBOV

PSPMODE

bit2

bit1

bit0

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7 :

IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU

0 = No word has been received

bit  6:

OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

bit  5:

IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software)

0 = No overflow occurred

bit  4:

PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel slave port mode

0 = General purpose I/O mode

bit  3:

Unimplemented: Read as '0'

PORTE Data Direction Bits

bit  2:

Bit2: Direction Control bit for pin RE2/CS

1 = Input

0 = Output

bit  1:

Bit1: Direction Control bit for pin RE1/WR

1 = Input

0 = Output

bit  0:

Bit0: Direction Control bit for pin RE0/RD

1 = Input

0 = Output

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  59

PIC16C6X

TABLE 5-11:

PORTE FUNCTIONS

TABLE 5-12:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name

Bit#

Buffer Type

Function

RE0/RD

bit0

ST/TTL

(1)

Input/output port pin or Read control input in parallel slave port mode.

RD

1 = Not a read operation

0 =  Read operation. The system reads the PORTD register (if 

chip selected)

RE1/WR

bit1

ST/TTL

(1)

Input/output port pin or Write control input in parallel slave port mode.

WR

1 =  Not a write operation

0 = Write operation. The system writes to the PORTD register (if 

chip selected)

RE2/CS

bit2

ST/TTL

(1)

Input/output port pin or Chip select control input in parallel slave port 

mode.

CS

1 = Device is not selected

0 = Device is selected

Legend:  ST = Schmitt Trigger input, TTL = TTL input 

Note 1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port (PSP) mode.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: 

POR,

BOR

Value on all 

other resets

09h

PORTE

RE2

RE1

RE0

---- -xxx

---- -uuu

89h

TRISE

IBF

OBF

IBOV

PSPMODE

PORTE Data Direction Bits

0000 -111

0000 -111

Legend:

x

 = unknown, 

u

 = unchanged, 

-

 = unimplemented locations read as '0'. Shaded cells not used by PORTE.

background image

PIC16C6X

DS30234D-page  60

©

 1997 Microchip Technology Inc.

5.6

I/O Programming Considerations

5.6.1

BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read followed by a write operation. The 

BCF

 and 

BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result back

to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs defined. For example, a 

BSF

 operation on bit5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the 

BSF

 operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi-directional I/O pin

(e.g., bit0) and it is defined as an input at this time, the

input signal present on the pin itself would be read into

the CPU and rewritten to the data latch of this particular

pin, overwriting the previous content. As long as the pin

stays in the input mode, no problem occurs. However, if

bit0 is switched into output mode later on, the content

of the data latch may now be unknown.

Reading the port register, reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(ex. 

BCF, BSF

, etc.) on a port, the value of the port pins

is read, the desired operation is done to this value, and

this value is then written to the port latch. 

Example 

5-4 shows the effect of two sequential

read-modify-write instructions on an I/O port.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

EXAMPLE 5-4:

READ-MODIFY-WRITE 

INSTRUCTIONS ON AN 

I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs

;                       PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

;                    PORT latch  PORT pins

;                    ----------  ---------

  BCF PORTB, 7     ; 01pp pppp   11pp pppp

  BCF PORTB, 6     ; 10pp pppp   11pp pppp

  BSF STATUS, RP0  ; 

  BCF TRISB, 7     ; 10pp pppp   11pp pppp

  BCF TRISB, 6     ; 10pp pppp   10pp pppp

;

;Note that the user may have expected the 

;pin values to be 00pp pppp. The 2nd BCF

;caused RB7 to be latched as the pin value

;(high).

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage the

chip.

5.6.2

SUCCESSIVE  OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle

(Figure 5-10). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load depen-

dent) before the next instruction which causes that file

to be read into the CPU is executed. Otherwise, the

previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with a 

NOP

 or another

instruction not accessing this I/O port.

FIGURE 5-10: SUCCESSIVE I/O OPERATION

PC

PC + 1

PC + 2

PC + 3

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to

PORTB

NOP

Port pin

sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

write to

PORTB

NOP

MOVF PORTB,W

PC

T

PD

Note:

This example shows a write to PORTB

followed by a read from PORTB.

Note that:

data setup time = (0.25T

CY

 - T

PD

)

where T

CY

 = instruction cycle

T

PD

 = propagation delay

Therefore, at higher clock frequencies,

a write followed by a read may be prob-

lematic.

background image

©

 1997 Microchip Technology Inc.

DS30234D-page  61

PIC16C6X

5.7

Parallel Slave Port

PORTD operates as an 8-bit wide parallel slave port

(microprocessor port) when control bit PSPMODE

(TRISE<4>) is set. In slave mode it is asynchronously

readable and writable by the external world through

RD control input (RE0/RD) and WR control input pin

(RE1/WR).

It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the

PORTD latch as an 8-bit latch. Setting PSPMODE

enables port pin RE0/RD to be the RD input, RE1/WR

to be the WR input and RE2/CS to be the CS (chip

select) input. For this functionality, the corresponding

data direction bits of the TRISE register (TRISE<2:0>)

must be configured as inputs (set). 

There are actually two 8-bit latches, one for data-out

(from the PIC16/17) and one for data input. The user

writes 8-bit data to PORTD data latch and reads data

from the port pin latch (note that they have the same

address). In this mode, the TRISD register is ignored

since the microprocessor is controlling the direction of

data flow.

A write to the PSP occurs when both the CS and WR

lines are first detected low. When either the CS or WR

lines become high (level triggered), then the Input

Buffer Full status flag bit IBF (TRISE<7>) is set on the

Q4 clock cycle, following the next Q2 cycle, to signal

the write is complete (Figure 5-12). The interrupt flag bit

PSPIF (PIR1<7>) is also set on the same Q4 clock

cycle. IBF can only be cleared by reading the PORTD

input latch. The input Buffer Overflow status flag bit

IBOV (TRISE<5>) is set if a second write to the Parallel

Slave Port is attempted when the previous byte has not

been read out of the buffer.

A read from the PSP occurs when both the CS and RD

lines are first detected low. The Output Buffer Full sta-

tus flag bit OBF (TRISE<6>) is cleared immediately

(Figure 5-13) indicating that the PORTD latch is waiting

to be read by the external bus. When either the CS or

RD pin becomes high (level triggered), the interrupt flag

bit PSPIF is set on the Q4 clock cycle, following the

next Q2 cycle, indicating that the read is complete.

OBF remains low until data is written to PORTD by the

user firmware.

When not in Parallel Slave Port mode, the IBF and OBF

bits are held clear. However, if flag bit IBOV was previ-

ously set, it must be cleared in firmware.

An interrupt is generated and latched into flag bit

PSPIF when a read or write operation is completed.

PSPIF must be cleared by the user in firmware and the

interrupt can be disabled by clearing the interrupt

enable bit PSPIE (PIE1<7>).

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 5-11: PORTD AND PORTE AS A 

PARALLEL SLAVE PORT

Data bus

WR

PORT

RD

RDx

Q

D

CK

EN

Q

D

EN

PORT

pin

One bit of PORTD

Set interrupt flag

PSPIF (PIR1<7>)