background image

 

SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

Typical V

OLP

 (Output Ground Bounce)

< 0.8 V at V

CC

 = 3.3 V, T

A

 = 25

°

C

D

Typical V

OHV

 (Output V

OH

 Undershoot)

> 2 V at V

CC

 = 3.3 V, T

A

 = 25

°

C

D

Supports Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

CC

)

D

Power Off Disables Inputs/Outputs,

Permitting Live Insertion

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

description

This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V V

CC

 operation.

The SN74LVCH16245A is designed for asynchronous communication between data buses. The

control-function implementation minimizes external timing requirements.

This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the

A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)

input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE should be tied to V

CC

 through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74LVCH16245A is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

DGG OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1DIR

1B1

1B2

GND

1B3

1B4

V

CC

1B5

1B6

GND

1B7

1B8

2B1

2B2

GND

2B3

2B4

V

CC

2B5

2B6

GND

2B7

2B8

2DIR

1OE

1A1

1A2

GND

1A3

1A4

V

CC

1A5

1A6

GND

1A7

1A8

2A1

2A2

GND

2A3

2A4

V

CC

2A5

2A6

GND

2A7

2A8

2OE

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SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

(each 8-bit section)

INPUTS

OPERATION

OE

DIR

OPERATION

L

L

B data to A bus

L

H

A data to B bus

H

X

Isolation

logic symbol

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

1OE

2OE

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1A1

47

G3

48

3 EN1 [BA]

1

1DIR

3 EN2 [AB]

G6

25

6 EN4 [BA]

24

2DIR

6 EN5 [AB]

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2A1

36

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1

4

2

5

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SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

To Seven Other Channels

1DIR

1A1

1B1

1OE

To Seven Other Channels

2DIR

2A1

2B1

2OE

1

47

24

36

48

2

25

13

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

: (see Note 1) 

–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1) 

–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high or low state, V

O

(see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through each V

CC

 or GND 

±

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 3): DGG package 

89

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

94

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51.

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SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

Operating

1.65

3.6

V

VCC

Supply voltage

Data retention only

1.5

V

VCC = 1.65 V to 1.95 V

0.65 

×

VCC

VIH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V

VCC = 2.7 V to 3.6 V

2

VCC = 1.65 V to 1.95 V

0.35 

×

VCC

VIL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V

VCC = 2.7 V to 3.6 V

0.8

VI

Input voltage

0

5.5

V

VO

Output voltage

High or low state

0

VCC

V

VO

Output voltage

3 state

0

5.5

V

VCC = 1.65 V

–4

IOH

High level output current

VCC = 2.3 V

–8

mA

IOH

High-level output current

VCC = 2.7 V

–12

mA

VCC = 3 V

–24

VCC = 1.65 V

4

IOL

Low level output current

VCC = 2.3 V

8

mA

IOL

Low-level output current

VCC = 2.7 V

12

mA

VCC = 3 V

24

t/

v

Input transition rise or fall rate

0

5

ns/V

TA

Operating free-air temperature

–40

85

°

C

NOTE  4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

IOH = –100 

µ

A

1.65 V to 3.6 V

VCC–0.2

IOH = –4 mA

1.65 V

1.2

VOH

IOH = –8 mA

2.3 V

1.7

V

VOH

IOH = 12 mA

2.7 V

2.2

V

IOH = –12 mA

3 V

2.4

IOH = –24 mA

3 V

2.2

IOL = 100 

µ

A

1.65 V to 3.6 V

0.2

IOL = 4 mA

1.65 V

0.45

VOL

IOL = 8 mA

2.3 V

0.7

V

IOL = 12 mA

2.7 V

0.4

IOL = 24 mA

3 V

0.55

II

Control inputs

VI = 0 to 5.5 V

3.6 V

±

5

µ

A

VI = 0.58 V

1 65 V

VI = 1.07 V

1.65 V

VI = 0.7 V

2 3 V

45

II(hold) A or B ports

VI = 1.7 V

2.3 V

–45

µ

A

(

)

VI = 0.8 V

3 V

75

VI = 2 V

3 V

–75

VI = 0 to 3.6 V§

3..6 V

±

500

Ioff

VI or VO = 5.5 V

0

±

10

µ

A

IOZ¶

VO = 0 to 5.5 V

3.6 V

±

10

µ

A

ICC

VI = VCC or GND

IO = 0

3 6 V

20

µ

A

ICC

3.6 V 

 VI 

 5.5 V#

IO = 0

3.6 V

20

µ

A

ICC

One input at VCC – 0.6 V,

Other inputs at 

VCC or GND

2.7 V to 3.6 V

500

µ

A

Ci

Control inputs

VI = VCC or GND

3.3 V

5

pF

Cio

A or B ports

VO = VCC or GND

3.3 V

7.5

pF

† All typical values are at VCC = 3.3 V, TA = 25

°

C.

‡ This information was not available at the time of publication.

§ This is the bus-hold maximum dynamic current required to switch the input from one state to another.

¶ For I/O ports, the parameter IOZ includes the input leakage current, but not II(hold).

# This applies in the disabled state only.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 1.8 V

±

 0.15 V

VCC = 2.5 V

±

 0.2 V

VCC = 2.7 V

VCC = 3.3 V

±

 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

tpd

A or B

B or A

4.7

1

4

ns

ten

OE

A or B

6.7

1.5

5.5

ns

tdis

OE

A or B

7.1

1.5

6.6

ns

tsk(o)||

1

ns

‡ This information was not available at the time of publication.

|| Skew between any two outputs of the same package switching in the same direction

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SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

operating characteristics, T

= 25

°

C

PARAMETER

TEST

CONDITIONS

VCC = 1.8 V

±

 0.15 V

VCC = 2.5 V

±

 0.2 V

VCC = 3.3 V

±

 0.3 V

UNIT

CONDITIONS

TYP

TYP

TYP

Cpd

Power dissipation capacitance

Outputs enabled

f = 10 MHz

40

pF

Cpd

per transceiver

Outputs disabled

f = 10 MHz

4

pF

† This information was not available at the time of publication.

background image

SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 1.8 V 

±

 0.15 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

1k

 Ω

1k

 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, ZO = 50 

, tr

2 ns, tf

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 1. Load Circuit and Voltage Waveforms

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SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.5 V 

±

 0.2 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500

 Ω

500

 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, ZO = 50 

, tr

2 ns, tf

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 2. Load Circuit and Voltage Waveforms

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SN74LVCH16245A

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

 

SCES063G – DECEMBER 1995 – REVISED JUNE 1998

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.7 V AND 3.3 V 

±

 0.3 V

VOH

VOL

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

6 V

Open

GND

500

 Ω

500

 Ω

tPLH

tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

1.5 V

1.5 V

2.7 V

0 V

1.5 V

1.5 V

VOH

VOL

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

0 V

1.5 V

2.7 V

0 V

1.5 V

1.5 V

0 V

2.7 V

0 V

1.5 V

1.5 V

tw

Input

2.7 V

2.7 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, ZO = 50 

, tr

2.5 ns, tf

2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

Figure 3. Load Circuit and Voltage Waveforms

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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