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SN74LVC161284

19-BIT BUS INTERFACE

 

 

SCAS583I – NOVEMBER 1996 – REVISED MARCH 1999

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

1.4-k

 Pullup Resistors Integrated on All

Open-Drain Outputs Eliminate the Need for

Discrete Resistors

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Designed for the IEEE Std 1284-I (Level 1

Type) and IEEE Std 1284-II (Level 2 Type)

Electrical Specifications

D

Flow-Through Architecture Optimizes PCB

Layout

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin-Shrink

Small-Outline (DGG) Packages

description

The SN74LVC161284 is designed for 3-V to 3.6-V

V

CC

 operation. This device provides

asynchronous two-way communication between

data buses. The control-function implementation

minimizes external timing requirements.

This device has eight bidirectional bits; data can

flow in the A-to-B direction when DIR is high, and

in the B-to-A direction when DIR is low. This

device also has five drivers, which drive the cable

side, and four receivers. The SN74LVC161284

has one receiver dedicated to the HOST LOGIC

line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in

a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive

requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel

peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have

a 1.4-k

 integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low

state or if the output voltage is above V

CC

 CABLE. If V

CC

 CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. V

CC

 is designed for 3-V to 3.6-V operation. V

CC

 CABLE supplies the inputs

and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even

when V

CC

 CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The SN74LVC161284 is characterized for operation from 0

°

C to 70

°

C.

Copyright 

©

 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

HD

A9

A10

A11

A12

A13

V

CC

A1

A2

GND

A3

A4

A5

A6

GND

A7

A8

V

CC

PERI LOGIC IN

A14

A15

A16

A17

HOST LOGIC OUT

DIR

Y9

Y10

Y11

Y12

Y13

V

CC

 CABLE

B1

B2

GND

B3

B4

B5

B6

GND

B7

B8

V

CC

 CABLE

PERI LOGIC OUT

C14

C15

C16

C17

HOST LOGIC IN

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SN74LVC161284

19-BIT BUS INTERFACE

 

 

SCAS583I – NOVEMBER 1996 – REVISED MARCH 1999

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUT

MODE

DIR

HD

OUTPUT

MODE

L

L

Open drain

A9–A13 to Y9–Y13 and PERI LOGIC IN to PERI LOGIC OUT

L

L

Totem pole

B1–B8 to A1–A8 and C14–C17 to A14–A17

L

H

Totem pole

B1–B8 to A1–A8, A9–A13 to Y9–Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14–C17 to A14–A17

H

L

Open drain

A1–A8 to B1–B8, A9–A13 to Y9–Y13, and PERI LOGIC IN to PERI LOGIC OUT

H

L

Totem pole

C14–C17 to A14–A17

H

H

Totem pole

A1–A8 to B1–B8, A9–A13 to Y9–Y13, C14–C17 to A14–A17, and PERI LOGIC IN to PERI LOGIC OUT

logic diagram

See Note B

See Note B

See Note A

B1–B8

Y9–Y13

PERI LOGIC OUT

C14–C17

HOST LOGIC IN

VCC CABLE

DIR

HD

A1–A8

A9–A13

PERI LOGIC IN

A14–A17

HOST LOGIC OUT

42

48

1

19

24

30

25

NOTES: A. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND.

B. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The

PMOS transistor is turned off when the associated driver is in the low state.

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SN74LVC161284

19-BIT BUS INTERFACE

 

 

SCAS583I – NOVEMBER 1996 – REVISED MARCH 1999

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range: V

CC

 CABLE 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

V

CC

 

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input and output voltage range, V

I

 and V

O

: Cable side (see Notes 1 and 2) 

–2 V to 7 V

. . . . . . . . . . . . . . . . . . 

Peripheral side (see Note 1) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

: Except PERI LOGIC OUT 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

PERI LOGIC OUT 

±

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through each V

CC

 or GND 

±

200 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output high sink current, I

SK

 (V

O

 = 5.5 V and V

CC

 CABLE = 3 V) 

65 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 3): DGG package 

89

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

94

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is greater than –0.5 V.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC CABLE

Supply voltage for the cable side, VCC CABLE 

 VCC

3

5.5

V

VCC

Supply voltage

3

3.6

V

A, B, DIR, and HD

2

VIH

High level input voltage

C14–C17

2.3

V

VIH

High-level input voltage

HOST LOGIC IN

2.6

V

PERI LOGIC IN

2

A, B, DIR, and HD

0.8

VIL

Low level input voltage

C14–C17

0.8

V

VIL

Low-level input voltage

HOST LOGIC IN

1.6

V

PERI LOGIC IN

0.8

VI

Input voltage

Peripheral side

0

VCC

V

VI

Input voltage

Cable side

0

5.5

V

VO

Open-drain output voltage

HD low

0

5.5

V

HD high, B and Y outputs

–14

IOH

High-level output current

A outputs and HOST LOGIC OUT

–4

mA

PERI LOGIC OUT

–0.5

B and Y outputs

14

IOL

Low-level output current

A outputs and HOST LOGIC OUT

4

mA

PERI LOGIC OUT

84

TA

Operating free-air temperature

0

70

°

C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74LVC161284

19-BIT BUS INTERFACE

 

 

SCAS583I – NOVEMBER 1996 – REVISED MARCH 1999

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,

V

CC 

CABLE = 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

V

I

t h

t

i

VthH – VthL for all inputs except the

C inputs and HOST LOGIC IN

3.3 V

0.4

V

Vt

Input hysteresis

VthH – VthL for the HOST LOGIC IN

3.3 V

0.2

V

VthH – VthL for the C inputs

3.3 V

0.8

HD high B and Y outputs

IOH = 14 mA

3 V

2.23

HD high, B and Y outputs

IOH = –14 mA

3.3 V‡

2.4

VOH

HD high, A outputs, and

IOH = –4 mA

3 V

2.4

V

VOH

g ,

,

HOST LOGIC OUT

IOH = –50 

µ

A

3 V

2.8

V

PERI LOGIC OUT

IOH = 0 5 mA

3.15 V

3.1

PERI LOGIC OUT

IOH = –0.5 mA

3.3 V‡

4.5

B and Y outputs

IOL = 14 mA

3 V

0.77

VOL

A outputs and HOST LOGIC OUT

IOL =  50 

µ

A

3 V

0.2

V

VOL

A outputs and HOST LOGIC OUT

IOL =  4 mA

3 V

0 4

V

PERI LOGIC OUT

IOL = 84 mA

3 V

0.8

C inputs

VI = VCC

3.6 V

w

50

µ

A

II

C inputs

VI = GND (pullup resistors)

3.6 V

w

–3.5

mA

All inputs except the B or C inputs

VI = VCC or GND

3.6 V

±

1

µ

A

B outputs

VO = VCC

3.6 V

20

µ

A

IOZ

B outputs

VO = GND (pullup resistors)

3.6 V

w

–3.5

mA

IOZ

A1–A8

VO = VCC or GND

3.6 V

±

20

µ

A

Open-drain Y outputs

VO = GND (pullup resistors)

3.6 V

w

–3.5

mA

I ff

Leakage to GND, B and Y outputs

VI or VO = 0 to 7 V

0 V

100

µ

A

Ioff

Leakage to VCC, B and Y outputs

VI or VO = 0 to 7 V

0 V

10

µ

A

ICC¶

VI = VCC,

IO = 0

3.6 V

0.8

mA

ICC¶

VI = GND (12 

×

 pullup)

3.6 V

45

mA

Ci

Control inputs

VI = VCC or GND

3.3 V

3

4

pF

Cio

All inputs

VO = VCC or GND

3.3 V

7

15

pF

ZO

Cable side

IOH = –35 mA

3.3 V

45

R pullup

Cable side

VO = 0 V (in Hi Z)

3.3 V

1.15

1.65

k

† Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25

°

C.

‡ VCC CABLE = 4.7 V

§ VCC CABLE = 3.6 V

¶  A maximum current of 170 

µ

A per pin is added to ICC if the pullup resistor pin is above VCC.

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SN74LVC161284

19-BIT BUS INTERFACE

 

 

SCAS583I – NOVEMBER 1996 – REVISED MARCH 1999

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figures 1 and 2)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN

TYP†

MAX

UNIT

tPLH

Totem pole

A or B

B or A

1

40

ns

tPHL

Totem pole

A or B

B or A

1

40

ns

tslew

Totem pole

Cable-side outputs

0.05

0.4

V/ns

ten

Totem pole

HD

B, Y, and PERI LOGIC OUT

1

25

ns

tdis

Totem pole

HD

B, Y, and PERI LOGIC OUT

1

25

ns

ten–tdis

1

10

ns

ten

DIR

A

1

50

ns

tdi

DIR

A

1

15

ns

tdis

DIR

B

1

50

ns

tr, tf

Open drain

A

B or Y

120

ns

tsk(o)‡

A or B

B or A

2.5

10

ns

† Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25

°

C.

‡ Skew is measured at 1/2 (VOH + VOL) for signals switching in the same direction.

operating characteristics, V

CC 

= 3.3 V, T

= 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

Outputs enabled

CL = 0,

f = 10 MHz

45

pF

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SN74LVC161284

19-BIT BUS INTERFACE

 

 

SCAS583I – NOVEMBER 1996 – REVISED MARCH 1999

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Output

(see Note C)

tPHL

tPLH

From

B or Y Output

Under Test

SLEW RATE A-TO-B OR A-TO-Y LOAD (Totem Pole)

VOLTAGE WAVEFORMS MEASURED AT TP1 

PROPAGATION DELAY TIMES (A to B)

2.7 V

VOH

VOL

0 V

62 

CL = 50 pF

(see Note A)

TP1

VCC

CL = 50 pF

(see Note A)

Sink Load

Source Load

1.4 V

VOH – 1.4 V

62 

tPHL

tPLH

Input

(see Note B)

Output

(see Note B)

1.4 V

VOL + 1.4 V

tw

A-TO-B LOAD OR A-TO-Y LOAD (Open Drain)

VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE

2.7 V

VOH

VOL

0 V

1.4 V

1.4 V

2 V

2 V

0.8 V

0.8 V

tr

tf

TP1

From

B or Y Output

CL = 50 pF

(see Note A)

500 

VCC

NOTES: A. CL includes probe and jig capacitance.

B. Input rise and fall times are 3 ns, 150 ns < pulse duration < 10 

µ

s for both low-to-high and high-to-low transitions. 

Slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and 1.9 V for the falling edge.

C. Input rise and fall times are 3 ns. Rise and fall times (open drain) < 120 ns.

D. The outputs are measured one at a time with one transition per measurement.

Input

(see Note C)

Figure 1. Load Circuits and Voltage Waveforms

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SN74LVC161284

19-BIT BUS INTERFACE

 

 

SCAS583I – NOVEMBER 1996 – REVISED MARCH 1999

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Input

(see Note D)

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

VCC 

×

 2 V

Open

GND

500 

500

 Ω

Output

Control

Output

Waveform 1

S1 at VCC 

×

 2 V

(see Note C)

Output

Waveform 2

S1 at GND

(see Note C)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.4 V

1.4 V

3 V

0 V

1.4 V

VOL + 0.3 V

1.4 V

VOH – 0.3 V

0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

VCC 

×

 2 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Input rise and fall times are 3 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. Input rise and fall times are 3 ns. Pulse duration is 150 ns < tw < 10 

µ

s.

E. The outputs are measured one at a time with one transition per measurement.

tPHL

tPLH

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (B to A)

2.7 V

VOH

VOL

0 V

1.4 V

50% VCC

Input

(see Note B)

Output

1.4 V

50% VCC

B-TO-A LOAD (Totem Pole)

tPHL

tPLH

From

B or Y Output

Under Test

A-TO-B LOAD OR A-TO-Y LOAD (Totem Pole)

VOLTAGE WAVEFORMS MEASURED AT TP1

PROPAGATION DELAY TIMES (A to B)

2.7 V

VOH

VOL

0 V

500 

CL = 50 pF

(see Note A)

TP1

VCC

CL = 50 pF

(see Note A)

Sink Load

Source Load

1.4 V

VOH – 1.4 V

500 

tPHL

tPLH

Output

1.4 V

VOL + 1.4 V

tw

Figure 2. Load Circuit and Voltage Waveforms

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Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1999, Texas Instruments Incorporated