background image

 

SN54ABT620, SN74ABT620

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS113D – FEBRUARY 1991 – REVISED APRIL 1998

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

State-of-the-Art 

EPIC-

ΙΙ

B

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per

JESD 17

D

Typical V

OLP

 (Output Ground Bounce) < 1 V

at V

CC

 = 5 V, T

A

 = 25

°

C

D

High-Drive Outputs (–32-mA I

OH

,

64-mA I

OL

)

D

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK), and

Plastic (N) and Ceramic (J) DIPs

description

These octal bus transceivers provide for

asynchronous communication between data

buses. The control-function implementation

allows for maximum flexibility in timing. The

’ABT620 devices provide inverted data at the

outputs.

These devices allow data transmission from the

A bus to the B bus or from the B bus to the A bus,

depending on the logic levels at the output-enable

(OEAB and OEBA) inputs.

The output-enable inputs can be used to disable the device so that the buses are effectively isolated. The

dual-enable configuration gives the transceivers the capability of storing data by simultaneously enabling OEAB

and OEBA. When both OEAB and OEBA are enabled and all other data sources to the two sets of bus lines

are at high impedance, both sets of bus lines (16 total) remain at their last states. In this way, each output

reinforces its input in this configuration.

To ensure the high-impedance state during power up or power down, OEBA should be tied to V

CC

 through a

pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by

the current-sourcing capability of the driver.

The SN54ABT620 is characterized for operation over the full military temperature range of –55

°

C to 125

°

C. The

SN74ABT620 is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 1998, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-

ΙΙ

B is a trademark of Texas Instruments Incorporated.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OEAB

A1

A2

A3

A4

A5

A6

A7

A8

GND

V

CC

OEBA

B1

B2

B3

B4

B5

B6

B7

B8

SN54ABT620 . . . J  PACKAGE

SN74ABT620 . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

B1

B2

B3

B4

B5

A3

A4

A5

A6

A7

 SN54ABT620 . . . FK PACKAGE

(TOP VIEW)

A2

A1

OEAB

B7

B6

OEBA

A8

GND

B8

V

CC

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SN54ABT620, SN74ABT620

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS113D – FEBRUARY 1991 – REVISED APRIL 1998

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OPERATION

OEBA

OEAB

OPERATION

L

L

B data to A bus

L

H

B data to A bus,

A data to B bus

H

L

Isolation

H

H

A data to B bus

logic symbol

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

EN1

19

EN2

1

OEAB

2

A1

3

A2

B1

18

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

B2

17

B3

16

B5

14

B4

15

B6

13

B8

11

B7

12

OEBA

1

1

2

1

logic diagram (positive logic)

To Seven Other Channels

19

1

2

18

OEBA

B1

OEAB

A1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high or power-off state, V

O

 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . 

Current into any output in the low state, I

O

: SN54ABT620 96 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ABT620 128 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): DB package 

115

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DW package 

97

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

N package 

67

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

PW package 

128

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace

length of zero.

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SN54ABT620, SN74ABT620

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS113D – FEBRUARY 1991 – REVISED APRIL 1998

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54ABT620

SN74ABT620

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High-level output current

–24

–32

mA

IOL

Low-level output current

48

64

mA

t/

v

Input transition rise or fall rate

Outputs enabled

5

5

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: All unused pins (control or I/O) of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application

report, 

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABT620, SN74ABT620

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS113D – FEBRUARY 1991 – REVISED APRIL 1998

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABT620

SN74ABT620

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

–1.2

–1.2

V

VCC = 4.5 V,

IOH = –3 mA

2.5

2.5

2.5

VOH

VCC = 5 V,

IOH = –3 mA

3

3

3

V

VOH

VCC = 4 5 V

IOH = –24 mA

2

2

V

VCC = 4.5 V

IOH = –32 mA

2*

2

VOL

VCC = 4 5 V

IOL = 48 mA

0.55

0.55

V

VOL

VCC = 4.5 V

IOL = 64 mA

0.55*

0.55

V

Vhys

100

mV

II

Control inputs

VCC = 5 5 V

VI = VCC or GND

±

1

±

1

±

1

µ

A

II

A or B ports

VCC = 5.5 V,

VI = VCC or GND

±

100

±

100

±

100

µ

A

IOZH‡

VCC = 5.5 V,

VO = 2.7 V

50

50

50

µ

A

IOZL‡

VCC = 5.5 V,

VO = 0.5 V

–50

–50

–50

µ

A

Ioff

VCC = 0,

VI or VO 

 4.5 V

±

100

±

100

µ

A

ICEX

VCC = 5.5 V,

VO = 5.5 V

Outputs high

50

50

50

µ

A

IO§

VCC = 5.5 V,

VO = 2.5 V

–50

–100

–180

–50

–180

–50

–180

mA

VCC = 5.5 V,

Outputs high

5

250

250

250

µ

A

ICC

A or B ports

VCC = 5.5 V,

IO = 0,

Outputs low

24

30

30

30

mA

VI = VCC or GND

Outputs disabled

0.5

250

250

250

µ

A

Data inp ts

VCC = 5.5 V,

One input at 3.4 V,

Outputs enabled

1.5

1.5

1.5

ICC¶

Data inputs

,

Other inputs at

VCC or GND

Outputs disabled

0.05

0.05

0.05

mA

Control inputs

VCC = 5.5 V, One input at 3.4 V,

Other inputs at VCC or GND

1.5

1.5

1.5

Ci

Control inputs

VI = 2.5 V or 0.5 V

4

pF

Cio

A or B ports

VO = 2.5 V or 0.5 V

7

pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.

† All typical values are at VCC = 5 V.

‡ The parameters IOZH and IOZL include the input leakage current.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABT620, SN74ABT620

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS113D – FEBRUARY 1991 – REVISED APRIL 1998

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

SN54ABT620

SN74ABT620

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

MIN

MAX

tPLH

A or B

B or A

1

4.1

1

1

4.8

ns

tPHL

A or B

B or A

1

4.3

1

1

4.8

ns

tPZH

OEBA

A

1.3

4.6

1.3

1.3

5.5

ns

tPZL

OEBA

A

1

6.1

1

1

7.1

ns

tPHZ

OEBA

A

2

6.3

2

2

7

ns

tPLZ

OEBA

A

1.4

5.4

1.4

1.4

5.8

ns

tPZH

OEAB

B

1.6

6.2

1.6

1.6

6.8

ns

tPZL

OEAB

B

2

5.9

2

2

6.4

ns

tPHZ

OEAB

B

1.2

5.6

1.2

1.2

6.5

ns

tPLZ

OEAB

B

1.1

4.7

1.1

1.1

5.6

ns

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABT620, SN74ABT620

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS113D – FEBRUARY 1991 – REVISED APRIL 1998

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

th

tsu

From Output

 Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

[

 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1998, Texas Instruments Incorporated