background image

 

SN54LVTH16245A, SN74LVTH16245B

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS143M – MAY 1992 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

D

Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

CC

)

D

Support Unregulated Battery Operation

Down to 2.7 V

D

Distributed V

CC

 and GND Pins Minimize

High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB

Layout

D

Typical V

OLP

 (Output Ground Bounce)

<0.8 V at V

CC

 = 3.3 V, T

A

 = 25

°

C

D

I

off 

and Power-Up 3-State Support Hot

Insertion

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II (SN74LVTH16245B Only)

D

ESD Protection Exceeds JESD 22

–  2000-V Human-Body Model (A114-A)

–  200-V Machine Model (A115-A)

–  1000-V Charged-Device Model (C101)

(SN74LVTH16245B Only)

D

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The SN54LVTH16245A and SN74LVTH16245B devices are 16-bit (dual-octal) noninverting 3-state

transceivers designed for low-voltage (3.3-V) V

CC

 operation, but with the capability to provide a TTL interface

to a 5-V system environment.

These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission

from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control

(DIR) input. The output-enable (OE) input can be used to disable the devices so that the buses are

effectively isolated.

Copyright 

©

 2000, Texas Instruments Incorporated

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

SN54LVTH16245A . . . WD  PACKAGE

SN74LVTH16245B . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1DIR

1B1

1B2

GND

1B3

1B4

V

CC

1B5

1B6

GND

1B7

1B8

2B1

2B2

GND

2B3

2B4

V

CC

2B5

2B6

GND

2B7

2B8

2DIR

1OE

1A1

1A2

GND

1A3

1A4

V

CC

1A5

1A6

GND

1A7

1A8

2A1

2A2

GND

2A3

2A4

V

CC

2A5

2A6

GND

2A7

2A8

2OE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

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SN54LVTH16245A, SN74LVTH16245B

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS143M – MAY 1992 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

description (continued)

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V

CC

 is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to V

CC

 through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I

off

 and power-up 3-state. The I

off

 circuitry

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

The SN54LVTH16245A is characterized for operation over the full military temperature range of –55

°

C to

125

°

C. The SN74LVTH16245B is characterized for operation from –40

°

C to 85

°

C.

FUNCTION TABLE

(each 8-bit section)

INPUTS

OPERATION

OE

DIR

OPERATION

L

L

B data to A bus

L

H

A data to B bus

H

X

Isolation

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SN54LVTH16245A, SN74LVTH16245B

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS143M – MAY 1992 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

1OE

2OE

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1A1

47

G3

48

3 EN1 [BA]

1

1DIR

3 EN2 [AB]

G6

25

6 EN4 [BA]

24

2DIR

6 EN5 [AB]

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2A1

36

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1

4

2

5

logic diagram (positive logic)

To Seven Other Channels

1DIR

1A1

1B1

1OE

To Seven Other Channels

2DIR

2A1

2B1

2OE

1

47

24

36

48

2

25

13

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SN54LVTH16245A, SN74LVTH16245B

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS143M – MAY 1992 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high-impedance

or power-off state, V

O

 (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high state, V

O

 (see Note 1) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . 

Current into any output in the low state, I

O

: SN54LVTH16245A 96 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74LVTH16245B

128 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Current into any output in the high state, I

(see Note 2): SN54LVTH16245A 

48 mA

. . . . . . . . . . . . . . . . . . . . 

SN74LVTH16245B 64 

mA

. . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK 

(V

< 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK 

(V

< 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 3): DGG package 

70

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DGV package 

58

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

63

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

SN54LVTH16245A

SN74LVTH16245B

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

2.7

3.6

2.7

3.6

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

5.5

5.5

V

IOH

High-level output current

–24

–32

mA

IOL

Low-level output current

48

64

mA

t/

v

Input transition rise or fall rate

Outputs enabled

10

10

ns/V

t/

VCC

Power-up ramp rate

200

200

µ

s/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE  4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

background image

SN54LVTH16245A, SN74LVTH16245B

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS143M – MAY 1992 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN54LVTH16245A

SN74LVTH16245B

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

TYP†

MAX

UNIT

VIK

VCC = 2.7 V,

II = –18 mA

–1.2

–1.2

V

VCC = 2.7 V to 3.6 V,

IOH = –100 

µ

A

VCC–0.2

VCC–0.2

VOH

VCC = 2.7 V,

IOH = –8 mA

2.4

2.4

V

VOH

VCC = 3 V

IOH = –24 mA

2

V

VCC = 3 V

IOH = –32 mA

2

VCC = 2 7 V

IOL = 100 

µ

A

0.2

0.2

VCC = 2.7 V

IOL = 24 mA

0.5

0.5

VOL

IOL = 16 mA

0.4

0.4

V

VOL

VCC = 3 V

IOL = 32 mA

0.5

0.5

V

VCC = 3 V

IOL = 48 mA

0.55

IOL = 64 mA

0.55

Control

VCC = 3.6 V,

VI = VCC or GND

±

1

±

1

inputs

VCC = 0 or 3.6 V,

VI = 5.5 V

10

10

II

A

B

VI = 5.5 V

20

20

µ

A

A or B

ports‡

VCC = 3.6 V

VI = VCC

5

1

orts‡

VI = 0

–5

–5

Ioff

VCC = 0,

VI or VO = 0 to 4.5 V

±

100

µ

A

VCC = 3 V

VI = 0.8 V

75

75

II(hold) A or B ports

VCC = 3 V

VI = 2 V

–75

–75

µ

A

(

)

VCC = 3.6 V§,

VI = 0 to 3.6 V

±

500

IOZPU

VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,

OE = don’t care

±

100*

±

100

µ

A

IOZPD

VCC = 1.5 V to 0, VO = 0.5 V to 3 V,

OE = don’t care

±

100*

±

100

µ

A

VCC = 3.6 V,

Outputs high

0.19

0.19

ICC

VCC = 3.6 V,

IO = 0,

Outputs low

5

5

mA

CC

VI = VCC or GND

Outputs disabled

0.19

0.19

ICC¶

VCC = 3 V to 3.6, One input at VCC – 0.6 V,

Other inputs at VCC or GND

0.2

0.2

mA

Ci

VI = 3 V or 0

4

4

pF

Cio

VO = 3 V or 0

10

10

pF

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

† All typical values are at VCC = 3.3 V, TA = 25

°

C.

‡ Unused pins at VCC or GND

§ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

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SN54LVTH16245A, SN74LVTH16245B

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS143M – MAY 1992 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Figure 1)

SN54LVTH16245A

SN74LVTH16245B

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

±

 0.3 V

VCC = 2.7 V

VCC = 3.3 V

±

 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

TYP†

MAX

MIN

MAX

tPLH

A or B

B or A

0.5

4.5

4.6

1.5

2.3

3.3

3.7

ns

tPHL

A or B

B or A

0.5

4.4

3.9

1.3

2.1

3.3

3.5

ns

tPZH

OE

A or B

0.5

6.5

6.6

1.5

2.8

4.5

5.3

ns

tPZL

OE

A or B

0.5

5.4

6.2

1.6

2.9

4.6

5.2

ns

tPHZ

OE

A or B

1

6.8

7

2.3

3.7

5.1

5.5

ns

tPLZ

OE

A or B

1

6.2

6.3

2.2

3.5

5.1

5.4

ns

tsk(o)

0.5

ns

† All typical values are at VCC = 3.3 V, TA = 25

°

C.

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SN54LVTH16245A, SN74LVTH16245B

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS143M – MAY 1992 – REVISED MARCH 2000

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500 

500

 Ω

Data Input

Timing Input

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

2.7 V

0 V

Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

3 V

0 V

VOL + 0.3 V

VOH – 0.3 V

 0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

6 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 2000, Texas Instruments Incorporated