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Rev. 2.2 - 4/27/98

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3

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5

6

7

8

9

10

11

12

 

Features

 

n

 

High-speed access times

Com’l: 7, 8, 10, 12 and 15 ns

Industrial: 8, 10, 12 and 15 ns

 

n

 

Low power operation (typical)

- PDM41257SA

Active: 400 mW 

Standby: 150 mW 

- PDM41257LA

Active: 350 mW 

Standby: 25 mW 

 

n

 

Single +5V (

 

±

 

10%) power supply

 

n

 

TTL compatible inputs and outputs

 

n

 

Packages

Plastic SOJ (300 mil) - SO 

 

 

Description

 

The PDM41257 is a high-performance CMOS static

RAM organized as 262,144 x 1 bit. Writing to this

device is accomplished when the write enable (WE)

and the chip enable (CE) inputs are both LOW.

Reading is accomplished when WE remains HIGH

and CE goes LOW. 

The PDM41257 operates from a single +5V power

supply and all the inputs and outputs are fully TTL-

compatible. The PDM41257 comes in two versions,

the standard power version PDM41257SA and a low

power version the PDM41257LA. The two versions

are functionally the same and only differ in their

power consumption.

The PDM41257 is available in a 24-pin 300-mil

plastic SOJ for surface mount applications.

A0

A17

CE

WE

Addresses

Decoder

Memory

Matrix

Column I/O

• • • • •

D

IN

D

OUT

 

Functional Block Diagram

 

PDM41257

 

256K Static RAM

256K x 1-Bit

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PDM41257

 

2

Rev. 2.2 - 4/27/98

 

Truth Table

 

NOTE: 1. H = V

 

IH

 

, L = V

 

IL

 

, X = DON’T CARE

 

Absolute Maximum Ratings

 

 (1)

 

NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may 

cause permanent damage to the device. This is a stress rating only and functional 

operation of the device at these or any other conditions above those indicated in the 

operational sections of this specification is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may affect reliability.

2.  Appropriate thermal calculations should be performed in all cases and specifically for 

those where the chosen package has a large thermal resistance (e.g., TSOP). The 

calculation should be of the form

: T

 

 

 = T

 

a

 

 + P * 

 

θ

 

ja

 

, where T

 

a

 

 is the ambient tempera-

ture, P is average operating power and 

 

θ

 

ja

 

 the thermal resistance of the package. For 

this product, use the following 

 

θ

 

ja

 

 value:

SOJ: 83

 

o

 

 C/W

 

WE

CE

D

 

OUT

 

MODE

 

X

H

Hi-Z

Standby

H

L

D

 

OUT

 

Read

L

L

Hi-Z

Write

 

Symbol

Rating

Com’l.

Ind.

Unit

 

T

 

TERM

 

Terminal Voltage with Respect to V

 

SS

 

–0.5 to +7.0

–0.5 to +7.0

 

°

 

C

T

 

BIAS

 

Temperature Under Bias

–55 to +125

–65 to +135

 

°

 

C

T

 

STG

 

Storage Temperature

–55 to +125

–65 to +150

 

°

 

C

P

 

T

 

Power Dissipation

1.0

1.0

W

I

 

OUT

 

DC Output Current

50

50

mA

T

 

j

 

Maximum Junction Temperature 

 

(2)

 

125

145

 

°

 

C

SOJ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A0

A1

A2

A3

A4

A5

A6

A7

A8

D

OUT

WE

Vss

Vcc

A17

A16

A15

A14

A13

A12

A11

A10

A9

D

IN

CE

 

Pin Configuration

Pin Description

 

Name

Description

 

A17-A0

Address Inputs

D

 

IN

 

Data Input

D

 

OUT

 

Data Output

WE

Write Enable Input

CE

Chip Enable Input

V

 

CC

 

Power (+5V)

V

 

SS

 

Ground

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PDM41257

 

Rev. 2.2 - 4/27/98

3

1

2

3

4

5

6

7

8

9

10

11

12

 

Recommended DC Operating Conditions

DC Electrical Characteristics 

 

(V

 

CC

 

 = 5.0V 

 

±

 

 10%)

NOTE:

1. V

 

IL

 

(min) = –3.0V for pulse width less than 20 ns.

 

Power Supply Characteristics

 

SHADED AREA = PRELIMINARY DATA

NOTE: All values are maximum guaranteed values.

 

Symbol

Parameter

Min.

Typ.

Max.

Unit

 

V

 

CC

 

Supply Voltage

4.5

5.0

5.5

V

V

 

SS

 

Supply Voltage

0

0

0

V

Commercial

Ambient Temperature

0

25

70

 

°

 

C

Industrial

Ambient Temperature

–40

25

85

 

°

 

C

 

PDM41257SA

PDM41257LA

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

 

I

 

LI

 

Input Leakage Current 

V

 

CC

 

 = MAX., V

 

IN

 

 = V

 

SS

 

 to V

 

CC

 

Com’l/

Ind.

–5

5

–5

5

 

µ

 

A

I

 

LO

 

Output Leakage Current

V

 

CC

 

= MAX., 

CE = V

 

IH

 

, V

 

OUT

 

 = V

 

SS

 

 to V

 

CC

 

Com’l/

Ind.

–5

5

–5

5

 

µ

 

A

V

 

IL

 

Input Low Voltage

–0.5

 

(1)

 

0.8

–0.5

 

(1)

 

0.8

V

V

 

IH

 

Input High Voltage

2.2

6.0

2.2

6.0

V

V

 

OL

 

Output Low Voltage

I

 

OL 

 

= 8 mA, V

 

CC

 

 = Min.

I

 

OL

 

 = 10 mA, V

 

CC

 

 = Min.

0.4

0.5

0.4

0.5

V

V

V

 

OH

 

Output High Voltage

I

 

OH

 

 = –4 mA, V

 

CC

 

 = Min.

2.4

2.4

V

 

-7

-8

-10

-12

-15

Symbol Parameter

Power

Com’l.   

Com’l.   

Ind.

Com’l.   

Ind.

Com’l.   

Ind.

Com’l.   

Ind.

Units

 

I

 

CC

 

Operating Current

CE = V

 

IL

 

SA

210

200

210

190

200

180

190

170

180

mA

f = f

 

MAX

 

 = 1/t

 

RC

 

V

 

CC

 

 = Max  

I

 

OUT

 

 = 0 mA

LA

190

180

190

170

180

160

170

150

160

mA

I

 

SB

 

Standby Current

CE = V

 

IH

 

  

SA

90

80

80

70

70

60

60

50

50

mA

f = f

 

MAX

 

 = 1/t

 

RC

 

V

 

CC

 

 = Max

LA

90

80

80

70

70

60

60

50

50

mA

I

 

SB1

 

Full Standby Current

CE 

 

 

 V

 

CC

 

 – 0.2V

SA

20

20

20

20

20

20

20

20

20

mA

f = 0

V

 

CC

 

 = Max

V

 

IN

 

 

 

 

 V

 

CC

 

 – 0.2V or 

 

 

 0.2V

LA

5

5

5

5

5

5

5

5

5

mA

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PDM41257

 

4

Rev. 2.2 - 4/27/98

 

Capacitance

 

(1)

 

 

 

(T

 

A

 

 = +25

 

°

 

C, f = 1.0 MHz)

NOTE: 1. This parameter is determined by device characterization but is not production tested.

 

AC Test  Conditions

 

Symbol

Parameter

Conditions

Max.

Unit

 

C

 

IN

 

Input Capacitance

V

 

IN

 

 = 0V

8

pF

C

 

OUT

 

Output Capacitance

V

 

OUT

 

 = 0V

8

pF

Input Pulse Levels

V

 

SS

 

 to 3.0V

Input rise and fall times

3 ns

Input timing reference levels

1.5V

Output reference levels

1.5V

Output load

See Figures 1 and 2

Figure 1. Output Load Equivalent

Figure 2. Output Load Equivalent

(for t

LZCE

, t

HZCE

, t

LZWE

, t

HZWE

)

+5V

480

255

D

OUT

30 pF

+5V

480

255

D

OUT

5 pF

5

4

3

2

1

0

0

30

60

90

120

Typical Delta tAA vs Capacitive Loading

Additional Lumped Capacitive Loading (pF)

Delta t

AA

 - nS

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PDM41257

 

Rev. 2.2 - 4/27/98

5

1

2

3

4

5

6

7

8

9

10

11

12

 

Read Cycle No. 1

 

(1)

 

Read Cycle No. 2

 

(2)

 

AC Electrical Characteristics

 

SHADED AREA = PRELIMINARY DATA.

Notes referenced are after Data Retention Table.

 

Description

-7

(6)

-8

(6)

-10

(6)

-12

-15

READ Cycle

Sym

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Units

READ cycle time

t

RC

7

8

10

12

15

ns

Address access time

t

AA

7

8

10

12

15

ns

Chip enable access time

t

ACE

7

8

10

12

15

ns

Output hold from address change

t

OH

3

3

3

3

3

ns

Chip enable to output in low Z

(3, 4, 5)

t

LZCE

5

5

5

5

5

ns

Chip disable to output in high Z

(3, 4, 5)

t

HZCE

5

5

10

10

10

ns

Chip enable to power up time

(4)

t

PU

0

0

0

0

0

ns

Chip disable to power down time

(4)

t

PD

7

8

10

12

15

ns

tRC

tAA

tOH

PREVIOUS DATA VALID

DOUT

ADDR

DATA VALID

t

RC

t

ACE

t

AA

t

LZCE

t

HZCE

t

LZOE

t

HZOE

t

AOE

ADDR

CE

D

OUT

DATA VALID

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PDM41257

6

Rev. 2.2 - 4/27/98

Write Cycle No. 1 (Write Enable Controlled) 

Write Cycle No. 2 (Chip Enable Controlled) 

AC Electrical Characteristics

SHADED AREA = PRELIMINARY DATA

Description

-7

(6)

-8

(6)

-10

(6)

-12

-15

WRITE Cycle

Sym

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Units

WRITE cycle time

t

WC

7

8

10

12

15

ns

Chip enable to end of write

t

CW

7

8

10

10

12

ns

Address valid to end of write

t

AW

7

8

10

10

12

ns

Address setup time

t

AS

0

0

0

0

0

ns

Address hold from end of write

t

AH

0

0

0

0

0

ns

Write pulse width

t

WP

7

8

10

10

11

ns

Data setup time

t

DS

6

7

7

7

8

ns

Data hold time

t

DH

0

0

0

0

0

ns

Write disable to output in low Z

(4,5) 

t

LZWE

0

0

0

0

0

ns

Write enable to output in high Z

(4,5) 

t

HZWE

3

3

3

3

3

ns

t WC

t AW

t CW

t AH

tAS

t HZWE

HIGH Z

DATA VALID

t LZWE

t DS

t DH

ADDR

CE

t WP

WE

DIN

DOUT

tWC

tAW

tCW

t WP

t DS

DATA VALID

tDH

tAS

ADDR

DIN

UNDEFINED

DON'T CARE

tAH

CE

WE

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PDM41257

Rev. 2.2 - 4/27/98

7

1

2

3

4

5

6

7

8

9

10

11

12

Low V

CC

 Data Retention Waveform

Data Retention Electrical Characteristics (LA Version Only)

NOTES: (For three previous Electrical Characteristics tables)

1. The device is continuously selected. Chip Enable is held in its active state.

2. The address is valid prior to or coincident with the latest occuring Chip Enable.

3. At any given temperature and voltage condition, t

HZCE

 is less than t

LZCE

.

4. This parameter is sampled.

5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured 

±

200 mV from steady state voltage.

6. V

CC

 = 5V 

±

 5%.

Ordering Information

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

V

DR

V

CC

 for Retention Data

2

V

I

CCDR

Data Retention Current

CE 

 V

CC

 – 0.2V

V

IN

 

 V

CC

 – 0.2V

or 

 0.2V

V

CC

 = 2V

95

500

µ

A

V

CC

 = 3V

350

750

µ

A

t

CDR

Chip Deselect to Data Retention Time

0

ns

t

R

(4)

Operation Recovery Time

t

RC

ns

DON'T CARE

VCC

V

V

IH

IL

t

CDR

V

t

R

4.5V

4.5V

Data Retention Mode

CE

DR

VDR

Device Type

Power

Speed

Package

Type

Process

Temp. Range

Preferred

Shipping

Container

Commercial (0

°

 to +70

°

C)

 Industrial (–40

°

C to +85

°

C)

7

   Commercial Only

10

12

15

SA 

   

Standard Power

LA          

Low Power

Blank

I

A

   Automotive ( –40

°

C to +105

°

C)

Blank     Tubes

TR         Tape & Reel

TY          Tray

PDM41257 - 256K (256Kx1) Static RAM

XXXXX

X

XX

X

X

X

SO         24-pin 300-mil Plastic SOJ 

Faster Memories for a Faster World ™