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 SN74ABT543A

 OCTAL REGISTERED TRANSCEIVER

 WITH 3-STATE OUTPUTS

 SCBS464A – JUNE 1992 – REVISED JUNE 1994

Copyright 

©

 1994, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

State-of-the-Art 

EPIC-

ΙΙ

B

 BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model (C = 200 pF,

R = 0)

Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

Typical V

OLP

 (Output Ground Bounce) < 1 V

at V

CC

 = 5 V, T

A

 = 25

°

C

High-Drive Outputs (–32-mA I

OH

,

64-mA I

OL

)

Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages, and Standard

Plastic 300-mil DIPs (JT)

description

The SN74ABT543A octal transceiver contains two sets of D-type latches for temporary storage of data flowing

in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are

provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB is

low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the

A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the

data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA,

and OEBA inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to V

CC

 through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74ABT543A is packaged in TI’s shrink small-outline package (DB), which provides the same I/O pin

count and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN74ABT543A is characterized for operation from – 40

°

C to 85

°

C.

FUNCTION TABLE†

INPUTS

OUTPUT

CEAB

LEAB

OEAB

A

B

H

X

X

X

Z

X

X

H

X

Z

L

H

L

X

B0‡

L

L

L

L

L

L

L

L

H

H

† A-to-B data flow is shown; B-to-A flow control is the

same except that it uses CEBA, LEBA, and OEBA.

‡ Output level before the indicated steady-state input

conditions were established.

DB, DW, OR NT PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

LEBA

OEBA

A1

A2

A3

A4

A5

A6

A7

A8

CEAB

GND

V

CC

CEBA

B1

B2

B3

B4

B5

B6

B7

B8

LEAB

OEAB

 

EPIC-

ΙΙ

B is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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SN74ABT543A

OCTAL REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS

SCBS464A – JUNE 1992 – REVISED JUNE 1994

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

1

1

4

2C6

14

3

A1

4

A2

B1

22

5D

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

B2

21

B3

20

B5

18

B4

19

B6

17

B8

15

B7

16

LEAB

3

G2

11

CEAB

2EN4

13

OEAB

1C5

1

LEBA

G1

23

CEBA

1EN3

2

OEBA

6D

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

 

OEBA

CEBA

LEBA

OEAB

CEAB

LEAB

A1

B1

C1

1D

C1

1D

2

23

1

13

11

14

3

22

To Seven Other Channels

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 SN74ABT543A

 OCTAL REGISTERED TRANSCEIVER

 WITH 3-STATE OUTPUTS

 SCBS464A – JUNE 1992 – REVISED JUNE 1994

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

 – 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (except I/O ports) (see Note 1) 

 – 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high state or power-off state, V

O

 

 – 0.5 V to 5.5 V

. . . . . . . . . . . . . 

Current into any output in the low state, I

O

 

 128 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK 

(V

< 0) 

 –18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK 

(V

< 0) 

 – 50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Maximum power dissipation at T

A

 = 55

°

C (in still air): DB package 

0.7 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

 DW 

package

W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

 NT 

package

1.3 

W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range 

 – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

recommended operating conditions (see Note 2)

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

VI

Input voltage

0

VCC

V

IOH

High-level output current

–32

mA

IOL

Low-level output current

64

mA

t/

v

Input transition rise or fall rate

Outputs enabled

5

ns/V

TA

Operating free-air temperature

–40

85

°

C

NOTE 2: Unused or floating pins (input or I/O) must be held high or low.

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SN74ABT543A

OCTAL REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS

SCBS464A – JUNE 1992 – REVISED JUNE 1994

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

MIN

MAX

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = – 18 mA

–1.2

–1.2

V

VCC = 4.5 V,

IOH = – 3 mA

2.5

2.5

VOH

VCC = 5 V,

IOH = – 3 mA

3

3

V

VOH

VCC = 4 5 V

IOH = –24 mA

2

V

VCC = 4.5 V

IOH = – 32 mA

2

VOL

VCC = 4 5 V

IOL = 48 mA

0.55

V

VOL

VCC = 4.5 V

IOL = 64 mA

0.55

V

II

VCC = 5 5 V

VI = VCC or GND

Control inputs

±

1

±

1

µ

A

II

VCC = 5.5 V,

VI = VCC or GND

A or B ports

±

100

±

100

µ

A

IOZH‡

VCC = 5.5 V,

VO = 2.7 V

50

50

µ

A

IOZL‡

VCC = 5.5 V,

VO = 0.5 V

– 50

– 50

µ

A

IOFF

VCC = 0,

VI or VO 

 4.5 V

±

100

±

100

µ

A

ICEX

VCC = 5.5 V,

VO = 5.5 V

Outputs high

50

50

µ

A

IO§

VCC = 5.5 V,

VO = 2.5 V

– 50

–100

–180

– 50

–180

mA

VCC = 5.5 V,

Outputs high

1

250

250

µ

A

ICC

VCC   5.5 V,

IO = 0,

A or B ports

Outputs low

24

34

34

mA

VI = VCC or GND

Outputs disabled

0.5

250

250

µ

A

ICC¶

VCC = 5.5 V,

One input at 3.4 V,

Other inputs at VCC or GND

1.5

1.5

mA

Ci

VI = 2.5 V or 0.5 V

Control inputs

4

pF

Cio

VO = 2.5 V or 0.5 V

A or B ports

7

pF

† All typical values are at VCC = 5 V.

‡ The parameters IOZH and IOZL include the input leakage current.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

VCC = 5 V,

TA = 25

°

C

MIN

MAX

UNIT

MIN

MAX

tw

Pulse duration, LEAB or LEBA low

3.5

3.5

ns

Data before LEAB or LEBA

High

2.5

2.5

t

Setup time

Data before LEAB or LEBA

Low

3

3

ns

tsu

Setup time

Data before CEAB or CEBA

High

2.5

2.5

ns

Data before CEAB or CEBA

Low

2.5

2.5

th

Hold time

Data after LEAB or LEBA

1

1

ns

th

Hold time

Data after CEAB or CEBA

1

1

ns

background image

 SN74ABT543A

 OCTAL REGISTERED TRANSCEIVER

 WITH 3-STATE OUTPUTS

 SCBS464A – JUNE 1992 – REVISED JUNE 1994

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

MIN

MAX

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

tPLH

A or B

B or A

1.6

3.3

4.4

1.6

5

ns

tPHL

A or B

B or A

1.6

4.1

5.1

1.6

6

ns

tPLH

LEBA or LEAB

A or B

1.6

3.9

5.1

1.6

6.2

ns

tPHL

LEBA or LEAB

A or B

1.6

4.4

5.4

1.6

6.3

ns

tPZH

OEBA or OEAB

A or B

1.4

3.1

4.1

1.4

5

ns

tPZL

OEBA or OEAB

A or B

2

3.9

4.9

2

5.7

ns

tPHZ

OEBA or OEAB

A or B

2.5

4.2

5.8

2.5

6.7

ns

tPLZ

OEBA or OEAB

A or B

2.5

4.8

6.1

2.5

7

ns

tPZH

CEBA or CEAB

A or B

1.4

3.4

4.4

1.4

5.4

ns

tPZL

CEBA or CEAB

A or B

2

4.1

5.2

2

6.1

ns

tPHZ

CEBA or CEAB

A or B

3.2

4.7

6.1

3.2

7

ns

tPLZ

CEBA or CEAB

A or B

2.5

5

6.7

2.5

7.3

ns

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SN74ABT543A

OCTAL REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS

SCBS464A – JUNE 1992 – REVISED JUNE 1994

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

th

tsu

From Output

  Under Test

CL = 50 pF

LOAD CIRCUIT FOR OUTPUTS

S1

7 V

Open

GND

500

 Ω

500

 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

1.5 V

tw

Input

(see Note A)

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

Input

(see Note B)

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note C)

Output

Waveform 2

S1 at Open

(see Note C)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

[

 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

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BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1998, Texas Instruments Incorporated