background image

 

SN54ABT16470, SN74ABT16470

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS085E – FEBRUARY 1991 – REVISED MAY 1997

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

State-of-the-Art 

EPIC-

ΙΙ

B

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

D

Typical V

OLP

 (Output Ground Bounce) < 1 V

at V

CC

 = 5 V, T

A

 = 25

°

C

D

Distributed V

CC

 and GND Pin Configuration

Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB

Layout

D

High-Drive Outputs (–32-mA I

OH

, 64-mA I

OL

)

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’ABT16470 are 16-bit registered transceivers

that contain two sets of D-type flip-flops for

temporary storage of data flowing in either

direction. The ’ABT16470 can be used as two 8-bit

transceivers or one 16-bit transceiver. Separate

clock (CLKAB or CLKBA) and output-enable

(OEAB or OEBA) inputs are provided for each

register to permit independent control in either

direction of data flow.

To avoid false clocking of the flip-flops, clock

enable (CLKEN) should not be switched from high

to low while CLK is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V

CC

 through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16470 is characterized for operation over the full military temperature range of –55

°

C to 125

°

C.

The SN74ABT16470 is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-

ΙΙ

B are trademarks of Texas Instruments Incorporated.

SN54ABT16470 . . . WD PACKAGE

SN74ABT16470 . . . DGG OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1OEAB

1CLKAB

1CLKENAB

GND

1A1

1A2

V

CC

1A3

1A4

1A5

GND

1A6

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

V

CC

2A7

2A8

GND

2CLKENAB

2CLKAB

2OEAB

1OEBA

1CLKBA

1CLKENBA

GND

1B1

1B2

V

CC

1B3

1B4

1B5

GND

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

V

CC

2B7

2B8

GND

2CLKENBA

2CLKBA

2OEBA

background image

SN54ABT16470, SN74ABT16470

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS085E – FEBRUARY 1991 – REVISED MAY 1997

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE†

INPUTS

OUTPUT

CLKENAB

CLKAB

OEAB

A

B

H

X

X

X

Z

X

X

H

X

Z

L

L

L

X

B0‡

L

L

L

L

L

L

H

H

† A-to-B data flow is shown: B-to-A flow is similar but uses

CLKENBA, CLKBA, and OEBA.

‡ Output level before the indicated steady-state input

conditions were established

background image

SN54ABT16470, SN74ABT16470

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS085E – FEBRUARY 1991 – REVISED MAY 1997

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1OEBA

1CLKENBA

1OEAB

1CLKENAB

2OEBA

2CLKENBA

2OEAB

2CLKENAB

2

1CLKAB

2C6

1A1

5

6D

1A2

6

1A3

8

1A4

9

1A5

10

1A6

12

1A7

13

1A8

14

1B1

52

5D

1B2

51

1B3

49

1B4

48

1B5

47

1B6

45

1B7

44

1B8

43

2EN4

1

G2

3

30

2CLKBA

7C11

7EN9

29

G7

31

27

2CLKAB

8C12

8EN10

28

G8

26

55

1CLKBA

1C5

1EN3

56

G1

54

2A1

15

12D

2A2

16

2A3

17

2A4

19

2A5

20

2A6

21

2A7

23

2A8

24

2B1

42

11D

2B2

41

2B3

40

2B4

38

2B5

37

2B6

36

2B7

34

2B8

33

1

1

1

1

10

4

background image

SN54ABT16470, SN74ABT16470

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS085E – FEBRUARY 1991 – REVISED MAY 1997

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

C1

1D

1D

C1

56

54

55

1

3

2

5

52

To Seven Other Channels

C1

1D

1D

C1

29

31

30

28

26

27

15

42

To Seven Other Channels

1B1

1OEBA

1CLKENBA

1CLKBA

1OEAB

1CLKENAB

1CLKAB

1A1

2B1

2OEBA

2CLKENBA

2CLKBA

2OEAB

2CLKENAB

2CLKAB

2A1

background image

SN54ABT16470, SN74ABT16470

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS085E – FEBRUARY 1991 – REVISED MAY 1997

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (except I/O ports) (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high or power-off state, V

O

 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . 

Current into any output in the low state, I

O

: SN54ABT16470 96 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ABT16470 128 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): DGG package 

81

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

74

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

recommended operating conditions (see Note 3)

SN54ABT16470

SN74ABT16470

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High-level output current

–24

–32

mA

IOL

Low-level output current

48

64

mA

t/

v

Input transition rise or fall rate

Outputs enabled

10

10

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABT16470, SN74ABT16470

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS085E – FEBRUARY 1991 – REVISED MAY 1997

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABT16470

SN74ABT16470

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

–1.2

–1.2

V

VCC = 4.5 V,

IOH = –3 mA

2.5

2.5

2.5

VOH

VCC = 5 V,

IOH = –3 mA

3

3

3

V

VOH

VCC = 4 5 V

IOH = –24 mA

2

2

V

VCC = 4.5 V

IOH = –32 mA

2*

2

VOL

VCC = 4 5 V

IOL = 48 mA

0.55

0.55

V

VOL

VCC = 4.5 V

IOL = 64 mA

0.55*

0.55

V

Vhys

100

mV

II

Control inputs

VCC = 5 5 V

VI = VCC or GND

±

1

±

1

±

1

µ

A

II

A or B ports

VCC = 5.5 V,

VI = VCC or GND

±

100

±

100

±

100

µ

A

IOZH‡

VCC = 5.5 V,

VO = 2.7 V

50

50

50

µ

A

IOZL‡

VCC = 5.5 V,

VO = 0.5 V

–50

–50

–50

µ

A

Ioff

VCC = 0,

VI or VO 

 4.5 V

±

100

±

100

µ

A

ICEX

VCC = 5.5 V,

VO = 5.5 V

Outputs high

50

50

50

µ

A

IO§

VCC = 5.5 V,

VO = 2.5 V

–50

–100

–200

–50

–200

–50

–200

mA

VCC = 5.5 V,

Outputs high

2

2

2

ICC

A or B ports

VCC = 5.5 V,

IO = 0,

Outputs low

35

35

35

mA

VI = VCC or GND

Outputs disabled

2

2

2

ICC¶

VCC = 5.5 V, One input at 3.4 V,

Other inputs at VCC or GND

0.5

0.5

0.5

mA

Ci

Control inputs

VI = 2.5 V or 0.5 V

3

pF

Cio

A or B ports

VO = 2.5 V or 0.5 V

8.5

pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.

† All typical values are at VCC = 5 V.

‡ The parameters IOZH and IOZL include the input leakage current.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 1)

VCC = 5 V,

SN54ABT16470

SN74ABT16470

CC

,

TA = 25

°

C

SN54ABT16470

SN74ABT16470

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

150

0

150

0

150

MHz

tw#

Pulse duration, CLKAB or CLKBA high or low

3.3

3.3

3.3

ns

tsu

Setup time, data before CLKAB

 or CLKBA

4

4

4

ns

th

Hold time, data after CLKAB

 or CLKBA

1

1

1

ns

# This parameter is characterized, but not production tested.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABT16470, SN74ABT16470

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS085E – FEBRUARY 1991 – REVISED MAY 1997

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

SN54ABT16470

SN74ABT16470

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fmax

150

150

150

MHz

tPLH

CLK

A or B

1.4

3.1

4.8

1.4

5.1

1.4

4.9

ns

tPHL

CLK

A or B

1.3

3.2

4.6

1.3

5.1

1.3

4.9

ns

tPZH

OE

A or B

1

3.1

4.3

1

5

1

4.9

ns

tPZL

OE

A or B

1.2

3.6

5.8

1.2

6.9

1.2

6.8

ns

tPHZ

OE

A or B

1.9

3.7

4.9

1.9

6

1.9

5.5

ns

tPLZ

OE

A or B

1.6

3.3

4.8

1.6

5.4

1.6

5.3

ns

tPZH

CLKEN

A or B

1

3.4

4.6

1

5.8

1

5.7

ns

tPZL

CLKEN

A or B

1.2

3.9

6

1.2

7.3

1.2

7.2

ns

tPHZ

CLKEN

A or B

1.7

3.9

5.2

1.7

6.2

1.7

5.8

ns

tPLZ

CLKEN

A or B

1.5

3.6

5.3

1.5

5.5

1.5

5.4

ns

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABT16470, SN74ABT16470

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS085E – FEBRUARY 1991 – REVISED MAY 1997

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

th

tsu

From Output

 Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1998, Texas Instruments Incorporated