background image

 

SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

State-of-the-Art 

EPIC-

ΙΙ

B

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

D

Typical V

OLP

 (Output Ground Bounce)

< 1 V at V

CC

 = 5 V, T

A

 = 25

°

C

D

High-Drive Outputs (–32-mA I

OH

, 64-mA I

OL

)

D

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Package, and Plastic (NT)

and Ceramic (JT) DIPs

description

These devices consist of bus-transceiver circuits,

D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the

data bus or from the internal storage registers.

Output-enable (OEAB and OEBA) inputs are

provided to control the transceiver functions.

Select-control (SAB and SBA) inputs are provided

to select either real-time or stored data for

transfer. The circuitry used for select control

eliminates the typical decoding glitch that occurs

in a multiplexer during the transition between

stored and real-time data. A low input selects

real-time data, and a high input selects stored

data. Figure 1 illustrates the four fundamental

bus-management functions that can be

performed with the ’ABT652A.

Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions

at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control inputs. When SAB

and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops

by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all

other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last

state.

To ensure the high-impedance state during power up or power down, OEBA should be tied to V

CC

 through a

pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver

(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is

determined by the current-sourcing capability of the driver (A to B).

Copyright 

©

 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-

ΙΙ

B is a trademark of Texas Instruments Incorporated.

SN54ABT652A . . . JT OR W PACKAGE

SN74ABT652A . . . DB, DW, NT, OR PW PACKAGE

(TOP VIEW)

SN54ABT652A . . . FK PACKAGE

(TOP VIEW)

3 2 1 28 27

12 13

5

6

7

8

9

10

11

25

24

23

22

21

20

19

OEBA

B1

B2

NC

B3

B4

B5

A1

A2

A2

NC

A4

A5

A6

4

26

14 15 16 17 18

A7

A8

GND

NC

B8

B7

B6

OEAB

SAB

CLKAB

NC

CLKBA

SBA

 

V

CC

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CLKAB

SAB

OEAB

A1

A2

A3

A4

A5

A6

A7

A8

GND

V

CC

CLKBA

SBA

OEBA

B1

B2

B3

B4

B5

B6

B7

B8

NC – No internal connection

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SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

description (continued)

The SN54ABT652A is characterized for operation over the full military temperature range of –55

°

C to 125

°

C.

The SN74ABT652A is characterized for operation from –40

°

C to 85

°

C.

FUNCTION TABLE

INPUTS

DATA I/O†

OPERATION OR FUNCTION

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1–A8

B1–B8

OPERATION OR FUNCTION

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

X

X

Input

Input

Store A and B data

X

H

H or L

X

X

Input

Unspecified‡

Store A, hold B

H

H

X‡

X

Input

Output

Store A in both registers

L

X

H or L

X

X

Unspecified‡

Input

Hold A, store B

L

L

X

X‡

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

H or L

X

H

X

Input

Output

Stored A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus and

stored B data to A bus

† The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always

enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡ Select control = L; clocks can occur simultaneously.

Select control = H; clocks must be staggered to load both registers.

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SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OEAB

X

L

L

OEAB

L

L

CLKAB

X

CLKBA

X

SAB

X

SBA

L

CLKAB

X

CLKBA

X

SAB

L

SBA

X

H

CLKAB CLKBA

X

SAB

X

SBA

X

CLKAB

CLKBA

SAB

SBA

X

H

X

X

X

X

X

H

L

H or L

H

H

OEBA

OEBA

H

H

OEAB OEBA

OEAB

OEBA

H or L

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

3

21

1

23

2

22

1

23

2

22

3

21

3

21

23

2

22

3

21

1

2

22

1

23

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

Figure 1. Bus-Management Functions

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SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

OEBA

EN1 [BA]

21

G5

22

SBA

A1

4

B1

20

4D

EN2 [AB]

3

OEAB

23

CLKBA

1

CLKAB

G7

2

SAB

5

7

7

5

6D

1

1

2

C6

C4

A2

5

B2

19

A3

6

B3

18

A4

7

B4

17

A5

8

B5

16

A6

9

B6

15

A7

10

B7

14

A8

11

B8

13

1

1

1

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SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

OEBA

A1

B1

1D

C1

1D

C1

One of Eight Channels

SAB

CLKAB

SBA

CLKBA

OEAB

To Seven Other Channels

21

3

23

22

1

2

4

20

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SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (except I/O ports) (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high or power-off state, V

O

 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . 

Current into any output in the low state, I

O

: SN54ABT652A 96 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ABT652A

128 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK 

(V

< 0) 

–18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK 

(V

< 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): DB package 

104

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DW package 

81

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

NT package 

67

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

PW package 

120

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,

which use a trace length of zero.

recommended operating conditions (see Note 3)

SN54ABT652A

SN74ABT652A

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High-level output current

–24

–32

mA

IOL

Low-level output current

48

64

mA

t/

v

Input transition rise or fall rate

Outputs enabled

5

5

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.

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SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABT652A

SN74ABT652A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

–1.2

–1.2

V

VCC = 4.5 V,

IOH = –3 mA

2.5

2.5

2.5

VOH

VCC = 5 V,

IOH = –3 mA

3

3

3

V

VOH

VCC = 4 5 V

IOH = –24 mA

2

2

V

VCC = 4.5 V

IOH = –32 mA

2*

2

VOL

VCC = 4 5 V

IOL = 48 mA

0.55

0.55

V

VOL

VCC = 4.5 V

IOL = 64 mA

0.55*

0.55

V

Vhys

100

mV

II

Control inputs

VCC = 5 5 V

VI = VCC or GND

±

1

±

1

±

1

µ

A

II

A or B ports

VCC = 5.5 V,

VI = VCC or GND

±

100

±

100

±

100

µ

A

IOZH‡

VCC = 5.5 V,

VO = 2.7 V

50**

10

50

µ

A

IOZL‡

VCC = 5.5 V,

VO = 0.5 V

–50**

–10

–50

µ

A

Ioff

VCC = 0,

VI or VO 

 4.5 V

±

100

±

100

µ

A

ICEX

VCC = 5.5 V,

VO = 5.5 V

Outputs high

50

50

50

µ

A

IO§

VCC = 5.5 V,

VO = 2.5 V

–50

–100

–180

–50

–180

–50

–180

mA

VCC = 5.5 V,

Outputs high

250

250

250

µ

A

ICC

VCC = 5.5 V,

IO = 0,

Outputs low

30

30

30

mA

VI = VCC or GND

Outputs disabled

250

250

250

µ

A

ICC¶

VCC = 5.5 V, One input at 3.4 V,

Other inputs at VCC or GND

1.5

1.5

1.5

mA

Ci

Control inputs

VI = 2.5 V or 0.5 V

7

pF

Cio

A or B ports

VO = 2.5 V or 0.5 V

12

pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.

** These limits apply only to the SN74ABT652A.

† All typical values are at VCC = 5 V.

‡ The parameters IOZH and IOZL include the input leakage current.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

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SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 2)

SN54ABT652A

VCC = 5 V,

TA = 25

°

C

MIN

MAX

UNIT

MIN

MAX

fclock

Clock frequency

0

125

0

125

MHz

tw

Pulse duration, CLK high or low

4

4

ns

tsu

Setup time, A or B before CLKAB

 or CLKBA

3

3.5

ns

th

Hold time, A or B after CLKAB

 or CLKBA

1.5

1.5

ns

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 2)

SN74ABT652A

VCC = 5 V,

TA = 25

°

C

MIN

MAX

UNIT

MIN

MAX

fclock

Clock frequency

0

125

0

125

MHz

tw

Pulse duration, CLK high or low

4

4

ns

tsu

Setup time, A or B before CLKAB

 or CLKBA

3

3

ns

th

Hold time, A or B after CLKAB

 or CLKBA

0

0

ns

background image

SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 2)

SN54ABT652A

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

MIN

MAX

UNIT

MIN

TYP

MAX

fmax

125

200

125

MHz

tPLH

CLK

B or A

2.2

4

5.1

1.7

5.9

ns

tPHL

CLK

B or A

1.7

4

5.1

1.7

5.9

ns

tPLH

A or B

B or A

1.5

3

4.8

1

5

ns

tPHL

A or B

B or A

1.5

3.3

4.6

1

5.6

ns

tPLH

SAB or SBA†

B or A

1.5

4

5.5

1.5

6.8

ns

tPHL

SAB or SBA†

B or A

1.5

3.6

4.9

1.5

6.2

ns

tPZH

OEBA

A

2

3.6

5.4

2

6.8

ns

tPZL

OEBA

A

3

5.7

7.7

3

9.2

ns

tPHZ

OEBA

A

1.5

3.2

5.8

1

7.5

ns

tPLZ

OEBA

A

1.5

3

4.3

1

4.6

ns

tPZH

OEAB

B

2

4.3

6.1

2

7.8

ns

tPZL

OEAB

B

3

5.5

7.4

3

8.9

ns

tPHZ

OEAB

B

1.5

3.3

6

1

8

ns

tPLZ

OEAB

B

1.5

3.4

5

1.5

6.8

ns

† These parameters are measured with the internal output state of the storage register opposite that of the bus input.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 2)

SN74ABT652A

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

MIN

MAX

UNIT

MIN

TYP

MAX

fmax

125

200

125

MHz

tPLH

CLK

B or A

2.2

4

5.1

2.2

5.6

ns

tPHL

CLK

B or A

1.7

4

5.1

1.7

5.6

ns

tPLH

A or B

B or A

1.5

3

4.3

1.5

4.8

ns

tPHL

A or B

B or A

1.5

3.3

4.6

1.5

5.4

ns

tPLH

SAB or SBA†

B or A

1.5

4

5.1

1.5

6.5

ns

tPHL

SAB or SBA†

B or A

1.5

3.6

4.9

1.5

5.9

ns

tPZH

OEBA

A

2

3.6

4.6

2

5.8

ns

tPZL

OEBA

A

3

5.7

6.8

3

8.5

ns

tPHZ

OEBA

A

1.5

3.2

4.5

1.5

5

ns

tPLZ

OEBA

A

1.5

3

3.8

1.5

4.1

ns

tPZH

OEAB

B

2

4.3

6.1

2

6.5

ns

tPZL

OEAB

B

3

5.5

6.5

3

7.4

ns

tPHZ

OEAB

B

1.5

3.3

4.5

1.5

5.5

ns

tPLZ

OEAB

B

1.5

3.4

4.4

1.5

5.1

ns

† These parameters are measured with the internal output state of the storage register opposite that of the bus input.

background image

SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

 

SCBS072F – JANUARY 1991 – REVISED MAY 1997

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

th

tsu

From Output

 Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

Figure 2. Load Circuit and Voltage Waveforms

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