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SN74LVCZ16240A

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES276B – JUNE 1999 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

Typical V

OLP

 (Output Ground Bounce)

<0.8 V at V

CC

 = 3.3 V, T

A

 = 25

°

C

D

Typical V

OHV

 (Output V

OH

 Undershoot)

>2 V at V

CC

 = 3.3 V, T

A

 = 25

°

C

D

I

off

 and Power-Up 3-State Support Hot

Insertion

D

Supports Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

CC

)

D

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D

ESD Protection Exceeds JESD 22

–  2000-V Human-Body Model (A114-A)

–  200-V Machine Model (A115-A)

–  1000-V Charged-Device Model (C101)

D

Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

description

This 16-bit buffer/driver is designed for 3-V to

3.6-V V

CC

 operation.

The SN74LVCZ16240A is designed specifically to improve both the performance and density of 3-state memory

address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides inverting

outputs and symmetrical active-low output-enable (OE) inputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

When V

CC

 is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to V

CC

 through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using I

off

 and power-up 3-state. The I

off

 circuitry

disables the outputs, preventing damaging current backflow through the device when it is powered down. The

power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

The SN74LVCZ16240A is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 2000, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC and Widebus are trademarks of Texas Instruments.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1OE

1Y1

1Y2

GND

1Y3

1Y4

V

CC

2Y1

2Y2

GND

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

V

CC

4Y1

4Y2

GND

4Y3

4Y4

4OE

2OE

1A1

1A2

GND

1A3

1A4

V

CC

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

V

CC

4A1

4A2

GND

4A3

4A4

3OE

DGG OR DL PACKAGE

(TOP VIEW)

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SN74LVCZ16240A

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES276B – JUNE 1999 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

(each 4-bit buffer)

INPUTS

OUTPUT

OE

A

Y

L

H

L

L

L

H

H

X

Z

logic symbol

47

1A1

46

1A2

44

1A3

43

1A4

1Y1

2

1Y2

3

1Y3

5

1Y4

6

41

2A1

40

2A2

38

2A3

37

2A4

2Y1

8

2Y2

9

2Y3

11

2Y4

12

36

3A1

35

3A2

33

3A3

32

3A4

3Y1

13

3Y2

14

3Y3

16

3Y4

17

30

4A1

29

4A2

27

4A3

26

4A4

4Y1

19

4Y2

20

4Y3

22

4Y4

23

EN1

1

EN4

24

1OE

2OE

3OE

4OE

EN2

48

EN3

25

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1

1

1

2

1

3

1

4

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SN74LVCZ16240A

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES276B – JUNE 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

1OE

1A1

1A2

1A3

1A4

1Y1

1Y2

1Y3

1Y4

1

47

46

44

43

2

3

5

6

2OE

2A1

2A2

2A3

2A4

2Y1

2Y2

2Y3

2Y4

48

41

40

38

37

8

9

11

12

3OE

3A1

3A2

3A3

3A4

3Y1

3Y2

3Y3

3Y4

25

36

35

33

32

13

14

16

17

4OE

4A1

4A2

4A3

4A4

4Y1

4Y2

4Y3

4Y4

24

30

29

27

26

19

20

22

23

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1) 

–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high or low state, V

O

(see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through each V

CC

 or GND 

±

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 3): DGG package 

70

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

63

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51.

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SN74LVCZ16240A

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES276B – JUNE 1999 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

3

3.6

V

VIH

High-level input voltage

VCC = 3 V to 3.6 V

2

V

VIL

Low-level input voltage

VCC = 3 V to 3.6 V

0.8

V

VI

Input voltage

0

5.5

V

VO

Output voltage

High or low state

0

VCC

V

VO

Output voltage

3-state

0

5.5

V

IOH

High-level output current

VCC = 3 V

–24

mA

IOL

Low-level output current

VCC = 3 V

24

mA

t/

v

Input transition rise or fall rate

10

ns/V

t/

VCC

Power-up ramp rate

150

µ

s/V

TA

Operating free-air temperature

–40

85

°

C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

IOH = –100 

µ

A

3 V to 3.6 V

VCC–0.2

VOH

IOH = –12 mA

3 V

2.4

V

IOH = –24 mA

3 V

2.2

IOL = 100 

µ

A

3 V to 3.6 V

0.2

VOL

IOL = 12 mA

3 V

0.4

V

IOL = 24 mA

3 V

0.55

II

VI = 0 to 5.5 V

3.6 V

±

5

µ

A

Ioff

VI or VO = 5.5 V

0

±

5

µ

A

IOZ

VO = 0 to 5.5 V

3.6 V

±

5

µ

A

IOZPU

VO = 0.5 to 2.5 V,

OE = don’t care

0 to 1.5 V

±

5

µ

A

IOZPD

VO = 0.5 to 2.5 V,

OE = don’t care

1.5 V to 0

±

5

µ

A

ICC

VI = VCC or GND

IO = 0

3 6 V

100

µ

A

ICC

3.6 V 

VI 

 5.5 V‡

IO = 0

3.6 V

100

µ

A

ICC

One input at VCC – 0.6 V,

Other inputs at VCC or GND

3 V to 3.6 V

100

µ

A

Ci

VI = VCC or GND

3.3 V

4.5

pF

Co

VO = VCC or GND

3.3 V

6

pF

† All typical values are at VCC = 3.3 V, TA = 25

°

C.

‡ This applies in the disabled state only.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

±

 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

tpd

A or B

B or A

1

4.2

ns

ten

OE

A or B

1.5

4.7

ns

tdis

OE

A or B

1.5

5.9

ns

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SN74LVCZ16240A

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES276B – JUNE 1999 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

operating characteristics, T

= 25

°

C

PARAMETER

TEST

CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per buffer/driver

Outputs enabled

f = 10 MHz

31

pF

Cpd

Power dissipation capacitance per buffer/driver

Outputs disabled

f = 10 MHz

3.5

pF

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SN74LVCZ16240A

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

 

SCES276B – JUNE 1999 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 3.3 V 

±

 0.3 V

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

×

 VCC

Open

GND

500 

500 

tPLH

tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

VCC

0 V

VOH

VOL

0 V

VOL + 0.3 V

VOH – 0.3 V

0 V

VCC

0 V

0 V

VCC

0 V

tw

Input

VCC

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

 2 ns, tf 

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

Figure 1. Load Circuit and Voltage Waveforms

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

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Copyright 

©

 2000, Texas Instruments Incorporated