background image

 

SN54ABT16540, SN74ABT16540A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

 

SCBS208C – FEBRUARY 1991 – REVISED APRIL 1997

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

State-of-the-Art 

EPIC-

ΙΙ

B

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

D

Typical V

OLP

 (Output Ground Bounce)

< 1 V at V

CC

 = 5 V, T

A

 = 25

°

C

D

Distributed V

CC

 and GND Pin Configuration

Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB

Layout

D

High-Drive Outputs (–32-mA I

OH

, 64-mA I

OL

)

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages, and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The SN54ABT16540 and SN74ABT16540A are

inverting 16-bit buffers/drivers composed of two

8-bit sections with separate output-enable gates.

These buffers and bus drivers provide a

high-performance bus interface for wide data

paths.

The 3-state control gate is a 2-input AND gate with

active-low inputs so that if either output-enable

(OE1 or OE2) input is high, all corresponding

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V

CC

 through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16540 is characterized for operation over the full military temperature range of –55

°

C to 125

°

C.

The SN74ABT16540A is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-

ΙΙ

B are trademarks of Texas Instruments Incorporated.

SN54ABT16540 . . . WD PACKAGE

SN74ABT16540A . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1OE1

1Y1

1Y2

GND

1Y3

1Y4

V

CC

1Y5

1Y6

GND

1Y7

1Y8

2Y1

2Y2

GND

2Y3

2Y4

V

CC

2Y5

2Y6

GND

2Y7

2Y8

2OE1

1OE2

1A1

1A2

GND

1A3

1A4

V

CC

1A5

1A6

GND

1A7

1A8

2A1

2A2

GND

2A3

2A4

V

CC

2A5

2A6

GND

2A7

2A8

2OE2

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SN54ABT16540, SN74ABT16540A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

 

SCBS208C – FEBRUARY 1991 – REVISED APRIL 1997

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

(each 8-bit section)

INPUTS

OUTPUT

OE1

OE2

A

Y

L

L

L

H

L

L

H

L

H

X

X

Z

X

H

X

Z

logic symbol

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

47

1A1

1

1Y1

2

48

46

1A2

1Y2

3

24

25

44

1A3

1Y3

5

43

1A4

1Y4

6

41

1A5

1Y5

8

40

1A6

1Y6

9

38

1A7

1Y7

11

37

1A8

1Y8

12

36

2A1

2Y1

13

35

2A2

2Y2

14

33

2A3

2Y3

16

32

2A4

2Y4

17

30

2A5

2Y5

19

29

2A6

2Y6

20

27

2A7

2Y7

22

26

2A8

2Y8

23

1OE1

1OE2

2OE1

2OE2

&

&

1

1

1

2

EN1

EN2

logic diagram (positive logic)

1OE1

1OE2

2OE1

2OE2

1A1

1Y1

2Y1

2A1

To Seven Other Channels

To Seven Other Channels

1

48

47

24

25

36

2

13

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SN54ABT16540, SN74ABT16540A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

 

SCBS208C – FEBRUARY 1991 – REVISED APRIL 1997

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high or power-off state, V

O

 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . 

Current into any output in the low state, I

O

: SN54ABT16540 96 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ABT16540A 128 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): DGG package 

89

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DGV package 

93

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

94

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

recommended operating conditions (see Note 3)

SN54ABT16540

SN74ABT16540A

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High-level output current

–24

–32

mA

IOL

Low-level output current

48

64

mA

t/

v

Input transition rise or fall rate

Outputs enabled

10

10

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABT16540, SN74ABT16540A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

 

SCBS208C – FEBRUARY 1991 – REVISED APRIL 1997

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABT16540

SN74ABT16540A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

–1.2

–1.2

V

VCC = 4.5 V,

IOH = –3 mA

2.5

2.5

2.5

VOH

VCC = 5 V,

IOH = –3 mA

3

3

3

V

VOH

VCC = 4 5 V

IOH = –24 mA

2

2

V

VCC = 4.5 V

IOH = –32 mA

2*

2

VOL

VCC = 4 5 V

IOL = 48 mA

0.55

0.55

V

VOL

VCC = 4.5 V

IOL = 64 mA

0.55*

0.55

V

Vhys

100

mV

II

VCC = 5.5 V,

VI = VCC or GND

±

1

±

1

±

1

µ

A

IOZH

VCC = 5.5 V,

VO = 2.7 V

10

50

10

µ

A

IOZL

VCC = 5.5 V,

VO = 0.5 V

–10

–50

–10

µ

A

Ioff

VCC = 0,

VI or VO 

 4.5 V

±

100

±

100

µ

A

ICEX

VCC = 5.5 V,

VO = 5.5 V

Outputs high

50

50

50

µ

A

IO‡

VCC = 5.5 V,

VO = 2.5 V

–50

–100

–180

–50

–180

–50

–180

mA

VCC = 5.5 V,

Outputs high

3

2

3

ICC

VCC = 5.5 V,

IO = 0,

Outputs low

34

32

34

mA

VI = VCC or GND

Outputs disabled

3

2

3

§

Data

VCC = 5.5 V,

One input at 3.4 V,

Outputs enabled

1

1

1

ICC§

inputs

,

Other inputs at

VCC or GND

Outputs disabled

0.05

0.05

0.05

mA

Control

inputs

VCC = 5.5 V, One input at 3.4 V,

Other inputs at VCC or GND

1.5

1.5

1.5

Ci

VI = 2.5 V or 0.5 V

3.5

pF

Co

VO = 2.5 V or 0.5 V

7.5

pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.

† All typical values are at VCC = 5 V.

‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

SN54ABT16540

SN74ABT16540A

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

tPLH

A

Y

1

2.3

3.3

1

4.2

1

4.1

ns

tPHL

A

Y

1.1

2.5

4.1

1.1

4.4

1.1

4.3

ns

tPZH

OE

Y

1.1

3.1

4.2

1.1

5.2

1.1

5.1

ns

tPZL

OE

Y

1.6

3.7

4.8

1.6

6

1.6

5.9

ns

tPHZ

OE

Y

1.6

4

5

1.6

5.4

1.6

5.7

ns

tPLZ

OE

Y

1.4

3.2

4.4

1.4

4.7

1.4

4.7

ns

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54ABT16540, SN74ABT16540A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

 

SCBS208C – FEBRUARY 1991 – REVISED APRIL 1997

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

th

tsu

From Output

 Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

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Copyright 

©

 1998, Texas Instruments Incorporated