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SN54HC125, SN74HC125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

 

SCLS104B – MARCH 1984 – REVISED MAY 1997

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

High-Current 3-State Outputs Interface

Directly With System Bus or Can Drive up

to 15 LSTTL Loads

D

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), and Ceramic Flat (W) Packages,

Ceramic Chip Carriers (FK), and Standard

Plastic (N) and Ceramic (J) 300-mil DIPs

description

These quadruple bus buffer gates feature

independent line drivers with 3-state outputs.

Each output is disabled when the associated

output-enable (OE) input is high.

The SN54HC125 is characterized for operation

over the full military temperature range of –55

°

C

to 125

°

C. The SN74HC125 is characterized for

operation from –40

°

C to 85

°

C.

FUNCTION TABLE

 (each 

buffer)

INPUTS

OUTPUT

OE

A

Y

L

H

H

L

L

L

H

X

Z

logic symbol

EN

1

2

1A

1Y

3

4

5

2A

2Y

6

10

9

3A

3Y

8

13

12

4A

4Y

11

1OE

2OE

3OE

4OE

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, N, and W packages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

V

CC

4OE

4A

4Y

3OE

3A

3Y

SN54HC125 . . . J  OR  W  PACKAGE

SN74HC125 . . . D, DB, OR N PACKAGE

(TOP VIEW)

3

2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3OE

1Y

NC

2OE

NC

2A

1A

1OE

NC

3Y

3A

V

4OE

2Y

GND

NC

SN54HC125 . . . FK PACKAGE

(TOP VIEW)

CC

NC – No internal connection

 

Copyright 

©

 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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SN54HC125, SN74HC125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

 

SCLS104B – MARCH 1984 – REVISED MAY 1997

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

1

1OE

2

1A

1Y

3

4

2OE

5

2A

2Y

6

10

3OE

9

3A

3Y

8

13

4OE

12

4A

4Y

11

Pin numbers shown are for the D, DB, J, N, and W packages.

absolute maximum ratings over operating free-air temperature range

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0 or V

I

 > V

CC

) (see Note 1) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0 or V

O

 > V

CC

) (see Note 1) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 (V

O

 = 0 to V

CC

±

35 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

±

70 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): D package 

127

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DB package 

158

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

N package 

78

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace

length of zero.

recommended operating conditions

SN54HC125

SN74HC125

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

2

5

6

2

5

6

V

VCC = 2 V

1.5

1.5

VIH

High-level input voltage

VCC = 4.5 V

3.15

3.15

V

VCC = 6 V

4.2

4.2

VCC = 2 V

0

0.5

0

0.5

VIL

Low-level input voltage

VCC = 4.5 V

0

1.35

0

1.35

V

VCC = 6 V

0

1.8

0

1.8

VI

Input voltage

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

V

VCC = 2 V

0

1000

0

1000

tt

Input transition (rise and fall) time

VCC = 4.5 V

0

500

0

500

ns

VCC = 6 V

0

400

0

400

TA

Operating free-air temperature

–55

125

–40

85

°

C

background image

SN54HC125, SN74HC125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

 

SCLS104B – MARCH 1984 – REVISED MAY 1997

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25

°

C

SN54HC125

SN74HC125

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

1.9

1.998

1.9

1.9

IOH = –20 

µ

A

4.5 V

4.4

4.499

4.4

4.4

VOH

VI = VIH or VIL

6 V

5.9

5.999

5.9

5.9

V

IOH = –6 mA

4.5 V

3.98

4.3

3.7

3.84

IOH = –7.8 mA

6 V

5.48

5.8

5.2

5.34

2 V

0.002

0.1

0.1

0.1

IOL = 20 

µ

A

4.5 V

0.001

0.1

0.1

0.1

VOL

VI = VIH or VIL

6 V

0.001

0.1

0.1

0.1

V

IOL = 6 mA

4.5 V

0.17

0.26

0.4

0.33

IOL = 7.8 mA

6 V

0.15

0.26

0.4

0.33

II

VI = VCC or 0

6 V

±

0.1

±

100

±

1000

±

1000

nA

IOZ

VO = VCC or 0

6 V

±

0.01

±

0.5

±

10

±

5

µ

A

ICC

VI = VCC or 0,

IO = 0

6 V

8

160

80

µ

A

Ci

2 V to 6 V

3

10

10

10

pF

switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25

°

C

SN54HC125

SN74HC125

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

48

120

150

150

tpd

A

Y

4.5 V

14

24

36

30

ns

6 V

11

20

25

26

2 V

53

120

180

150

ten

OE

Y

4.5 V

14

24

36

30

ns

6 V

11

20

31

26

2 V

30

120

180

150

tdis

OE

Y

4.5 V

15

24

36

30

ns

6 V

14

20

31

26

2 V

28

60

90

75

tt

Any

4.5 V

8

12

18

15

ns

6 V

6

10

15

13

background image

SN54HC125, SN74HC125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

 

SCLS104B – MARCH 1984 – REVISED MAY 1997

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, C

L

 = 150 pF

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25

°

C

SN54HC125

SN74HC125

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

67

150

225

190

tpd

A

Y

4.5 V

19

30

45

38

ns

6 V

15

25

39

32

2 V

100

135

200

170

ten

OE

Y

4.5 V

20

27

40

34

ns

6 V

17

23

34

29

2 V

45

210

315

265

tt

Any

4.5 V

17

42

63

53

ns

6 V

13

36

53

45

operating characteristics, T

A

 = 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per gate

No load

45

pF

background image

SN54HC125, SN74HC125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

 

SCLS104B – MARCH 1984 – REVISED MAY 1997

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

50%

50%

10%

10%

90%

90%

VCC

0 V

tr

tf

Input

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

50%

50%

50%

10%

10%

90%

90%

VCC

VOH

VOL

0 V

tr

tf

Input

In-Phase

Output

50%

tPLH

tPHL

50%

50%

10%

10%

90%

90%

VOH

VOL

tr

tf

tPHL

tPLH

Out-of-Phase

Output

50%

10%

90%

VCC

VCC

VOL

0 V

Output

Control

(Low-Level

Enabling)

Output

Waveform 1

(See Note B)

50%

tPZL

tPLZ

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

VOH

0 V

50%

50%

tPZH

tPHZ

Output

Waveform 2

(See Note B)

VCC

Test

Point

From Output

Under Test

CL

(see Note A)

RL

VCC

S1

S2

LOAD CIRCUIT

PARAMETER

CL

tPZH

tpd or tt

tdis

ten

tPZL

tPHZ

tPLZ

1 k

1 k

50 pF

or

150 pF

50 pF

Open

Closed

RL

S1

Closed

Open

S2

Open

Closed

Closed

Open

50 pF

or

150 pF

Open

Open

––

NOTES: A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR 

 1 MHz, ZO = 50 

, tr = 6 ns, tf = 6 ns.

D. The outputs are measured one at a time with one input transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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Copyright 

©

 1998, Texas Instruments Incorporated