background image

CMOS I²C 2-WIRE BUS

8K ELECTRICALLY ERASABLE PROGRAMMABLE ROM

1K X 8 BIT EEPROM

Turbo IC, Inc.

24C08

1

2

3

4

5

6

7

8

NC

NC

A2

GND

VCC

NC

SCL

SDA

8 pin PDIP

1

2

3

4

5

6

7

8

NC

NC

A2

GND

VCC

NC

SCL

SDA

8 pin SOIC

PIN DESCRIPTION

DESCRIPTION:

The Turbo IC 24C08 is a serial 8K EEPROM fabricated with

Turbo’s proprietary, high reliability, high performance CMOS

technology. It’s 8K of memory is organized as 1,024 x 8 bits.

The memory is configured as 64 pages with each page con-

taining 16 bytes. This device offers significant advantages

in low power and low voltage applications.

The Turbo IC 24C08 uses the I²C addressing protocol and

2-wire serial interface which includes a bidirectional serial

data bus synchronized by a clock. It offers a flexible byte

write and a faster 16-byte page write.

The Turbo IC 24C08 is assembled in either a 8-pin PDIP or

8-pin SOIC package. Pin #1, #2 and #7 are not connected

(NC). Pin #3 is the A2 device address input for the 24C08,

such that a total of two 24C08 devices can be connected on

a single bus. Pin #4 is the ground (Vss). Pin #5 is the serial

data (SDA) pin used for bidirectional transfer of data. Pin #6

is the serial clock (SCL) input pin. Pin #8 is the power sup-

ply (Vcc) pin.

All data is serially transmitted in bytes (8 bits) on the SDA

bus. To access the Turbo IC 24C08 (slave) for a read or

write operation, the controller (master) issues a start condi-

tion by pulling SDA from high to low while SCL is high. The

master then issues the device address byte which consists

of 1010 (A2) (B9) (B8) (R/W). The most significant bits (1010)

are a device type code signifying an EEPROM device. A2 is

the device address select bit which has to match the A2 pin

input on the 24C08 device. The B[9:8] bits are the 2 most

significant bits of the memory address. The read/write bit

determines whether to do a read or write operation. After

each byte is transmitted, the receiver has to provide an ac-

knowledge by pulling the SDA bus low on the ninth clock

cycle. The acknowledge is a handshake signal to the trans-

mitter indicating a successful data transmission.

FEATURES :

• Extended Power Supply Voltage

Single Vcc for Read and Programming

(Vcc = 2.7 V to 5.5 V)

• Low Power  (Isb = 2µa @ 5.5 V)

• I²C Bus, 2-Wire Serial Interface

• Support Byte Write and Page Write (16 Bytes)

• Automatic Page write Operation (maximum 10 ms)

Internal Control Timer

Internal Data Latches for 16 Bytes

• High Reliability CMOS Technology with EEPROM Cell

Endurance : 1,000,000 Cycles

Data Retention : 100 Y

ears

1

SERIAL CLOCK (SCL)

 The SCL input synchronizes the data on the SDA

bus. It is used in conjunction with SDA to define

the start and stop conditions. It is also used in

conjunction with SDA to transfer data to and from

the Turbo IC 24C08.

SERIAL DATA (SDA)

SDA  is a bidirectional pin used to transfer data

in and out of the Turbo IC 24C08. The pin is an

open-drain output. A pullup resistor must be con-

nected from SDA to Vcc.

PIN DESCRIPTION

DEVICE ADDRESS (A2)

A2 is a device address input that enables a total

of two 24C08 devices to connect on a single bus.

When the address input pin is left unconnected,

it is interpreted as zero.

background image

24C08

Turbo IC, Inc.

Note: The write cycle time t

WC 

is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.

DESCRIPTION (Continued):

For a write operation, the master issues a start condition, a

device address byte, a memory address byte, and then up to

16 data bytes. The Turbo IC 24C08 acknowledges after each

byte transmission. To terminate the transmission, the master

issues a stop condition by pulling SDA from low to high while

SCL is high.

For a read operation, the master issues a start condition and

a device address byte. The Turbo IC 24C08 acknowledges,

and then transmits a data byte, which is accessed from the

EEPROM memory. The master acknowledges, indicating that

it requires more data bytes. The Turbo IC 24C08 transmits

more data bytes, with the memory address counter auto-

matically incrementing for each data byte, until the master

does not acknowledge, indicating that it is terminating the

transmission. The master then issues a stop condition.

DEVICE OPERATION:

BIDIRECTIONAL BUS PROTOCOL:

The Turbo IC 24C08 follows the I²C bus protocol. The proto-

col defines any device that sends data onto the SDA bus as

a transmitter, and the receiving device as a receiver. The

device controlling the transfer is the master and the device

being controlled is the slave. The master always initiates the

data transfers, and provides the clock for both transmit and

receive operations. The Turbo IC 24C08 acts as a slave de-

vice in all applications. Either the master or the slave can

take control of the SDA bus, depending on the requirement

of the protocol.

START/STOP CONDITION AND DATA TRANSITIONS:

While SCL clock is high, a high to low transition on the SDA

bus is recognized as a START condition which precedes any

read or write operation. While SCL clock is high, a low to

high transition on the SDA bus is recognized as a STOP con-

dition which terminates the communication and places the

Turbo IC 24C08 into standby mode. All other data transitions

on the SDA bus must occur while SCL clock is low to ensure

proper operation.

ACKNOWLEDGE:

All data is serially transmitted in bytes (8 bits) on the SDA

bus. The acknowledge protocol is used as a handshake sig-

nal to indicate successful transmission of a byte of data. The

bus transmitter, either the master or the slave (Turbo IC

24C08), releases the bus after sending a byte of data on the

SDA bus. The receiver pulls the SDA bus low during the ninth

clock cycle to acknowledge the successful transmission of a

byte of data. If the SDA is not pulled low during the ninth

clock cycle, the Turbo IC 24C08 terminates the data trans-

mission and goes into standby mode.

For the write operation, the Turbo IC 24C08 acknowledges

after the device address byte, acknowledges after the memory

address byte, and acknowledges after each subsequent data

byte.

For the read operation, the Turbo IC 24C08 acknowledges

after the device address byte. Then the Turbo IC 24C08 trans-

mits each subsequent data byte, and the master acknowl-

edges after each data byte transfer, indicating that it requires

more data bytes. The Turbo IC 24C08 monitors the SDA bus

for the acknowledge. To terminate the transmission, the mas-

ter does not acknowledge, and then sends a stop condition.

Write Cycle Timing

SCL

SDA

WORD n

8th BIT

ACK

STOP

CONDITION

START

CONDITION

t

WC

2

background image

24C08

Data Valid

Turbo IC, Inc.

Start and Stop Definition

Output Acknowledge

SDA

SCL

DATA STABLE

DATA STABLE

DATA

CHANGE

SDA

SCL

START

STOP

SCL

DATA IN

DATA OUT

1

8

9

ACKNOWLEDGE

START

3

background image

24C08

Turbo IC, Inc.

DEVICE ADDRESSING:

Following the start condition, the master will issue a device

address byte consisting of 1010 (A2) (B9) (B8) (R/W) to ac-

cess the selected Turbo IC 24C08 for a read or write opera-

tion. A2 is the device address select bit which has to match

the A2 pin input on the 24C08 device. The B[9:8] bits are the

2 most significant bits of the memory address. The (R/W) bit

is a high (1) for read and low (0) for write.

DATA INPUT DURING WRITE OPERATION:

During the write operation, the Turbo IC 24C08 latches the

SDA bus signal on the rising edge of the SCL clock.

DATA OUTPUT DURING READ OPERATION:

During the read operation, the Turbo IC 24C08 serially shifts

the data onto the SDA bus on the falling edge of the SCL

clock.

MEMORY ADDRESSING:

The memory address is sent by the master in the form of 2

bytes. Device address A2 and memory address bits B[9:8],

are included in the device address byte. The remaining

memory address bits B[7:0] are included in the second byte.

The memory address byte can only be sent as part of a write

operation.

BYTE WRITE OPERATION:

The master initiates the byte write operation by issuing a

start condition, followed by the device address byte 1010

(A2) (B9) (B8) 0, followed by the memory address byte, fol-

lowed by one data byte, followed by an acknowledge, then a

stop condition. After each byte transfer, the Turbo IC 24C08

acknowledges the successful data transmission by pulling

the SDA bus low. The stop condition starts the internal

EEPROM write cycle, and all inputs are disabled until the

completion of the write cycle.

4

PAGE WRITE OPERATION:

The master initiates the page write operation by issuing a

start condition, followed by the device address byte 1010

(A2) (B9) (B8) 0, followed by the memory address byte, fol-

lowed by up to 16 data bytes, followed by an acknowledge,

then a stop condition. After each byte transfer, the Turbo IC

24C08 acknowledges the successful data transmission by

pulling SDA low. After each data byte transfer, the memory

address counter is automatically incremented by one. The

stop condition starts the internal EEPROM write cycle only if

the stop condition occurs in the clock cycle immediately fol-

lowing the acknowledge (10th clock cycle). All inputs are dis-

abled until the completion of the write cycle.

POLLING ACKNOWLEDGE:

During the internal write cycle of a write operation in the Turbo

IC 24C08, the completion of the write cycle can be detected

by polling acknowledge. The master starts acknowledge poll-

ing by issuing a start condition, then followed by the device

address byte 1010 (A2) (B9) (B8) 0. If the internal write cycle

is finished, the Turbo IC 24C08 acknowledges by pulling the

SDA bus low. If the internal write cycle is still ongoing, the

Turbo IC 24C08 does not acknowledge because it’s inputs

are disabled. Therefore, the device will not respond to any

command. By using polling acknowledge, the system delay

for write operations can be reduced. Otherwise, the system

needs to wait for the maximum internal write cycle time, tWC,

given in the spec.

POWER ON RESET:

 The Turbo IC 24C08 has a Power On Reset circuit (POR) to

prevent data corruption and accidental write operations dur-

ing power up. On power up, the internal reset signal is on

and the Turbo IC 24C08 will not respond to any command

until the VCC voltage has reached the POR threshold value.

background image

24C08

Turbo IC, Inc.

Device Address

1

0

1

0

A

2

B

9

B

8

R/W

MSB

LSB

Byte Write

SDA LINE

 DEVICE

ADDRESS

WORD ADDRESS

DATA

S

T

O

P

A

C

K

A

C

K

M

S

B

L

S

B

R

/

W

A

C

K

S

T

A

R

T

W

R

I

T

E

Page Write

SDA LINE

 DEVICE

ADDRESS

  WORD ADDRESS 

DATA (n)

S

T

O

P

A

C

K

A

C

K

M

S

B

L

S

B

R

/

W

A

C

K

S

T

A

R

T

W

R

I

T

E

A

C

K

//

//

DATA (n + x)

5

background image

24C08

Turbo IC, Inc.

Random Read

CURRENT ADDRESS READ:

The internal memory address counter of the Turbo IC 24C08

contains the last memory address accessed during the pre-

vious read or write operation, incremented by one. To start

the current address read operation, the master issues a start

condition, followed by the device address byte 1010 (A2) (B9)

(B8) 1. The Turbo IC 24C08 responds with an acknowledge

by pulling the SDA bus low, and then serially shifts out the

data byte accessed from memory at the location correspond-

ing to the memory address counter. The master does not

acknowledge, then sends a stop condition to terminate the

read operation. It is noted that the memory address counter

is incremented by one after the data byte is shifted out.

RANDOM ADDRESS READ:

The master starts with a dummy write operation (one with no

data bytes) to load the internal memory address counter by

first issuing a start condition, followed by the device address

byte 1010 (A2) (B9) (B8) 0, followed by the memory address

bytes. Following the acknowledge from the Turbo IC 24C08,

the master starts the current read operation by issuing a start

condition, followed by the device address byte 1010 (A2) (B9)

(B8) 1. The Turbo IC 24C08 responds with

an acknowledge by pulling the SDA bus low, and then seri-

ally shifts out the data byte accessed from memory at the

location corresponding to the memory address counter. The

master does not acknowledge, then sends a stop condition

to terminate the read operation. It is noted that the memory

address counter is incremented by one after the data byte is

shifted out.

SEQUENTIAL READ:

The sequential read is initiated by either a current address

read or random address read. After the Turbo IC 24C08 seri-

ally shifts out the first data byte, the master acknowledges

by pulling the SDA bus low, indicating that it requires addi-

tional data bytes. After the data byte is shifted out, the Turbo

IC 24C08 increments the memory address counter by one.

Then the Turbo IC 24C08 shifts out the next data byte. The

sequential reads continues for as long as the master keeps

acknowledging. When the memory address counter is at the

last memory location, the counter will ‘roll-over’ when

incremented by one to the first location in memory (address

zero). The master terminates the sequential read operation

by not acknowledging, then sends a stop condition.

Current Address Read

SDA LINE

 DEVICE

ADDRESS

S

T

O

P

N

O

A

C

K

M

S

B

L

S

B

R

/

W

A

C

K

S

T

A

R

T

R

E

A

D

DATA

SDA LINE

 DEVICE

ADDRESS

DATA n

S

T

O

P

N

O

A

C

K

A

C

K

A

C

K

M

S

B

L

S

B

R

/

W

A

C

K

S

T

A

R

T

W

R

I

T

E

//

//

R

E

A

D

DEVICE

ADDRESS

WORD

ADDRESS N

DUMMY WRITE

6

background image

24C08

Turbo IC, Inc.

Sequential Read

SDA LINE

 DEVICE

ADDRESS

DATA n

        DATA n +1

DATA  n + 2

S

T

O

P

A

C

K

A

C

K

A

C

K

M

S

B

L

S

B

R

/

W

A

C

K

S

T

A

R

T

R

E

A

D

N

O

A

C

K

DATA n + 3

D.C. CHARACTERISTICS

Symbol

Parameter

Condition

Min

Max

Units

I

cc1

Active Vcc Current

READ at 100 KHZ

1.0

MA

I

cc2

Active Vcc Current

WRITE at 100 KHZ

3.0

MA

I

sb1

Standby Current

Vcc = 2.7 v

0.5

uA

Vcc = 5.5 v

2.0

uA

I

sb2

Standby Current

Vcc = 4.5 v

20.0

uA

Vcc = 5.5 v

35.0

uA

I

il

Input Leakage Current

Vin=Vcc Max

3

uA

I

ol

Output Leakage Current

3

uA

 V

il

Input Low Voltage

-1.0

0.8

V

V

ih

Input High Voltage

Vccx0.7

Vcc+0.5

V

V

ol2

Output Low

Vcc=3.0v  Iol=2.1 mA

0.4

V

V

ol1

Output Low

Vcc=2.7v   Iol=-0.15 mA

0.25

 V

 

* “Absolute Maximum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operation sec-

tion of this specification is not implied. Exposure to absolute maximum

rating conditions for extended  periods may affect device reliability.

TEMPERATURE

Storage:

-65°

 

C to 150° C

Under Bias:

-55° C to 125° C

ALL INPUT OR OUTPUT VOLTAGES

with respect to Vss

+6 V to -0.3 V

RECOMMENDED OPERATING CONDITIONS

Temperature Range:

Commercial:

0

°

 C to 70

°

 C

Industrial:

-40

°

 C to 85

°

 C

Military:

-55

°

 C to 125

°

 C

Vcc Supply Voltage:

2.7 to 5.5 Volts

4.5 to 5.5 Volts

Endurance:

100,000 Cycles/Byte (Typical)

Data Retention:

100 Years

ABSOLUTE MAXIMUM RATINGS

7

background image

24C08

Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131   Phone: 408-392-0208   Fax: 408-392-0207

See us at  www.turbo-ic.com

Rev. 4.0-10/28/01

TURBO IC PRODUCTS AND DOCUMENTS

1.

All documents are  subject to change without notice. Please contact  Turbo IC for the latest

revision of documents.

2.

Turbo IC does not assume any responsibility for any damage to the user that may result from

accidents or operation under abnormal conditions.

3.

Turbo IC does not assume any responsibility for the use of any circuitry other than what

embodied in a Turbo IC product. No other circuits, patents, licenses are implied.

4.

Turbo IC products are  not authorized for use in life support systems or other critical systems

where component failure may endanger life. System designers should design with error

detection and correction, redundancy and back-up features.

Turbo IC, Inc.

Bus Timing

t

SU.STA

t

HD.STA

t

F

t

LOW

t

HIGH

t

LOW

t

HD.DAT

t

SU.DAT

t

R

t

SU.STO

t

BUF

t

DH

t

AA

SCL

SDA IN

SDA OUT

Part Numbers & Order Information

TU24C08BS3I

1K X 8

Serial

EEPROM

A.C. CHARACTERISTICS

    Symbol

       Parameter

                           2.7 volt

                5.5 volt

Min

Max

Min

Max

Units

SCL

SCL Clock Frequency

100

400

kHZ

T

Noise Suppression Time (1)

100

100

ns

t

LOW

Clock Low Period

4.7

1.2

us

t

HIGH

Clock High Period

4.0

0.6

us

t

AA

SCL Low to SDA Data Out

0.1

4.5

0.1

0.9

us

t

BUF

Bus Free to New Start (1)

4.7

1.2

us

t

HD.STA

Start Hold Time

4.0

0.6

us

t

SU.STA

Start Set-up Time

4.7

0.6

us

t

HD.DAT

Data-in Hold Time

0

0

us

t

SU.DAT

Data-in Set-up Time

200

100

ns

t

R

SCL and SDA Rise Time (1)

1.0

0.3

us

t

F

SCL and SDA Fall Time (1)

300

300

ns

t

SU.STO

Stop Set-up Time

4.7

0.6

us

t

DH

Data-out Hold Time

100

50

ns

t

WC

Write Cycle Time

10

10

ms

Note: 1 This parameter is characterized and not 100% tested.

Temperature

-Commercial

  I -Industrial

Package

P -PDIP

S -SOIC

 Voltage

 3

 - 

2.7V to 5.5V

     - 4.5V to 5.5 V

2nd generation