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1

Data sheet acquired from Harris Semiconductor

SCHS181

Features

• Buffered Inputs

• High Current Bus Driver Outputs

• Two Independent Three-State Enable Controls

• Typical Propagation Delay t

PLH

, t

PHL

= 8ns at V

CC

= 5V,

C

L

 = 15pF, T

A

 = 25

o

C

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs  . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range  . . . -55

o

C to 125

o

C

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

 = 30%, N

IH

 = 30% of V

CC

at V

CC

 = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), V

IH

 = 2V (Min)

- CMOS Input Compatibility, I

l

1

µ

A at V

OL

, V

OH

Description

The Harris CD74HC367, CD74HCT367, CD74HC368, and

CD74HCT368 silicon gate CMOS three-state buffers are gen-

eral purpose high-speed non-inverting and inverting buffers.

They have high drive current outputs which enable high speed

operation even when driving large bus capacitances. These cir-

cuits possess the low power dissipation of CMOS circuitry, yet

have speeds comparable to low power Schottky TTL circuits.

Both circuits are capable of driving up to 15 low power Schottky

inputs.

The CD74HC367 and CD74HCT367 are non-inverting buffers,

whereas the CD74HC368 and CD74HCT368 are inverting buff-

ers. These devices have two output enables, one enable (OE1)

controls 4 gates and the other (OE2) controls the remaining 2

gates.

The CD74HCT367 and CD74HCT368 logic families are speed,

function and pin compatible with the standard 74LS logic family.

Ordering Information

PART NUMBER

TEMP. RANGE

(

o

C)

PACKAGE

PKG. NO.

CD74HC367E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT367E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT368E

-55 to 125

16 Ld PDIP

E16.3

CD74HC367M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT367M

-55 to 125

16 Ld SOIC

M16.15

CD74HC368M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT368M

-55 to 125

16 Ld SOIC

M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer or die for this part number is available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

Pinouts

CD74HC367, CD74HCT367

(PDIP, SOIC)

TOP VIEW

CD74HC368, CD74HCT368

(PDIP, SOIC)

TOP VIEW

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

OE1

1A

1Y

2A

2Y

3A

GND

3Y

V

CC

6A

6Y

5A

5Y

4A

4Y

OE2

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

OE1

1A

1Y

2A

2Y

3A

GND

3Y

V

CC

6A

6Y

5A

5Y

4A

4Y

OE2

November 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

 ©

 Harris Corporation 1997

CD74HC367, CD74HCT367,

CD74HC368, CD74HCT368

High Speed CMOS Logic Hex Buffer/Line Driver,

Three-State Non-Inverting and Inverting

File Number

1538.1

[ /Title

(CD74

HC367

,

CD74

HCT36

7,

CD74

HC368

,

CD74

HCT36

8)

/Sub-

ject

(High

Speed

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2

Functional Diagrams

CD74HC367, CD74HCT367

CD74HC368, CD74HCT368

TRUTH TABLE

INPUTS

OUTPUTS

(Y)

OE

A

HC/HCT367

HC/HCT368

L

L

L

H

L

H

H

L

H

X

(Z)

(Z)

NOTE:

H = High Voltage Level

L = Low Voltage Level

X = Don’t Care

Z = High Impedance (OFF) State

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

OE1

1A

1Y

2A

2Y

3A

GND

3Y

V

CC

6A

6Y

5A

5Y

4A

4Y

OE2

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

OE1

1A

1Y

2A

2Y

3A

GND

3Y

V

CC

6A

6Y

5A

5Y

4A

4Y

OE2

CD74HC367, CD74HCT367, CD74HC368, CD74HCT368

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3

Logic Diagram

NOTE: Inverter not included in HC/HCT367.

FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF

THOSE SHOWN, i.e., 1Y, 2Y, ETC.)

4

2A

2Y

5

6

3A

3Y

7

10

4A

4Y

9

12

5A

5Y

11

14

6A

6Y

13

OE1

1

15

OE2

ONE OF SIX IDENTICAL CIRCUITS

V

CC

3

1Y

GND

8

(NOTE)

2

1A

16

CD74HC367, CD74HCT367, CD74HC368, CD74HCT368

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4

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For V

I

 < -0.5V or V

I

 > V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Diode Current, I

OK

For V

O

 < -0.5V or V

O

 > V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

20mA

DC Drain Current, per Output, I

O

For -0.5V < V

O

 < V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . . . . . .±

35mA

DC Output Source or Sink Current per Output Pin, I

O

For V

O

 > -0.5V or V

O

 < V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

25mA

DC V

CC

 or Ground Current, I

CC

 . . . . . . . . . . . . . . . . . . . . . . . . .±

50mA

Operating Conditions

Temperature Range, T

A

 . . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125

o

C

Supply Voltage Range, V

CC

HC Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

I

, V

O

 . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3)

θ

JA

 (

o

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

160

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

o

C

Maximum Storage Temperature Range  . . . . . . . . . .-65

o

C to 150

o

C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

o

C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3.

θ

JA

 is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

High Level Input

Voltage

V

IH

-

-

2

1.5

-

-

1.5

-

1.5

-

V

4.5

3.15

-

-

3.15

 -

3.15

-

V

6

4.2

-

-

4.2

-

4.2

-

V

Low Level Input

Voltage

V

IL

-

-

2

-

-

0.5

-

0.5

-

0.5

V

4.5

-

-

1.35

-

1.35

-

1.35

V

6

-

-

1.8

-

1.8

-

1.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

 or

V

IL

-0.02

2

1.9

-

-

1.9

-

1.9

-

V

-0.02

4.5

4.4

-

-

4.4

 -

4.4

-

V

-0.02

6

5.9

-

-

5.9

-

5.9

-

V

High Level Output

Voltage

TTL Loads

-6

4.5

3.98

-

-

3.84

-

3.7

-

V

-7.8

6

5.48

-

-

5.34

-

5.2

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

 or

V

IL

0.02

2

-

-

0.1

-

0.1

-

0.1

V

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

0.02

6

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

6

4.5

-

-

0.26

-

0.33

-

0.4

V

7.8

6

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 or

GND

-

6

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

6

-

-

8

-

80

-

160

µ

A

CD74HC367, CD74HCT367, CD74HC368, CD74HCT368

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5

Three-State Leakage

Current

I

OZ

V

IL

 or

V

IH

V

O

 =

V

CC

 or

GND

6

-

-

±

0.5

-

±

5.0

-

±

10

µ

A

HCT TYPES

High Level Input

Voltage

V

IH

-

-

4.5 to

5.5

2

-

-

2

-

2

-

V

Low Level Input

Voltage

V

IL

-

-

4.5 to

5.5

-

-

0.8

-

0.8

-

0.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

 or

V

IL

-0.02

4.5

4.4

-

-

4.4

-

4.4

-

V

High Level Output

Voltage

TTL Loads

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

 or

V

IL

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

4

4.5

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 to

GND

0

5.5

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

5.5

-

-

8

-

80

-

160

µ

A

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

(Note 4)

I

CC

V

CC

-2.1

-

4.5 to

5.5

-

100

360

-

450

-

490

µ

A

Three-State Leakage

Current

I

OZ

V

IL

 or

V

IH

V

O

 =

V

CC

 or

GND

5.5

-

-

±

0.5

-

±

5.0

-

±

10

µ

A

NOTE:

4. For dual-supply systems theoretical worst case (V

I

 = 2.4V, V

CC

 = 5.5V) specification is 1.8mA.

DC Electrical Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HCT Input Loading Table

INPUT

UNIT LOADS

OE1

0.6

All Others

0.55

NOTE: Unit Load is

I

CC

limit specified in DC Electrical

Specifications table, e.g., 360

µ

A max at 25

o

C.

Switching Specifications

Input t

r

, t

f

 = 6ns

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO

125

o

C

UNITS

TYP

MAX

MAX

MAX

HC TYPES

Propagation Delay,

Data to Outputs

HC/HCT367

t

PLH

, t

PHL

C

L

= 50pF

2

-

105

130

160

ns

4.5

-

21

26

32

ns

6

-

18

24

27

ns

C

L

= 15pF

5

8

-

-

-

ns

CD74HC367, CD74HCT367, CD74HC368, CD74HCT368

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6

Propagation Delay,

Data to Outputs

HC/HCT368

t

PLH

, t

PHL

C

L

= 50pF

2

-

105

130

160

ns

4.5

-

21

26

32

ns

6

-

18

24

27

ns

C

L

= 15pF

5

9

-

-

-

ns

Propagation Delay,

Output Enable and Disable

to Outputs

t

PLH

, t

PHL

C

L

= 50pF

2

-

150

190

225

ns

4.5

-

30

38

45

ns

6

-

26

33

38

ns

C

L

= 15pF

5

12

-

-

-

ns

Output Transition Time

t

TLH

, t

THL

C

L

= 50pF

2

-

60

75

90

ns

4.5

-

12

15

18

ns

6

-

10

13

15

ns

Input Capacitance

C

I

-

-

-

10

10

10

pF

Three-State Output

Capacitance

C

O

-

-

-

20

20

20

pF

Power Dissipation

Capacitance

(Notes 5, 6)

C

PD

-

5

40

-

-

-

pF

HCT TYPES

Propagation Delay,

Data to Outputs

HC/HCT367

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

25

31

38

ns

C

L

= 15pF

5

9

-

-

-

ns

Propagation Delay,

Data to Outputs

HC/HCT368

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

30

38

45

ns

C

L

= 15pF

5

11

-

-

-

ns

Propagation Delay,

Output Enable and Disable

to Outputs

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

35

44

53

ns

C

L

= 15pF

5

14

-

-

-

ns

Output Transition Time

t

TLH

, t

THL

C

L

= 50pF

4.5

-

12

15

18

ns

Input Capacitance

C

IN

-

-

-

10

10

10

pF

Three-State Capacitance

C

O

-

-

-

20

20

20

pF

Power Dissipation

Capacitance

(Notes 5, 6)

C

PD

-

5

42

-

-

-

pF

NOTES:

5. C

PD

 is used to determine the dynamic power consumption, per buffer.

6. P

D

= V

CC

2

f

i

 (C

PD

 + C

L

) where f

i

 = Input Frequency, C

L

 = Output Load Capacitance, V

CC

 = Supply Voltage.

Switching Specifications

Input t

r

, t

f

 = 6ns  (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO

125

o

C

UNITS

TYP

MAX

MAX

MAX

CD74HC367, CD74HCT367, CD74HC368, CD74HCT368

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7

Test Circuits and Waveforms

FIGURE 2. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

FIGURE 5. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE:

Open drain waveforms t

PLZ

and t

PZL

are the same as those for three-state shown on the left. The test circuit is Output R

L

= 1k

to

V

CC

, C

L

 = 50pF.

FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

t

PHL

t

PLH

t

THL

t

TLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

V

CC

t

r

 = 6ns

t

f

 = 6ns

90%

t

PHL

t

PLH

t

THL

t

TLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

t

r

 = 6ns

t

f

 = 6ns

90%

50%

10%

90%

GND

V

CC

10%

90%

50%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

6ns

6ns

t

PZH

t

PHZ

t

PZL

t

PLZ

0.3

2.7

GND

3V

10%

90%

1.3V

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

t

r

6ns

t

PZH

t

PHZ

t

PZL

t

PLZ

6ns

t

f

1.3

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

V

CC

 FOR t

PLZ

 AND t

PZL

GND FOR t

PHZ

 AND t

PZH

OUTPUT

R

L

 = 1k

C

L

50pF

CD74HC367, CD74HCT367, CD74HC368, CD74HCT368

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

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 1999, Texas Instruments Incorporated