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SN54HC164, SN74HC164

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

 

 

SCLS115B – DECEMBER 1982 – REVISED MAY 1997

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

AND-Gated (Enable / Disable) Serial Inputs

D

Fully Buffered Clock and Serial Inputs

D

Direct Clear

D

Package Options Include Plastic

Small-Outline (D) and Ceramic Flat (W)

Packages, Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J)

300-mil DIPs

description

These 8-bit shift registers feature AND-gated

serial inputs and an asynchronous clear (CLR)

input. The gated serial (A and B) inputs permit

complete control over incoming data; a low at

either input inhibits entry of the new data and

resets the first flip-flop to the low level at the next

clock (CLK) pulse. A high-level input enables the

other input, which then determines the state of the

first flip-flop. Data at the serial inputs can be

changed while CLK is high or low, provided the

minimum setup time requirements are met.

Clocking occurs on the low-to-high-level transition

of CLK.

The SN54HC164 is characterized for operation

over the full military temperature range of –55

°

C

to 125

°

C. The SN74HC164 is characterized for

operation from –40

°

C to 85

°

C.

FUNCTION TABLE

INPUTS

OUTPUTS

CLR

CLK

A

B

QA

QB . . . QH

L

X

X

X

L

L

L

H

L

X

X

QA0

QB0

QH0

H

H

H

H

QAn

QGn

H

L

X

L

QAn

QGn

H

X

L

L

QAn

QGn

QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,

before the indicated steady-state input conditions were

established

QAn, QGn = the level of QA or QG before the most recent

 transition of CLK: indicates a 1-bit shift

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54HC164 . . . J  OR  W  PACKAGE

SN74HC164 . . . D  OR  N  PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

A

B

Q

A

Q

B

Q

C

Q

D

GND

V

CC

Q

H

Q

G

Q

F

Q

E

CLR

CLK

3

2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

Q

G

NC

Q

F

NC

Q

E

Q

A

NC

Q

B

NC

Q

C

B

A

NC

CLK

CLR

V

Q

D

GND

NC

SN54HC164 . . . FK PACKAGE

(TOP VIEW)

CC

H

Q

NC – No internal connection

 

Copyright 

©

 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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SN54HC164, SN74HC164

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

 

 

SCLS115B – DECEMBER 1982 – REVISED MAY 1997

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

SRG8

R

9

8

CLK

C1/

1

A

3

2

B

CLR

4

&

1D

5

6

10

11

12

13

QA

QB

QC

QD

QE

QF

QG

QH

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, N, and W packages.

logic diagram (positive logic)

9

A

B

CLR

CLK

Pin numbers shown are for the D, J, N, and W packages.

C1

1D

R

3

QA

C1

1D

R

4

QB

C1

1D

R

5

QC

C1

1D

R

6

QD

C1

1D

R

10

QE

C1

1D

R

11

QF

C1

1D

R

12

QG

C1

1D

R

13

QH

2

1

8

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SN54HC164, SN74HC164

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

 

 

SCLS115B – DECEMBER 1982 – REVISED MAY 1997

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

typical clear, shift, and clear sequence

CLK

A

B

CLR

QA

QB

QC

QD

QE

QF

QG

QH

Clear

Clear

Serial Inputs

Outputs

absolute maximum ratings over operating free-air temperature range

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0 or V

I

 > V

CC

) (see Note 1) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0 or V

O

 > V

CC

) (see Note 1) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 (V

O

 = 0 to V

CC

±

25 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): D package 

127

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

N package 

78

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace

length of zero.

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SN54HC164, SN74HC164

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

 

 

SCLS115B – DECEMBER 1982 – REVISED MAY 1997

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions

SN54HC164

SN74HC164

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

2

5

6

2

5

6

V

VCC = 2 V

1.5

1.5

VIH

High-level input voltage

VCC = 4.5 V

3.15

3.15

V

VCC = 6 V

4.2

4.2

VCC = 2 V

0

0.5

0

0.5

VIL

Low-level input voltage

VCC = 4.5 V

0

1.35

0

1.35

V

VCC = 6 V

0

1.8

0

1.8

VI

Input voltage

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

V

VCC = 2 V

0

1000

0

1000

tt†

Input transition (rise and fall) time

VCC = 4.5 V

0

500

0

500

ns

VCC = 6 V

0

400

0

400

TA

Operating free-air temperature

–55

125

–40

85

°

C

† If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced

grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,

the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25

°

C

SN54HC164

SN74HC164

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

1.9

1.998

1.9

1.9

IOH = –20 

µ

A

4.5 V

4.4

4.499

4.4

4.4

VOH

VI = VIH or VIL

6 V

5.9

5.999

5.9

5.9

V

IOH = –4 mA

4.5 V

3.98

4.3

3.7

3.84

IOH = –5.2 mA

6 V

5.48

5.8

5.2

5.34

2 V

0.002

0.1

0.1

0.1

IOL = 20 

µ

A

4.5 V

0.001

0.1

0.1

0.1

VOL

VI = VIH or VIL

6 V

0.001

0.1

0.1

0.1

V

IOL = 4 mA

4.5 V

0.17

0.26

0.4

0.33

IOL = 5.2 mA

6 V

0.15

0.26

0.4

0.33

II

VI = VCC or 0

6 V

±

0.1

±

100

±

1000

±

1000

nA

ICC

VI = VCC or 0,

IO = 0

6 V

8

160

80

µ

A

Ci

2 V to 6 V

3

10

10

10

pF

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SN54HC164, SN74HC164

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

 

 

SCLS115B – DECEMBER 1982 – REVISED MAY 1997

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25

°

C

SN54HC164

SN74HC164

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

0

6

0

4.2

0

5

fclock

Clock frequency

4.5 V

0

31

0

21

0

25

MHz

6 V

0

36

0

25

0

28

2 V

100

150

125

CLR low

4.5 V

20

30

25

t

Pulse duration

6 V

17

25

21

ns

tw

Pulse duration

2 V

80

120

100

ns

CLK high or low

4.5 V

16

24

20

6 V

14

20

18

2 V

100

150

125

Data

4.5 V

20

30

25

t

Setup time before CLK

6 V

17

25

21

ns

tsu

Setup time before CLK

2 V

100

150

125

ns

CLR inactive

4.5 V

20

30

25

6 V

17

25

21

2 V

5

5

5

th

Hold time, data after CLK

4.5 V

5

5

5

ns

6 V

5

5

5

switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25

°

C

SN54HC164

SN74HC164

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

6

10

4.2

5

fmax

4.5 V

31

54

21

25

MHz

6 V

36

62

25

28

2 V

140

205

295

255

tPHL

CLR

Any Q

4.5 V

28

41

59

51

6 V

24

35

51

46

ns

2 V

115

175

265

220

ns

tpd

CLK

Any Q

4.5 V

23

35

53

44

6 V

20

30

45

38

2 V

38

75

110

95

tt

4.5 V

8

15

22

19

ns

6 V

6

13

19

16

operating characteristics, T

A

 = 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

No load

135

pF

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SN54HC164, SN74HC164

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

 

 

SCLS115B – DECEMBER 1982 – REVISED MAY 1997

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

th

tsu

50%

50%

50%

10%

10%

90%

90%

VCC

VCC

0 V

0 V

tr

tf

Reference

Input

Data

Input

50%

High-Level

Pulse

50%

VCC

0 V

50%

50%

VCC

0 V

tw

Low-Level

Pulse

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

50%

50%

50%

10%

10%

90%

90%

VCC

VOH

VOL

0 V

tr

tf

Input

In-Phase

Output

50%

tPLH

tPHL

50%

50%

10%

10%

90%

90%

VOH

VOL

tr

tf

tPHL

tPLH

Out-of-Phase

Output

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR 

 1 MHz, ZO = 50 

, tr = 6 ns, tf = 6 ns.

C. For clock inputs, fmax is measured when the input duty cycle is 50%.

D. The outputs are measured one at a time with one input transition per measurement.

E. tPLH and tPHL are the same as tpd.

Test

Point

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Figure 1. Load Circuit and Voltage Waveforms

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

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Copyright 

©

 1998, Texas Instruments Incorporated