background image

 TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Copyright 

©

 1995, Texas Instruments Incorporated

1

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Second-Generation PLD Architecture

High-Performance Operation:

f

max

 (External Feedback) . . . 80 MHz

Propagation Delay . . . 7.5 ns Max

Increased Logic Power – Up to 22 Inputs

and 10 Outputs

Increased Product Terms – Average of 12

Per Output

Variable Product Term Distribution 

Allows More Complex Functions to Be

Implemented

Each Output Is User Programmable for

Registered or Combinational Operation,

Polarity, and Output Enable Control

Power-Up Clear on Registered Outputs

TTL-Level Preload for Improved Testability

Extra Terms Provide Logical Synchronous

Set and Asynchronous Reset Capability

Fast Programming, High Programming

Yield, and Unsurpassed Reliability Ensured

Using Ti-W Fuses

AC and DC Testing Done at the Factory

Utilizing Special Designed-In Test Features

Package Options Include Both Plastic Chip

Carrier and Plastic DIP

     

description

The TIBPAL22V10-7C is a programmable array logic device featuring high speed and functional equivalency

when compared to presently available devices. The TIBPAL22V10-7C is implemented with the familiar

sum-of-products (AND-OR) logic structure featuring programmable output logic macrocells. This IMPACT-X

circuit combines the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to

provide reliable, high-performance substitutes for conventional TTL logic.

This device contains up to 22 inputs and 10 outputs. It incorporates the unique capability of defining and

programming the architecture of each output on an individual basis. Outputs can be registered or nonregistered

and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are

enabled through the use of individual product terms.

These devices are covered by U.S. Patent 4,410,987.

IMPACT-X is a trademark of Texas Instruments Incorporated.

NT PACKAGE

(TOP VIEW)

1

2

3

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CLK/I

I

I

I

I

I

I

I

I

I

I

GND

V

CC

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I

3 2 1 28 27

12 13

5

6

7

8

9

10

11

25

24

23

22

21

20

19

I/O/Q

I/O/Q

I/O/Q

NC

I/O/Q

I/O/Q

I/O/Q

I

I

I

NC

I

I

I

4

26

14 15 16 17 18

I

I

GND

NC

I

I/O/Q

I/O/Q

I

I

CLK/I

NC

I/O/Q

I/O/Q

FN PACKAGE

(TOP VIEW)

NC

No internal connection

Pin assignments in operating mode

V

CC

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TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

2

description (continued)

Further advantages can be seen in the introduction of variable product term distribution. This technique

allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This

variable allocation of terms allows far more complex functions to be implemented than in previously available

devices.

Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These

functions are common to all registers. When the synchronous set product term is a logic 1, the output registers

are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term

is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on

the polarity selected during programming. Output registers can be preloaded to any desired state during testing.

Preloading permits full logical verification during product testing.

With features such as programmable output logic macrocells and variable product term distribution, the

TIBPAL22V10’ offers quick design and development of custom LSI functions with complexities of 500 to 800

equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a

temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and

10 outputs are possible.

A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is

applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered

outputs selected as active-high power up with their outputs low.

A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once

blown, the verification circuitry is disabled and all other fuses will appear to be open.

The TIBPAL22V10-7C is characterized for operation from 0

°

C to 75

°

C.

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 TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

3

functional block diagram (positive logic)

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

10

12

14

EN

16

16

14

12

10

22

22

1

10

&

44 x 132

I/O/Q

I/O/Q

I/O/Q

I/O/Q

EN

EN

EN

EN

EN

EN

EN

EN

EN

10

10

8

8

10

11

CLK/I

I

Set

Reset

1S

R

C1

denotes fused inputs

Output

Logic

Macrocell

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TIBP

AL22V10-7C

HIGH-PERFORMANCE 

IMP

ACT

-X

 PROGRAMMABLE ARRA

Y LOGIC CIRCUITS

SRPS014D

 – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST

 OFFICE BOX 655303 

 DALLAS, TEXAS 75265

4

0

4

8

12

16

20

24

28

Increment

First

Fuse

Numbers

32

36

40

Macro-

cell

R = 5809

P = 5808

R = 5811

P = 5810

R = 5813

P = 5812

R = 5815

P = 5814

R = 5817

P = 5816

logic diagram (positive logic)

Asynchronous Reset

23

22

21

20

19

1

2

3

4

5

(to all registers)

396

0

440

880

924

1452

1496

2112

2156

2860

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I

I

I

I

CLK/I

Macro-

cell

Macro-

cell

Macro-

cell

Macro-

cell

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 TIBP

AL22V10-7C

HIGH-PERFORMANCE 

IMP

ACT

-X

 PROGRAMMABLE ARRA

Y LOGIC CIRCUITS

SRPS014D

 – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST

 OFFICE BOX 655303 

 DALLAS, TEXAS 75265

5

Fuse number = First fuse number + Increment

R = 5819

P = 5818

R = 5821

P = 5820

R = 5823

P = 5822

R = 5825

P = 5824

R = 5827

P = 5826

18

6

7

8

9

10

11

17

16

15

14

Synchronous Set

13

(to all registers)

Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.

2904

3608

3652

4268

4312

4840

4884

5324

5368

5720

5764

I

I

I

I

I

I

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I

Macro-

cell

Macro-

cell

Macro-

cell

Macro-

cell

Macro-

cell

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TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

6

output logic macrocell diagram

C1

G

0

3

0

1

1

0

3

2

MUX

I = 0

1S

1D

R

MUX

G1

1

1

SS

AR

From Clock Buffer

S1

S0

AR = asynchronous reset

SS = synchronous set

Output Logic Macrocell

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FEEDBACK AND OUTPUT CONFIGURATION

 TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

7

C1

1S

1D

R

S1 = 0

S0 = 0

C1

1S

1D

R

S1 = 0

S0 = 1

REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT

REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT

S1 = 1

S0 = 0

S1 = 1

S0 = 1

I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT

I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT

MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE

FUSE SELECT

S1

S0

0

0

Register feedback

Registered

Active low

0

1

Register feedback

Registered

Active high

1

0

I/O feedback

Combinational

Active low

1

1

I/O feedback

Combinational

Active high

0 = unblown fuse, 1 = blown fuse

S1 and S0 are select-function fuses as shown in the output logic macrocell

diagram.

Figure 1. Resultant Macrocell Feedback and Output Logic After Programming

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ns

Pulse duration

tw

TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

8

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

CC

 (see Note 1) 

  7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range (see Note 1) 

 –1.2 V to V

CC

 +0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to disabled output (see Note 1) 

 – 0.5 V to V

CC

 +0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range 

 0

°

C to 75

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range 

 – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.75

5

5.25

V

VIH

High-level input voltage (see Note 2)

2

5.5

V

VIL

Low-level input voltage (see Note 2)

0.8

V

IOH

High-level output current

– 3.2

mA

IOL

Low-level output current

16

mA

Clock high or low

4

Asynchronous reset high or low

6

Input

5.5

Feedback

5.5

tsu

Setup time before clock

Synchronous preset (active)

8

ns

Synchronous preset (inactive)

8

Asynchronous reset (inactive)

6

th

Hold time, input, set, or feedback after clock

0

ns

TA

Operating free-air temperature

0

75

°

C

NOTE 2: These are absolute voltage levels with respect to the ground terminal of the device and includes all overshoots due to system and/or

tester noise. Testing these parameters should not be attempted without suitable equipment.

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IIL

VCC = 5.25 V,

VI = 0.4 V

mA

UNIT

TEST

CONDITIONS

TO

(OUTPUT)

FROM

(INPUT)

PARAMETER

 TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

9

electrical characteristics over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIK

VCC = 4.75 V,

II = – 18 mA

– 1.2

V

VOH

VCC = 4.75 V,

IOH = – 3.2 mA

2.4

V

VOL

VCC = 4.75 V,

IOL = 16 mA

0.35

0.5

V

IOZH‡

VCC = 5.25 V,

VO = 2.7 V

0.1

mA

IOZL‡

VCC = 5.25 V,

VO = 0.4 V

– 0.1

mA

II

VCC = 5.25 V,

VI = 5.5 V

1

mA

IIH‡

VCC = 5.25 V,

VI = 2.7 V

25

µ

A

CLK

– 0.25

All others

– 0.1

IOS§

VCC = 5.25 V,

VO = 0.5 V

– 30

– 130

mA

ICC

VCC = 5.25 V,

VI = GND,

Outputs open

210

mA

Ci

f = 1 MHz,

VI = 2 V

6

pF

Co

f = 1 MHz,

VO = 2 V

8

pF

† All typical values are at VCC = 5 V, TA = 25

°

C.

‡ I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively.

§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to

avoid test problems caused by test equipment ground degradation.

switching characteristics

 

over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

TIBPAL22V10-7CFN

TIBPAL22V10-7CNT

MIN

MAX

MIN

MAX

Without feedback

125

125

fmax¶

With internal feedback (counter configuration)

100

100

MHz

With external feedback

87

80

tpd

I, I/O

I/O

R1 = 300 

,

3

7.5

3

7.5

ns

tpd

I, I/O (reset)

Q

R2 = 300 

,

12

12

ns

tpd

CLK

Q

See Figure 6

1.5

6

1.5

7

ns

tpd#

CLK

Feedback

4.5

4.5

ns

ten

I, I/O

I/O, Q

8

8

ns

tdis

I, I/O

I/O, Q

7.5

7.5

ns

¶ fmax (without feedback) = 

1

tw(low)

)

tw(high)

   fmax (with internal feedback) =  

1

tsu

)

t

pd

(CLK to feedback)

   fmax (with external feedback) = 

1

tsu

)

t

pd

(CLK to Q)

# This parameter is calculated from the measured fmax with internal feedback in the counter configuration.

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TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

10

preload procedure for registered outputs (see Notes 3 and 4)

The output registers can be preloaded to any desired state during device testing. This permits any state to be

tested without having to step through the entire state-machine sequence. Each register is preloaded individually

by following the steps given below:

Step 1. With V

CC

 at 5 V and pin 1 at V

IL

, raise pin 13 to V

IHH

.

Step 2. Apply either V

IL

 or V

IH

 to the output corresponding to the register to be preloaded.

Step 3. Pulse pin 1, clocking in preload data.

Step 4. Remove output voltage, then lower pin 13 to V

IL

. Preload can be verified by observing the voltage

level at the output pin.

td

tsu

tw

td

VIHH

VIL

VIL

VOL

VOH

VIH

Pin 13

Pin 1

Registered I/O

Input

Output

VIH

VIL

Figure 2. Preload Waveforms

NOTES: 3. Pin numbers shown are for the  NT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly.

4.

t

d = 

t

su =

 t

w

 

= 100 ns to 1000 ns. 

V

IHH

 

= 10.25 V to 10.75 V.

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 TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

11

power-up reset

Following power up, all registers are reset to zero. The output level depends on the polarity selected during

programming. This feature provides extra flexibility to the system designer and is especially valuable in

simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of V

CC

  be

monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and

feedback setup times are met.

1.5 V

tsu‡

tpd†

tw

VOL

VOH

VIL

VIH

5 V

VCC

Active High

Registered Output

Active Low

Registered Output

CLK

4 V

VOH

VOL

1.5 V

1.5 V

(600 ns typ, 1000 ns MAX)

State Unknown

1.5 V

State Unknown

† This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.

‡ This is the setup time for input or feedback.

Figure 3. Power-Up Reset Waveforms

programming information

Texas Instruments programmable logic devices can be programmed using widely available software and

inexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, and

firmware are available upon request. Information on programmers capable of programming Texas Instruments

programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI

distributor, or by calling Texas Instruments at (214) 997-5666.

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TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

12

THERMAL INFORMATION

thermal management of the TIBPAL22V10-7C

Thermal management of the TIBPAL22V10-7CNT and TIBPAL22V10-7CFN is necessary when operating at

certain conditions of frequency, output loading, and outputs switching simultaneously. The device and system

application will determine the appropriate level of management.

Determining the level of thermal management is based on factors such as power dissipation (P

D

), ambient

temperature (T

A

), and transverse airflow (FPM). Figures 4 (a) and 4 (b) show the relationship between ambient

temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be

determined at a particular ambient temperature and device power dissipation level in order to ensure the device

specifications.

Figure 5 illustrates how power dissipation varies as a function of frequency and the number of outputs switching

simultaneously. It should be noted that all outputs are fully loaded (C

L

 = 50 pF ). Since the condition of ten fully

loaded outputs represents the worst-case condition, each application must be evaluated accordingly.

(a) TIBPAL22V10-7CNT

40

20

10

0

0

200

400

600

60

70

Minimum 

T

ransverse 

Air Flow – ft/min

80

50

30

MINIMUM TRANSVERSE AIR FLOW

vs

AMBIENT TEMPERATURE

TA – Ambient Temperature –

°

C

100

300

500

40

20

10

0

0

200

400

600

60

70

Minimum 

T

ransverse 

Air Flow – ft/min

MINIMUM TRANSVERSE AIR FLOW

vs

AMBIENT TEMPERATURE

80

50

30

TA – Ambient Temperature –

°

C

(b) TIBPAL22V10-7CFN

100

300

500

PD = 1.8 W

PD = 1.6 W

PD = 1.4 W

PD = 1.2 W

PD = 1 W

PD = 1.8 W

PD = 1.6 W

PD = 1.4 W

PD = 1.2 W

PD = 1 W

Figure 4

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 TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

13

THERMAL INFORMATION

1400

1300

1200

1700

f – Frequency – MHz

1800

P

D

 – Power Dissipation – mW

POWER DISSIPATION

vs

FREQUENCY

1900

2000

1600

1500

0.1

0.4

1

4

10

40

100

0.2

2

20

200

VCC = 5 V

R1 = 300 

R2 = 300 

TA = 25 

°

C

CL = 50 pF

1 Output Switching

10 Outputs Switching

Figure 5

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TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

14

PARAMETER MEASUREMENT INFORMATION

tsu

S1

From Output

Under Test

Test

Point

R2

CL

(see Note A)

LOAD CIRCUIT FOR

3-STATE OUTPUTS

3 V

0

1.5 V

1.5 V

th

1.5 V

Timing

Input

Data

Input

Input

In-Phase

Output

Out-of-Phase

Output

(see Note D)

tpd

tpd

tpd

tpd

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOH

VOH

VOL

VOL

3 V

0

3 V

(see Note B)

1.5 V

1.5 V

1.5 V

1.5 V

tw

High-Level

Pulse

Low-Level

Pulse

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note C)

Waveform 2

S1 Open

(see Note C)

1.5 V

1.5 V

3 V

(see Note B)

 2.7 V

VOL

VOH

VOH – 0.5 V

 0 V

ten

ten

tdis

tdis

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

R1

3 V

3 V

(see Note B)

0

VOL 

+

 0.5 V

5 V

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.

B. All input pulses have the following characteristics: PRR 

 1 MHz, tr = tf = 2 ns, duty cycle = 50%.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2

is for an output with internal conditions such that the output is high except when disabled by the output control.

D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.

E. Equivalent loads may be used for testing.

Figure 6. Load Circuit and Voltage Waveforms

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 TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

15

TYPICAL CHARACTERISTICS

200

190

180

170

0

25

50

Figure 7

210

SUPPLY CURRENT

vs

FREE - AIR TEMPERATURE

75

TA – Free - Air Temperature –

°

C

I CC

 – Supply Current – mA

VCC = 4.75 V

VCC = 5.25 V

VCC = 5 V

1

0

7

2

3

4

5

6

0

25

50

Figure 9

Propagation Delay T

ime 

– 

ns

75

PROPAGATION DELAY TIME

vs

FREE - AIR TEMPERATURE

VCC = 5 V

CL = 50 pF

R1 = 300 

R2 = 300 

10 Outputs  Switching

TA – Free - Air Temperature –

°

C

1

0

4.75

5

Figure 8

Propagation Delay T

ime 

– 

ns

7

PROPAGATION DELAY TIME

vs

SUPPLY VOLTAGE

5.25

VCC – Supply Voltage – V

TA = 25 

°

C

CL = 50 pF

R1 = 300 

R2 = 300 

10 Outputs Switching

CL – Load Capacitance – pF

8

4

2

0

100

200

300

400

Figure 10

12

14

16

500

10

6

PROPAGATION DELAY TIME

vs

LOAD  CAPACITANCE

VCC = 5 V

TA = 25

°

C

R1 = 300 

R2 = 300 

1 Output Switching

0

600

2

3

4

5

6

tPLH (I, I/O to O, I/O)

tPHL (I, I/O to O, I/O)

tPLH (CLK to Q)

tPHL (CLK to Q)

tPHL (I, I/O to O, I/O)

tPLH (I, I/O to O, I/O)

tPLH (CLK to Q)

tPHL (CLK to Q)

t

pd

 – Propagation Delay T

ime – ns

tpd (CLK to Q)

tpd (I, I/O to O, I/O)

background image

TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

 PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

16

TYPICAL CHARACTERISTICS

900

800

1

4

10

40

100

Figure 13

1100

f – Frequency – MHz

1200

2

20

P

D

 – Power Dissipation – mW

POWER DISSIPATION

vs

FREQUENCY

10 - BIT COUNTER MODE

VCC = 5 V

TA = 75 

°

C

TA = 0 

°

C

TA = 25 

°

C

2

5

3

1

1

2

3

4

5

Figure 11

Propagation Delay T

ime 

– 

ns

7

6

7

6

4

WORST-CASE PROPAGATION DELAY TIME

vs

NUMBER OF OUTPUTS SWITCHING

FN  PACKAGE

VCC = 5 V

TA = 25

°

C

CL = 50 pF

R1 = 300 

R2 = 300 

Number of Outputs Switching

6

7

10

= tPLH (I, I/O to O, I/O)

= tPHL (I, I/O to O, I/O)

= tPLH (CLK to Q)

= tPHL (CLK to Q)

1000

2

5

3

1

1

2

3

4

5

Figure 12

Propagation Delay T

ime 

– 

ns

7

6

7

6

4

WORST-CASE PROPAGATION DELAY TIME

vs

NUMBER OF OUTPUTS SWITCHING

NT PACKAGE

VCC = 5 V

TA = 25

°

C

CL = 50 pF

R1 = 300 

R2 = 300 

Number of Outputs Switching

6

7

10

= tPLH (I, I/O to O, I/O)

= tPHL (I, I/O to O, I/O)

= tPLH (CLK to Q)

= tPHL (CLK to Q)

background image

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©

 1998, Texas Instruments Incorporated