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1

Data sheet acquired from Harris Semiconductor

SCHS135

Features

• True and Complementary Outputs

• Buffered Inputs and Outputs

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs  . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range  . . . -55

o

C to 125

o

C

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

 = 30%, N

IH

 = 30% of V

CC

at V

CC

 = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), V

IH

 = 2V (Min)

- CMOS Input Compatibility, I

l

1

µ

A at V

OL

, V

OH

Description

The Harris CD74HC75 and CD74HCT75 are dual 2-bit

bistable transparent latches. Each one of the 2-bit latches is

controlled by separate Enable inputs (1E and 2E) which are

active LOW. When the Enable input is HIGH data enters the

latch and appears at the Q output. When the Enable input

(1E and 2E) is LOW the output is not affected.

Pinout

CD74HC75, CD74HCT75

(PDIP, SOIC)

TOP VIEW

Ordering Information

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

1Q0

1D0

1D1

2E

V

CC

2D0

2Q1

2D1

1Q0

1Q1

1E

GND

2Q0

2Q0

2Q1

1Q1

March 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

 ©

 Harris Corporation 1998

File Number

1666.1

CD74HC75,

CD74HCT75

Dual 2-Bit Bistable

Transparent Latch

[ /Title

(CD74

HC75,

CD74

HCT75

)

/Sub-

ject

(Dual

2-Bit

Bistabl

e

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2

Functional Diagram

TRUTH TABLE

INPUTS

OUTPUTS

D

E

Q

Q

L

H

L

H

H

H

H

L

X

L

Q0

Q0

NOTE:

H = High Level

L

= Low Level

X = Don’t Care

Q0 = The level of Q before the transition of E.

D0

2 (6)

3 (7)

16 (10)

Q1

Q0

D1

13 (4)

E

1 (11)

14 (8)

15 (9)

Q0

Q1

1 OF 2

LATCHES

FIGURE 1. LOGIC DIAGRAM

FIGURE 2. LATCH DETAIL

D0

3 (7)

2 (6)

LATCH 0

Q

D

LE

LE

16 (10)

1 (11)

Q0

Q0

E

13 (4)

LATCH 1

Q

D

LE

LE

D1

14 (8)

Q1

15 (9)

Q1

5

12

GND

V

CC

P

N

LE

LE

Q

P

N

LE

LE

Q

CD74HC75, CD74HCT75

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3

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For V

I

 < -0.5V or V

I

 > V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . .±

20mA

DC Drain Current, per Output, I

O

For -0.5V < V

O

 < V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . . . . . .±

25mA

DC Output Diode Current, I

OK

For V

O

 < -0.5V or V

O

 > V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Source or Sink Current per Output Pin, I

O

For V

O

 > -0.5V or V

O

 < V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

25mA

DC V

CC

 or Ground Current, I

CC

 . . . . . . . . . . . . . . . . . . . . . . . . .±

50mA

Operating Conditions

Temperature Range, T

A

 . . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125

o

C

Supply Voltage Range, V

CC

HC Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

I

, V

O

 . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3)

θ

JA

 (

o

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

115

Maximum Junction Temperature (Hermetic Package or Die) . . . 175

o

C

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150

o

C

Maximum Storage Temperature Range  . . . . . . . . . .-65

o

C to 150

o

C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

o

C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3.

θ

JA

 is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

High Level Input

Voltage

V

IH

-

-

2

1.5

-

-

1.5

-

1.5

-

V

4.5

3.15

-

-

3.15

 -

3.15

-

V

6

4.2

-

-

4.2

-

4.2

-

V

Low Level Input

Voltage

V

IL

-

-

2

-

-

0.5

-

0.5

-

0.5

V

4.5

-

-

1.35

-

1.35

-

1.35

V

6

-

-

1.8

-

1.8

-

1.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

 or

V

IL

-0.02

2

1.9

-

-

1.9

-

1.9

-

V

4.5

4.4

-

-

4.4

 -

4.4

-

V

6

5.9

-

-

5.9

-

5.9

-

V

High Level Output

Voltage

TTL Loads

-

-

-

-

-

-

-

-

-

V

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

-5.2

6

5.48

-

-

5.34

-

5.2

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

 or

V

IL

0.02

2

-

-

0.1

-

0.1

-

0.1

V

4.5

-

-

0.1

-

0.1

-

0.1

V

6

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

-

-

-

-

-

-

-

-

-

V

4

4.5

-

-

0.26

-

0.33

-

0.4

V

5.2

6

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 or

GND

-

6

-

-

±

0.1

-

±

1

-

±

1

µ

A

CD74HC75, CD74HCT75

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4

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

6

-

-

4

-

40

-

80

µ

A

HCT TYPES

High Level Input

Voltage

V

IH

-

-

4.5 to

5.5

2

-

-

2

-

2

-

V

Low Level Input

Voltage

V

IL

-

-

4.5 to

5.5

-

-

0.8

-

0.8

-

0.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

 or

V

IL

-

4.5

4.4

-

-

4.4

-

4.4

-

V

High Level Output

Voltage

TTL Loads

-0.02

4.5

3.98

-

-

3.84

-

3.7

-

V

Low Level Output

Voltage CMOS Loads

V

OL

V

IH

 or

V

IL

-4

4.5

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

0.02

4.5

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

and

GND

4

5.5

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

5.5

-

-

4

-

40

-

80

µ

A

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

I

CC

(Note 4)

V

CC

- 2.1

-

4.5 to

5.5

-

100

360

-

450

-

490

µ

A

NOTE:

4. For dual-supply systems theoretical worst case (V

I

 = 2.4V, V

CC

 = 5.5V) specification is 1.8mA.

DC Electrical Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HCT Input Loading Table

INPUT

UNIT LOADS

D0, D1

0.8

1E, 2E

1.2

NOTE: Unit Load is

I

CC

limit specified in DC Electrical Specifica-

tions table, e.g., 360

µ

A max at 25

o

C.

Prerequisite For Switching Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

Pulse Width Enable Input

t

W

-

2

80

-

-

100

-

120

-

ns

4.5

16

-

-

20

-

24

-

ns

6

14

-

-

17

-

20

-

ns

Setup Time D to Enable

t

SU

-

2

60

-

-

75

-

90

-

ns

4.5

12

-

-

15

-

18

-

ns

6

10

-

-

13

-

15

-

ns

CD74HC75, CD74HCT75

background image

5

Hold Time Enable to D

t

H

-

2

3

-

-

3

-

3

-

ns

4.5

3

-

-

3

-

3

-

ns

6

3

-

-

3

-

3

-

ns

HCT TYPES

Pulse Width Enable Input

t

W

-

4.5

16

-

-

20

-

24

-

ns

Setup Time D to Enable

t

SU

-

4.5

12

-

-

15

-

18

-

ns

Hold Time Enable to D

t

H

-

4.5

3

-

-

3

-

3

-

ns

Switching Specifications

Input t

r

, t

f

 = 6ns

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

Propagation Delay,

Data to Q

t

PLH

, t

PHL

C

L

= 50pF

2

-

-

110

-

140

-

165

ns

C

L

= 50pF

4.5

-

-

22

-

28

-

33

ns

C

L

= 15pF

5

-

9

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

19

-

24

-

28

ns

Propagation Delay,

Data to Q

t

PLH

, t

PHL

C

L

= 50pF

2

-

-

130

-

165

-

195

ns

C

L

= 50pF

4.5

-

-

26

-

33

-

39

ns

C

L

= 15pF

5

-

10

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

22

-

28

-

33

ns

Propagation Delay,

Enable to Q

t

PLH

, t

PHL

C

L

= 50pF

2

-

-

130

-

165

-

195

ns

C

L

= 50pF

4.5

-

-

26

-

33

-

39

ns

C

L

= 15pF

5

-

10

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

22

-

28

-

33

ns

Propagation Delay,

Enable to Q

t

PLH

, t

PHL

C

L

= 50pF

2

-

-

130

-

165

-

195

ns

C

L

= 50pF

4.5

-

-

26

-

33

-

39

ns

C

L

= 15pF

5

-

11

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

22

-

28

-

33

ns

Output Transition Time

t

TLH

, t

THL

C

L

= 50pF

2

-

-

75

-

95

-

110

ns

C

L

= 50pF

4.5

-

-

15

-

19

-

22

ns

C

L

= 50pF

6

-

-

13

-

16

-

19

ns

Input Capacitance

C

I

-

-

-

-

10

-

10

-

10

pF

Power Dissipation Capacitance

(Notes 5, 6)

C

PD

-

5

-

46

-

-

-

-

-

pF

HCT TYPES

Propagation Delay,

Data to Q

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

-

28

-

35

-

42

ns

C

L

= 15pF

5

-

11

-

-

-

-

-

ns

Propagation Delay,

Data to Q

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

-

28

-

35

-

42

ns

C

L

= 15pF

5

-

11

-

-

-

-

-

ns

Propagation Delay,

Enable to Q

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

-

28

-

35

-

42

ns

C

L

= 15pF

5

11

-

-

-

-

-

ns

Prerequisite For Switching Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

CD74HC75, CD74HCT75

background image

6

Propagation Delay,

Enable to Q

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

-

30

-

38

-

45

ns

C

L

= 15pF

5

-

12

-

-

-

-

-

ns

Output Transition Time

t

TLH

, t

THL

C

L

= 50pF

4.5

-

-

15

-

19

-

22

ns

Input Capacitance

C

I

-

-

-

-

10

-

10

-

10

pF

Power Dissipation Capacitance

(Notes 5, 6)

C

PD

-

5

-

46

-

-

-

-

-

pF

NOTES:

5. C

PD

 is used to determine the dynamic power consumption, per latch.

6. P

D

 = V

CC

2

 f

i

 (C

PD

 + C

L

) where f

i

 = input frequency, C

L

 = output load capacitance, V

CC

 = supply voltage.

Switching Specifications

Input t

r

, t

f

 = 6ns  (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% V

CC

 to 90% V

CC

 in

accordance with device truth table. For f

MAX

, input duty cycle = 50%.

FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% V

CC

 to 90% V

CC

 in

accordance with device truth table. For f

MAX

, input duty cycle = 50%.

FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 5. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

90%

50%

10%

GND

V

CC

t

r

C

L

t

f

C

L

50%

50%

t

WL

t

WH

10%

t

WL

+ t

WH

=

f

CL

I

CLOCK

2.7V

1.3V

0.3V

GND

3V

t

r

C

L

= 6ns

t

f

C

L

= 6ns

1.3V

1.3V

t

WL

t

WH

0.3V

t

WL

+ t

WH

=

fC

L

I

t

PHL

t

PLH

t

THL

t

TLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

V

CC

t

r

 = 6ns

t

f

 = 6ns

90%

t

PHL

t

PLH

t

THL

t

TLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

t

r

 = 6ns

t

f

 = 6ns

90%

CD74HC75, CD74HCT75

background image

7

FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

Test Circuits and Waveforms

 (Continued)

t

r

C

L

t

f

C

L

GND

V

CC

GND

V

CC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

V

CC

50%

50%

90%

10%

50%

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

t

H(H)

t

r

C

L

t

f

C

L

GND

3V

GND

3V

1.3V

2.7V

0.3V

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

3V

1.3V

1.3V

1.3V

90%

10%

1.3V

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

1.3V

t

H(H)

1.3V

CD74HC75, CD74HCT75

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