background image

SN54AC563, SN74AC563

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

 

SCAS552A – NOVEMBER 1995 – REVISED MAY 1996

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

3-State Inverting Outputs Drive Bus Lines

Directly

D

Full Parallel Access for Loading

D

Flow-Through Architecture to Optimize

PCB Layout

D

EPIC

 (Enhanced-Performance Implanted

CMOS) 1-

µ

m Process

D

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

Ceramic Chip Carriers (FK) and 

Flatpacks (W), and Standard Plastic (N) and

Ceramic (J) DIPs

description

The ’AC563 are octal D-type transparent latches

with 3-state outputs. When the latch-enable (LE)

input is high, the Q outputs follow the

complements of the data (D) inputs. When LE is

taken low, the Q outputs are latched at the inverse

logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the high-imped-

ance state. In the high-impedance state, the

outputs neither load nor drive the bus lines

significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines without need for interface or pullup

components.

OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

The SN54AC563 is characterized for operation over the full military temperature range of – 55

°

C to 125

°

C. The

SN74AC563 is characterized for operation from –40

°

C to 85

°

C.

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

OE

LE

D

Q

L

H

H

L

L

H

L

H

L

L

X

Q0

H

X

X

Z

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1D

2D

3D

4D

5D

6D

7D

8D

GND

V

CC

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

LE

SN54AC563 . . . J  OR  W  PACKAGE

SN74AC563 . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

2Q

3Q

4Q

5Q

6Q

3D

4D

5D

6D

7D

2D

1D

OE

8Q

7Q

1Q

8D

GND

CLK

V

CC

SN54AC563 . . . FK PACKAGE

(TOP VIEW)

 

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Copyright 

©

 1996, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

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SN54AC563, SN74AC563

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

 

SCAS552A – NOVEMBER 1995 – REVISED MAY 1996

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

logic diagram (positive logic)

OE

1D

2

1D

3

2D

4

3D

5

4D

6

5D

C1

11

LE

19

18

17

16

15

14

13

12

7

6D

8

7D

9

8D

EN

1

OE

LE

1D

1Q

1

11

2

19

To Seven Other Channels

C1

1D

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

1

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

 –0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

 –0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 (see Note 1) 

 –0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0 or V

I

 > V

CC

)  

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0 or V

O

 > V

CC

)  

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 (V

O

 = 0 to V

CC

)  

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

 

±

200 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Maximum power dissipation at T

A

 = 55

°

C (in still air) (see Note 2): DB package 

 0.6 W

. . . . . . . . . . . . . . . . . 

DW package 

 1.6 W

. . . . . . . . . . . . . . . . . 

N package 

 1.3 W

. . . . . . . . . . . . . . . . . . . 

PW package 

 0.7 W

. . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

  

–65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150

°

C and a board trace length of 750 mils,

except for the N package, which has a trace length of zero.

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SN54AC563, SN74AC563

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

 

SCAS552A – NOVEMBER 1995 – REVISED MAY 1996

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54AC563

SN74AC563

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

2

6

2

6

V

VCC = 3 V

2.1

2.1

VIH

High-level input voltage

VCC = 4.5 V

3.15

3.15

V

VCC = 5.5 V

3.85

3.85

VCC = 3 V

0.9

0.9

VIL

Low-level input voltage

VCC = 4.5 V

1.35

1.35

V

VCC = 5.5 V

1.65

1.65

VI

Input voltage

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

V

VCC = 3 V

–12

–12

IOH

High-level output current

VCC = 4.5 V

–24

–24

mA

VCC = 5.5 V

–24

–24

VCC = 3 V

12

12

IOL

Low-level output current

VCC = 4.5 V

24

24

mA

VCC = 5.5 V

24

24

t/

v

Input transition rise or fall rate

8

8

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25

°

C

SN54AC563

SN74AC563

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

3 V

2.99

2.9

2.9

IOH = –50 

µ

A

4.5 V

4.49

4.4

4.4

5.5 V

5.49

5.4

5.4

VOH

IOH = –12 mA

3 V

2.56

2.48

2.46

V

IOH = 24 mA

4.5 V

3.86

3.8

3.76

IOH = –24 mA

5.5 V

4.86

4.8

4.76

IOH = –75 mA†

5.5 V

3.85

3.85

3 V

0.002

0.1

0.1

0.1

IOL = 50 

µ

A

4.5 V

0.001

0.1

0.1

0.1

5.5 V

0.001

0.1

0.1

0.1

VOL

IOL = 12 mA

3 V

0.36

0.5

0.44

V

IOL = 24 mA

4.5 V

0.36

0.5

0.44

IOL = 24 mA

5.5 V

0.36

0.5

0.44

IOL = 75 mA†

5.5 V

1.65

1.65

II

VI = VCC or GND

5.5 V

±

0.1

±

1

±

1

µ

A

IOZ

VO = VCC or GND

5.5 V

±

0.5

±

5

±

5

µ

A

ICC

VI = VCC or GND,

IO = 0

5.5 V

8

80

µ

A

Ci

VI = VCC or GND

5 V

4.5

pF

† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54AC563, SN74AC563

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

 

SCAS552A – NOVEMBER 1995 – REVISED MAY 1996

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range, V

CC

 = 3.3 V 

±

 0.3 V

(unless otherwise noted) (see Figure 1)

TA = 25

°

C

SN54AC563

SN74AC563

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration, LE high

6

8

7

ns

tsu

Setup time, data before LE

2.5

5

3

ns

th

Hold time, data after LE

2

3

2

ns

timing requirements over recommended operating free-air temperature range, V

CC

 = 5 V 

±

 0.5 V

(unless otherwise noted) (see Figure 1)

TA = 25

°

C

SN54AC563

SN74AC563

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration, LE high

4

6

5

ns

tsu

Setup time, data before LE

2

4.5

2.5

ns

th

Hold time, data after LE

2

3

2

ns

switching characteristics over recommended operating free-air temperature range,

V

CC 

= 3.3 V 

±

 0.3 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

TA = 25

°

C

SN54AC563

SN74AC563

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

tPLH

D

Q

3.5

5.3

13

1.5

16.5

3.5

15

ns

tPHL

D

Q

3.5

5.6

12

1.5

15.5

3.5

14

ns

tPLH

LE

Q

3.5

4.6

13

1.5

16.5

3.5

15

ns

tPHL

LE

Q

3.5

4.8

12

1.5

15.5

3.5

14

ns

tPZH

OE

Q

2.5

5.3

11

1.5

13.5

2.5

12

ns

tPZL

OE

Q

3

5.4

11

1.5

14

3.5

12.5

ns

tPHZ

OE

Q

4

6

12.5

1.5

15

4.5

13.5

ns

tPLZ

OE

Q

2

5.1

9.5

1.5

12

2.5

10.5

ns

switching characteristics over recommended operating free-air temperature range,

V

CC 

= 5 V 

±

 0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

TA = 25

°

C

SN54AC563

SN74AC563

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

tPLH

D

Q

2

5.3

10

1.5

13

2

11.5

ns

tPHL

D

Q

2

5.6

9.5

1.5

12.5

2

11

ns

tPLH

LE

Q

2

4.6

9.5

1.5

12.5

2

11

ns

tPHL

LE

Q

2

4.8

8.5

1.5

11.5

2

9.5

ns

tPZH

OE

Q

2

5.3

9

1.5

11.5

2

10

ns

tPZL

OE

Q

1.5

5.4

8.5

1.5

11

2

9.5

ns

tPHZ

OE

Q

2

6

11

1.5

13.5

2

12

ns

tPLZ

OE

Q

1.5

5.1

8

1.5

10.5

1.5

9

ns

operating characteristics, V

CC

 = 5 V, T

A

 = 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

CL = 50 pF,      f = 1 MHz

25

pF

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54AC563, SN74AC563

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

 

SCAS552A – NOVEMBER 1995 – REVISED MAY 1996

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50% VCC

0 V

0 V

th

tsu

VOLTAGE WAVEFORMS

Data Input

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

0 V

50% VCC

50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% VCC

VOLTAGE WAVEFORMS

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

×

 VCC

500

 Ω

500

 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

[

 VCC

0 V

50% VCC

VOL + 0.3 V

50% VCC

[

 0 V

Open

VOLTAGE WAVEFORMS

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

Open

TEST

S1

VCC

0 V

50% VCC

tw

VOLTAGE WAVEFORMS

Input

50% VCC

50% VCC

50% VCC

VCC

50% VCC

50% VCC

VCC

VCC

50% VCC

50% VCC

50% VCC

VOH – 0.3 V

VCC

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 1 MHz, ZO = 50 

, tr 

 2.5 ns, tf 

 2.5 ns.

D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1998, Texas Instruments Incorporated