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SN54ABT16373A, SN74ABT16373A

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

 

SCBS160C – DECEMBER 1992 – REVISED MAY 1997

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

State-of-the-Art 

EPIC-

ΙΙ

B

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

D

Typical V

OLP

 (Output Ground Bounce)

< 0.8 V at V

CC

 = 5 V, T

A

 = 25

°

C

D

High-Impedance State During Power Up

and Power Down

D

Distributed V

CC

 and GND Pin Configuration

Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB

Layout

D

High-Drive Outputs (–32-mA I

OH

, 64-mA I

OL

)

D

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’ABT16373A are 16-bit transparent D-type

latches with 3-state outputs designed specifically

for driving highly capacitive or relatively

low-impedance loads. They are particularly

suitable for implementing buffer registers, I/O

ports, bidirectional bus drivers, and working

registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,

the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up

at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus

lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

When V

CC

 is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to V

CC

 through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16373A is characterized for operation over the full military temperature range of –55

°

C to 125

°

C.

The SN74ABT16373A is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-

ΙΙ

B are trademarks of Texas Instruments Incorporated.

SN54ABT16373A . . . WD PACKAGE

SN74ABT16373A . . . DGG OR DL PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1OE

1Q1

1Q2

GND

1Q3

1Q4

V

CC

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

V

CC

2Q5

2Q6

GND

2Q7

2Q8

2OE

1LE

1D1

1D2

GND

1D3

1D4

V

CC

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

V

CC

2D5

2D6

GND

2D7

2D8

2LE

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SN54ABT16373A, SN74ABT16373A

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

 

SCBS160C – DECEMBER 1992 – REVISED MAY 1997

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

(each 8-bit section)

INPUTS

OUTPUT

OE

LE

D

Q

L

H

H

H

L

H

L

L

L

L

X

Q0

H

X

X

Z

logic symbol

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1OE

2OE

1EN

1

C3

48

1LE

3D

47

1D1

46

1D2

44

1D3

43

1D4

1Q1

2

1Q2

3

1Q3

5

1Q4

6

41

1D5

40

1D6

38

1D7

37

1D8

1Q5

8

1Q6

9

1Q7

11

1Q8

12

4D

36

2D1

35

2D2

33

2D3

32

2D4

2Q1

13

2Q2

14

2Q3

16

2Q4

17

30

2D5

29

2D6

27

2D7

26

2D8

2Q5

19

2Q6

20

2Q7

22

2Q8

23

2EN

24

C4

25

2LE

1

2

logic diagram (positive logic)

1OE

1LE

1D1

To Seven Other Channels

1Q1

2OE

2LE

2D1

2Q1

To Seven Other Channels

1

48

47

24

25

36

C1

1D

13

2

C1

1D

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SN54ABT16373A, SN74ABT16373A

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

 

SCBS160C – DECEMBER 1992 – REVISED MAY 1997

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high or power-off state, V

O

 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . 

Current into any output in the low state, I

O

: SN54ABT16373A 96 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ABT16373A 128 

mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): DGG package 

89

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DL package 

94

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

recommended operating conditions (see Note 3)

SN54ABT16373A

SN74ABT16373A

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High-level output current

–24

–32

mA

IOL

Low-level output current

48

64

mA

t/

v

Input transition rise or fall rate

Outputs enabled

10

10

ns/V

t/

VCC

Power-up ramp rate

200

200

µ

s/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

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SN54ABT16373A, SN74ABT16373A

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

 

SCBS160C – DECEMBER 1992 – REVISED MAY 1997

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

°

C

SN54ABT16373A

SN74ABT16373A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = –18 mA

–1.2

–1.2

–1.2

V

VCC = 4.5 V,

IOH = –3 mA

2.5

2.5

2.5

VOH

VCC = 5 V,

IOH = –3 mA

3

3

3

V

VOH

VCC = 4 5 V

IOH = –24 mA

2

2

V

VCC = 4.5 V

IOH = –32 mA

2*

2

VOL

VCC = 4 5 V

IOL = 48 mA

0.55

0.55

V

VOL

VCC = 4.5 V

IOL = 64 mA

0.55*

0.55

V

Vhys

100

mV

II

VCC = 0 to 5.5 V,

VI = VCC or GND

±

1

±

1

±

1

µ

A

IOZPU‡

VCC = 0 to 2.1 V,

VO = 0.5 V to 2.7 V, OE = X

±

50

±

50

±

50

µ

A

IOZPD‡

VCC = 2.1 V to 0,

VO = 0.5 V to 2.7 V, OE = X

±

50

±

50

±

50

µ

A

IOZH

VCC = 2.1 V to 5.5 V,

VO = 2.7 V, OE 

 2 V

10

10

10

µ

A

IOZL

VCC = 2.1 V to 5.5 V,

VO = 0.5 V, OE 

 2 V

–10

–10

–10

µ

A

Ioff

VCC = 0, VI or VO 

 4.5 V

±

100

±

100

µ

A

ICEX Outputs high

VCC = 5.5 V,

VO = 5.5 V

50

50

50

µ

A

IO§

VCC = 5.5 V,

VO = 2.5 V

–50

–100

–180

–50

–180

–50

–180

mA

Outputs high

V

5 5 V I

0

2

2

2

ICC

Outputs low

VCC = 5.5 V, IO = 0,

VI = VCC or GND

85

85

85

mA

Outputs disabled

VI = VCC or GND

2

2

2

ICC¶

VCC = 5.5 V, One input at 3.4 V,

Other inputs at VCC or GND

1.5

1.5

1.5

mA

Ci

VI = 2.5 V or 0.5 V

3.5

pF

Co

VO = 2.5 V or 0.5 V

9.5

pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.

† All typical values are at VCC = 5 V.

‡ This parameter is characterized, but not production tested.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 1)

VCC = 5 V,

TA = 25

°

C#

SN54ABT16373A

SN74ABT16373A

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tw

Pulse duration, LE high

3.3

3.3

3.3

ns

tsu

Setup time, data before LE

1.5

2.4

1.5

ns

th

Hold time, data after LE

1

2.2

1

ns

# These values apply only to the SN74ABT16373A.

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SN54ABT16373A, SN74ABT16373A

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

 

SCBS160C – DECEMBER 1992 – REVISED MAY 1997

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 1)

SN54ABT16373A

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

MIN

MAX

UNIT

MIN

TYP

MAX

tPLH

D

Q

1.4

3.7

5.3

1.4

6.5

ns

tPHL

D

Q

2

4

5.4

2

6.5

ns

tPLH

LE

Q

1.7

4.1

5.7

1.7

7

ns

tPHL

LE

Q

2.3

4.3

5.6

2.3

6.3

ns

tPZH

OE

Q

1.1

3.4

5

1.1

6.4

ns

tPZL

OE

Q

1.5

3.5

4.9

1.5

5.8

ns

tPHZ

OE

Q

2.4

5.1

7.1

2.4

8.3

ns

tPLZ

OE

Q

1.6

4.4

6.3

1.6

8

ns

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 1)

SN74ABT16373A

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25

°

C

MIN

MAX

UNIT

MIN

TYP

MAX

tPLH

D

Q

1.4

3.7

5.3

1.4

6.3

ns

tPHL

D

Q

2

4

5.4

2

6.2

ns

tPLH

LE

Q

1.7

4.1

5.7

1.7

6.7

ns

tPHL

LE

Q

2.3

4.3

5.6

2.3

6.1

ns

tPZH

OE

Q

1.1

3.4

5

1.1

6.1

ns

tPZL

OE

Q

1.5

3.5

4.9

1.5

5.6

ns

tPHZ

OE

Q

2.4

5.1

7.1

2.4

8.1

ns

tPLZ

OE

Q

1.6

4.4

5.8

1.6

6.5

ns

background image

SN54ABT16373A, SN74ABT16373A

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

 

SCBS160C – DECEMBER 1992 – REVISED MAY 1997

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

th

tsu

From Output

 Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500

 Ω

500

 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

 0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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Copyright 

©

 1998, Texas Instruments Incorporated