background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0                     

                                   

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

1

FEATURES

  Fast access time :70/100 ns

  CMOS Low power consumption

Operation current : 30/20 (Icc,max.)

Standby: 20uA (TYP.) L-version

                      2uA (TYP.) LL-version

  Single 2.3V~2.7V power supply

 Operation 

temperature:

Industrial : -40℃~85℃

  All inputs and outputs are TTL compatible

Fully static operation

  Three state outputs

  Data retention voltage : 1.5V (min)

  Data byte control : 

LB

(I/O1~I/O8)

UB (I/O9~I/O16)

  Package : 48-pin 6mm × 8mm TFBGA

FUNCTIONAL BLOCK DIAGRAM

 

MEMORY ARRAY 

2048 Rows x 128 Columns x 16 bits 

COLUMN I/O 

COLUMN DECODER 

I/O 

CONTROL 

LOGIC 

CONTROL 

I/O1 

VSS 

VCC 

I/O16 

. . 

A10 

A11 

A5 

A7 

.

 A9 

ROW 

DECODER 

A0 

A1 

A2 

A3 

A4 

A8 

A13 

A14 

A15 

A16 

A17 

 A6 

LB  

UB

WE

OE

1

CE

 

 A12 

CE2 

GENERAL DESCRIPTION

The UT62V25716(I) is a 4,194,304-bit low power

CMOS static random access memory organized

as 262,144 words by 16 bits.

The UT62V25716(I) operates from a single

2.3V~2.7V power supply and all inputs and

outputs are fully TTL compatible.

The UT62V25716(I) is designed for low power

system applications.    It is particularly well suited

for use in high-density low power system

applications.

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A17

Address Inputs

I/O1 - I/O16

Data Inputs/Outputs

1

CE

, CE2

Chip Enable Input

WE

Write Enable Input

OE

Output Enable Input

LB

Lower-Byte Control

UB

High-Byte Control

Vcc

Power Supply

Vss

Ground

NC

No Connection

PIN CONFIGURATION

OE

1

CE

WE

LB

UB

A12

A11

A13

CE2

I/O9

A10

A14

I/O11

I/O10

A15

I/O6

I/O7

I/O8

A9

Vss

I/O12

A8

A16

I/O5

Vcc

Vcc

I/O4

A17

NC

I/O13

Vss

NC

A7

A0

I/O3

I/O2

I/O15

I/O14

I/O1

NC

A6

A1

A3

A5

NC

I/O16

A4

A2

1

2

3

4

5

6

H

G

C

D

E

F

A

B

TFBGA

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0                     

                                   

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

2

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

RATING

UNIT

  Terminal Voltage with Respect to V

SS

V

TERM

-0.3 to 4.6

V

 Operating Temperature

 Industrial

T

A

-40℃~85℃

 Storage Temperature

T

STG

-65 to 150

 Power Dissipation

P

D

1.0~1.5

W

  DC Output Current

I

OUT

20

mA

  Soldering Temperature (under 10 secs)

Tsolder

260.10

.sec

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device

reliability.

TRUTH TABLE

MODE

1

CE

CE2

OE

WE

LB

UB

I/O1-I/O8

I/O9-I/O16

SUPPLY

CURRENT

H

X

X

X

X

X

High – Z

High – Z

I

SB

, I

SB1

X

L

X

X

X

X

High – Z

High – Z

I

SB

, I

SB1

Standby

X

X

X

X

H

H

High  –  Z

High  –  Z

I

SB

, I

SB1

Output

Disable

L

L

H

H

H

H

H

H

L

X

X

L

High – Z

High – Z

High – Z

High – Z

I

CC

,I

CC1

,I

CC2

Read

L

L

L

H

H

H

L

L

L

H

H

H

L

H

L

H

L

L

D

OUT

High – Z

D

OUT

High – Z

D

OUT

D

OUT

I

CC

,I

CC1

,I

CC2

Write

L

L

L

H

H

H

X

X

X

L

L

L

L

H

L

H

L

L

D

IN

High – Z

D

IN

High – Z

D

IN

D

IN

I

CC

,I

CC1

,I

CC2

Note:    H = V

IH

, L=V

IL

, X = Don't care.(Must be low or high state)

DC ELECTRICAL CHARACTERISTICS 

(Vcc = 2.3V~2.7V, TA = -40℃~85℃(I))

PARAMETER

SYMBOL

TEST CONDITION

MIN. TYP.

MAX.

UNIT

 Power Voltage

Vcc

2.3

2.5

2.7

V

  Input High Voltage

V

IH

2.0

-

Vcc+0.3

V

  Input Low Voltage

V

IL

- 0.2

-

0.6

V

 Input Leakage Current

I

LI

V

SS

  ≦V

IN

  ≦Vcc

- 1

-

1

µA

Output Leakage Current

I

LO

V

SS

  ≦V

I/O

  ≦Vcc, Output Disabled

- 1

-

1

µA

  Output High Voltage

V

OH

I

OH

= - 0.5mA

2.0

-

-

V

  Output Low Voltage

V

OL

I

OL

= 0.5mA

-

-

0.4

V

70

-

20

30

mA

I

CC

Cycle time =min,100% duty, I

I/O

=0mA,

CE2=V

IH

,

1

CE

=V

IL, 

V

IN

=V

IH 

or V

IL

,

100

-

15

20

mA

Icc1

Cycle time = 1us,100% duty, I

I/O

=0mA,

1

CE ≦0.2V, CE2≧Vcc-0.2V

other pins at 0.2V or Vcc-0.2V,

-

3

4

mA

 Operating Power

Supply Current

Icc2

Cycle time =500ns,100% duty, I

I/O

=0mA,

1

CE ≦0.2V, CE2≧Vcc-0.2V

other pins at 0.2V or Vcc-0.2V,

-

6

8

mA

  Standby Current (TTL)

I

SB

1

CE

=V

IH,

or CE2=V

IH

,other pins =V

IH

 or V

IL

,

-

0.3

0.5

mA

-L

-

20

80

µA

Standby Current (CMOS)

I

SB1

1

CE

V

CC

-0.2V,or CE2  ≦0.2V,

other pins at 0.2V or Vcc-0.2V,

-LL

-

2

15

µA

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0

                                                 

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                 

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

3

CAPACITANCE (TA=25℃, f=1.0MHz)

 PARAMETER

SYMBOL

MIN.

MAX

UNIT

 Input Capacitance

C

IN

-

6

pF

 Input/Output Capacitance

C

I/O

-

8

pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

      Input Pulse Levels

0V to 2.2V

      Input Rise and Fall Times

5ns

      Input and Output Timing Reference Levels

1.2V

   Output Load

C

L

 = 30pF, I

OH

/I

OL

 = -0.5mA/0.5mA

AC ELECTRICAL CHARACTERISTICS 

(V

CC

 = 2.3V~2.7V , TA = -40℃~85℃(I))

(1) READ CYCLE

 PARAMETER

SYMBOL

UT62V25716(I)-70

UT62V25716(I)-100

UNIT

MIN.

MAX.

MIN.

MAX.

  Read Cycle Time

t

RC

70

-

100

-

ns

  Address Access Time

t

AA

-

70

-

100

ns

  Chip Enable Access Time

t

ACE

-

70

-

100

ns

  Output Enable Access Time

t

OE

-

35

-

50

ns

  Chip Enable to Output in Low Z

t

CLZ*

10

-

10

-

ns

  Output Enable to Output in Low Z

t

OLZ*

5

-

5

-

ns

  Chip Disable to Output in High Z

t

CHZ*

-

25

-

30

ns

  Output Disable to Output in High Z

t

OHZ*

-

25

-

30

ns

  Output Hold from Address Change

t

OH

5

-

5

-

ns

LB

,

UB

 Access Time

t

BA

-

70

-

100

ns

LB

,

UB

 to High-Z Output

t

HZB

-

30

0

40

ns

LB

,

UB

 to Low-Z Output

t

LZB

0

-

0

-

ns

(2) WRITE CYCLE

 PARAMETER

SYMBO

L

UT62V25716(I)-70

UT62V25716(I)-100

UNIT

MIN.

MAX.

MIN.

MAX.

  Write Cycle Time

t

WC

70

-

100

-

ns

  Address Valid to End of Write

t

AW

60

-

80

-

ns

  Chip Enable to End of Write

t

CW

60

-

80

-

ns

  Address Set-up Time

t

AS

0

-

0

-

ns

  Write Pulse Width

t

WP

55

-

70

-

ns

  Write Recovery Time

t

WR

0

-

0

-

ns

  Data to Write Time Overlap

t

DW

30

-

40

-

ns

  Data Hold from End of Write Time

t

DH

0

-

0

-

ns

  Output Active from End of Write

t

OW*

5

-

5

-

ns

  Write to Output in High Z

t

WHZ*

-

30

-

40

ns

LB

,

UB

 Valid to End of Write

t

PWB

60

-

80

-

ns

* These parameters are guaranteed by device characterization, but not production tested.

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0

                                                 

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                 

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

4

TIMING WAVEFORMS

READ CYCLE 1 

(Address Controlled)

 

(1,2,4)

t

RC

Address

DOUT

Data Valid

t

AA

t

OH

t

OH

READ CYCLE 2 

(

1

CE and CE2

 and  OE Controlled)

 (1,3,5,6)

RC

AA

ACE1

ACE2

BLZ

OE

CHZ1

CHZ2

OHZ

CLZ1

CLZ2

BHZ

OH

OLZ

HIGH-Z

Data Valid

HIGH-Z

Address

CE1

CE2

LB , UB

OE

Dout

Notes :

1. 

WE

 is HIGH for read cycle.

2.  Device is continuously selected  CE1=V

IL 

and CE2=V

IH. 

and

 

LB

=V

IL

 and

 

UB =V

IH.

3.  Address must be valid prior to or coincident with  CE1and CE2 and

 

LB

 and

 

UB  transition; otherwise t

AA

 is the limiting

parameter.

4.  OE  is low.

5. t

CLZ1

, t

CLZ2

, t

OLZ

, t

CHZ1

, t

CHZ2

 and    t

OHZ

 are specified with C

L

=5pF.    Transition is measured  ± 500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ1

 is less than t

CLZ1

, t

CHZ2  

is less than t

CLZ2

, t

OHZ

 is less than t

OLZ.

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0

                                                 

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                 

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

5

WRITE CYCLE 1 

(

WE

Controlled)

 

(1,2,3,5)

WC

AW

CW1

AS

WP

PWB

WH

OW

DW

DH

CW2

WR

Address

CE1

CE2

WE

LB , UB

Dout

Din

Data Valid

High-Z

(4)

(4)

WRITE CYCLE 2 

(

1

CE and CE2 

Controlled)

 

(1,2,5)

WC

AW

CW1

AS

WR

CW2

WP

PWB

WHZ

DW

DH

Data Valid

Address

CE1

CE2

WE

LB , UB

Dout

Din

High-Z

Notes :

1.

WE

 or  CE1 must be HIGH during all address transitions.

2.  A write occurs during the overlap of a low  CE1 and a low 

WE

.

3. During a 

WE

 controlled with write cycle with  OE LOW, t

WP

 must be greater than t

WHZ

+t

DW

 to allow the drivers to turn off and

data to be placed on the bus.

4.  During this period, I/O pins are in the output state, and input singals must not be applied.

5. If the  CE1LOW transition occurs simultaneously with or after 

WE

 LOW transition, the outputs remain in a high impedance

state.

6. t

OW

   

and  t

WHZ

 are specified with C

= 5pF.    Transition is measured  ± 500mV from steady state.

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0

                                                 

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                 

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

6

DATA RETENTION CHARACTERISTICS (TA = 

-40℃~85℃

(I))

PARAMETER

SYMBOL  TEST CONDITION

MIN.

TYP.

MAX. UNIT

 

Vcc for Data Retention

   

V

DR

 

1

CE ≧V

CC

-0.2V or CE2≦

0.2V

1.5

-

-

V

  Data Retention Current

   

I

DR

 Vcc=1.5V

 - L

-

1

50

µA

 

1

CE   ≧  V

CC

-0.2V

or CE2≦0.2V

 - LL

-

0.5

15

µA

  Chip Disable to Data

   

t

CDR

  See Data Retention

0

-

-

ms

 

Retention Time

 

 

 Waveforms (below)

 

Recovery Time

 

  t

R

5

-

-

ms

DATA RETENTION WAVEFORM

  t

CDR

      t

R

V

CC

1

CE

V

SS

Date Retention Mode

            V

DR 

  ≧ 1.5V

       

1

CE

  ≧  V

CC 

-0.2V

      4.5

V

IL

            V

IL

V

IH

        V

IH

          CE2

 

 

≤ 0.2V

    CE2

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0

                                                 

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                 

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

7

PACKAGE OUTLINE DIMENSION

48 pin 6.0mmX8.0mm TFBGA Package Outline Dimension

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0

                                                 

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                 

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

8

ORDERING INFORMATION

INDUSTRIAL TEMPERATURE

PART NO.

ACCESS TIME

( ns )

STANDBY CURRENT

µA max )

PACKAGE

UT62V25716BS-70LI

70

20

48 PIN BGA

UT62V25716BS-70LLI

70

2

48 PIN BGA

UT62V25716BS-100LI

100

20

48 PIN BGA

UT62V25716BS-100LLI

100

2

48 PIN BGA

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0

                                                 

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                 

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

9

REVISION HISTORY

REVISION

DESCRIPTION

DATE

Preliminary Rev. 0.5

Original.

Mar, 2001

Rev.1.0

1. Separate Industrial and Commercial SPEC.

2. New waveforms.

3.  Add access time 55ns range.

4.  The symbols CE1# and OE# and WE# are

revised as 

1

CE  and  OE and 

WE

.

Aug 7,2001

background image

         

UTRON

                                       

UT62V25716(I)

Rev. 1.0

                                                 

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.                                                                 

P80066

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882   FAX: 886-3-5777919

10

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