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SN54HC20, SN74HC20

DUAL 4-INPUT POSITIVE-NAND GATES

 

 

SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW), and

Ceramic Flat (W) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) DIPs

description

The ’HC20 devices contain two independent

4-input NAND gates. They perform the Boolean

function Y = A 

 B 

 C 

 D or Y = A + B + C + D in

positive logic.

The SN54HC20 is characterized for operation

over the full military temperature range of –55

°

C

to 125

°

C. The SN74HC20 is characterized for

operation from –40

°

C to 85

°

C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

C

D

Y

H

H

H

H

L

L

X

X

X

H

X

L

X

X

H

X

X

L

X

H

X

X

X

L

H

logic symbol

1

1A

2

1B

1Y

6

4

1C

5

1D

2Y

8

9

2A

10

2B

&

12

2C

13

2D

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

NC

1C

1D

1Y

GND

V

CC

2D

2C

NC

2B

2A

2Y

SN54HC20 . . . J  OR  W  PACKAGE

SN74HC20 . . . D, DB, N, OR PW PACKAGE

(TOP VIEW)

3

2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

2C

NC

NC

NC

2B

NC

NC

1C

NC

1D

1B

1A

NC

2Y

2A

V

2D

1Y

GND

NC

SN54HC20 . . . FK PACKAGE

(TOP VIEW)

CC

NC – No internal connection

 

Copyright 

©

 2000, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

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SN54HC20, SN74HC20

DUAL 4-INPUT POSITIVE-NAND GATES

 

 

SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

1A

1Y

1B

1C

1D

2A

2Y

2B

2C

2D

1

2

4

5

9

10

12

13

6

8

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

absolute maximum ratings over operating free-air temperature range

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0 or V

I

 > V

CC

) (see Note 1) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0 or V

O

 > V

CC

) (see Note 1) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 (V

O

 = 0 to V

CC

±

25 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): D package 

86

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DB package 

96

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

N package 

80

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

PW package 

113

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

SN54HC20

SN74HC20

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

2

5

6

2

5

6

V

VCC = 2 V

1.5

1.5

VIH

High-level input voltage

VCC = 4.5 V

3.15

3.15

V

VCC = 6 V

4.2

4.2

VCC = 2 V

0

0.5

0

0.5

VIL

Low-level input voltage

VCC = 4.5 V

0

1.35

0

1.35

V

VCC = 6 V

0

1.8

0

1.8

VI

Input voltage

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

V

VCC = 2 V

0

1000

0

1000

tt

Input transition (rise and fall) time

VCC = 4.5 V

0

500

0

500

ns

VCC = 6 V

0

400

0

400

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN54HC20, SN74HC20

DUAL 4-INPUT POSITIVE-NAND GATES

 

 

SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25

°

C

SN54HC20

SN74HC20

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

1.9

1.998

1.9

1.9

IOH = –20 

µ

A

4.5 V

4.4

4.499

4.4

4.4

VOH

VI = VIH or VIL

6 V

5.9

5.999

5.9

5.9

V

IOH = –4 mA

4.5 V

3.98

4.3

3.7

3.84

IOH = –5.2 mA

6 V

5.48

5.8

5.2

5.34

2 V

0.002

0.1

0.1

0.1

IOL = 20 

µ

A

4.5 V

0.001

0.1

0.1

0.1

VOL

VI = VIH or VIL

6 V

0.001

0.1

0.1

0.1

V

IOL = 4 mA

4.5 V

0.17

0.26

0.4

0.33

IOL = 5.2 mA

6 V

0.15

0.26

0.4

0.33

II

VI = VCC or 0

6 V

±

0.1

±

100

±

1000

±

1000

nA

ICC

VI = VCC or 0,

IO = 0

6 V

2

40

20

µ

A

Ci

2 V to 6 V

3

10

10

10

pF

switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25

°

C

SN54HC20

SN74HC20

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

45

110

165

140

tpd

A, B, C, or D

Y

4.5 V

14

22

33

28

ns

6 V

11

19

28

24

2 V

27

75

110

95

tt

Y

4.5 V

9

15

22

19

ns

6 V

7

13

19

16

operating characteristics, T

A

 = 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

No load

25

pF

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SN54HC20, SN74HC20

DUAL 4-INPUT POSITIVE-NAND GATES

 

 

SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

50%

50%

10%

10%

90%

90%

VCC

0 V

tr

tf

Input

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

50%

50%

50%

10%

10%

90%

90%

VCC

VOH

VOL

0 V

tr

tf

Input

In-Phase

Output

50%

tPLH

tPHL

50%

50%

10%

10%

90%

90%

VOH

VOL

tr

tf

tPHL

tPLH

Out-of-Phase

Output

Test

Point

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR 

 1 MHz, ZO = 50 

, tr = 6 ns, tf = 6 ns.

C. The outputs are measured one at a time with one input transition per measurement.

D. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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Copyright 

©

 2000, Texas Instruments Incorporated