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1

Data sheet acquired from Harris Semiconductor

SCHS127

Features

• Typical Propagation Delay: 6ns at V

CC

 = 5V,

C

L

 = 15pF, T

A

 = 25

o

C, Fastest Part in QMOS Line

• Wide Operating Temperature Range  . . . -55

o

C to 125

o

C

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HCU Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

 = 20%, N

IH

 = 30% of

V

CC

 at V

CC

 = 5V

• CMOS Input Compatibility, I

l

1

µ

A at V

OL

, V

OH

Description

The Harris CD74HCU04 unbuffered hex inverter utilizes silicon-

gate CMOS technology to achieve operation speeds similar to

LSTTL gates with the low power consumption of standard

CMOS integrated circuits. These devices are especially useful

in crystal oscillator and analog applications. Figures 10 and 11

are supplied as design information for the above applications.

Pinout

CD74HC04,

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

o

C)

PACKAGE

PKG.

NO.

CD74HCU04E

-55 to 125

14 Ld PDIP

E14.3

CD74HCU04M

-55 to 125

14 Ld SOIC

M14.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer or die for this part number is available which meets all elec-

trical specifications. Please contact your local sales office or

Harris customer service for ordering information.

1A

1Y

2A

2Y

3A

3Y

GND

V

CC

6A

6Y

5A

5Y

4A

4Y

1

2

3

4

5

6

7

14

13

12

11

10

9

8

February 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

 ©

 Harris Corporation 1998

File Number

1655.1

CD74HCU04

High Speed CMOS Logic

Hex Inverter

[ /Title

(CD74

HCU04

)

/Sub-

ject

(High

Speed

CMOS

Logic

Hex

Inverter

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2

Functional Diagram

Logic Symbol

Schematic Diagram

1A

1Y

2Y

3A

3Y

GND

1

2

3

4

5

6

14

13

12

11

V

CC

5A

4Y

5Y

6Y

6A

10

8

7

9

4A

2A

nA

nY

(3, 5, 9, 11, 13) 1

V

CC

2 (4, 6, 8, 10, 12)

CD74HCU04

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3

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

CC

Voltages Referenced to Ground . . . . . . . . . . . . . . . . -0.5V to +7V

DC Input Diode Current, I

IK

For V

I

 < -0.5V or V

I

 > V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Diode Current, I

OK

For V

O

 < -0.5V or V

O

 > V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

20mA

DC Drain Current, per Output, I

O

For V

O

 > -0.5V or V

O

 < V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

25mA

DC V

CC

 or Ground Current, I

CC

 . . . . . . . . . . . . . . . . . . . . . . . . .±

50mA

Operating Conditions

Temperature Range T

A

. . . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125

o

C

Supply Voltage Range, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

DC Input or Output Voltage, V

I

, V

O

 . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3)

θ

JA

 (

o

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

180

Maximum Junction Temperature (Hermetic Package or Die) . . . 175

o

C

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150

o

C

Maximum Storage Temperature Range  . . . . . . . . . .-65

o

C to 150

o

C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

o

C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3.

θ

JA

 is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO +85

o

C

-55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

MAX

MIN

MAX

MIN

MAX

High Level Input

Voltage

V

IH

-

-

2

1.7

-

1.7

-

1.7

-

V

4.5

3.6

-

3.6

 -

3.6

-

V

6

4.8

-

4.8

-

4.8

-

V

Low Level Input

Voltage

V

IL

-

-

2

-

0.3

-

0.3

-

0.3

V

4.5

-

0.8

-

0.8

-

0.8

V

6

-

1.1

-

1.1

-

1.1

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH or

V

IL

-0.02

2

1.8

-

1.8

-

1.8

-

V

-0.02

4.5

4

-

4

 -

4

-

V

-0.02

6

5.5

-

5.5

-

5.5

-

V

High Level Output

Voltage

TTL Loads

V

CC

 or

GND

-4

4.5

3.98

-

3.84

-

3.7

-

V

-5.2

6

5.48

-

5.34

-

5.2

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH or

V

IL

0.02

2

-

0.2

-

0.2

-

0.2

V

0.02

4.5

-

0.5

-

0.5

-

0.5

V

0.02

6

-

0.5

-

0.5

-

0.5

V

Low Level Output

Voltage

TTL Loads

4

4.5

-

0.26

-

0.33

-

0.4

V

V

CC

 or

GND

5.2

6

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 or

GND

-

6

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

6

-

2

-

20

-

40

µ

A

CD74HCU04

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4

Switching Specifications

Input t

r

, t

f

 = 6ns

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Propagation Delay,

Input to Output Y (Figure 1)

t

PLH

, t

PHL

C

L

= 50pF

2

-

-

70

-

90

-

105

ns

C

L

 = 50pF

4.5

-

-

14

-

18

-

21

ns

C

L

 = 15pF

5

-

5

-

-

-

-

-

ns

C

L

 = 50pF

6

-

-

12

-

15

-

18

ns

Transition Times (Figure 1)

t

TLH

, t

THL

C

L

= 50pF

2

-

-

75

-

95

18

110

ns

4.5

-

-

15

-

19

-

22

ns

6

-

-

13

-

16

-

19

ns

Input Capacitance

C

I

-

See Figure 3

pF

Power Dissipation Capacitance

(Notes 4, 5)

C

PD

-

5

-

14

-

-

-

-

-

pF

NOTES:

4. C

PD

 is used to determine the dynamic power consumption, per inverter.

5. P

D

 = V

CC

2

 f

i

 (C

PD

 + C

L

) where f

i

 = input frequency, C

L

 = output load capacitance, V

CC

 = supply voltage.

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

t

PHL

t

PLH

t

THL

t

TLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

V

CC

t

r

 = 6ns

t

f

 = 6ns

90%

Typical Performance Curves

FIGURE 2. TYPICAL INVERTER SUPPLY CURRENT AS FUNCTION OF INPUT VOLTAGE

V

I

, INPUT VOLTAGE (V)

I

CC,

V

CC

 T

O

 GND CURRENT (mA)

25.0

22.5

20.0

17.5

15.0

12.5

10.0

7.5

5.0

2.5

0

1

2

3

4

5

6

V

CC

 = 2V

V

CC

 = 4.5V

V

CC

 = 6V

AMBIENT TEMPERATURE

T

A

 = 25

o

 C

CD74HCU04

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5

FIGURE 3. INPUT CAPACITNCE AS A FUNCTION OF INPUT VOLTAGE

Typical Performance Curves

 (Continued)

65

60

55

50

45

40

35

30

25

20

15

10

5

0

1

2

3

4

5

6

V

DD

 = 3V, V

I

 0-3V

INPUT PIN 5 CONDITIONS

V

IN,

INPUT VOLTAGE (V)

AMBIENT TEMPERATURE, T

A

 = 25

o

C

C

I

, INPUT CAP

A

CIT

ANCE (pF)

70

V

DD

 = 2V, V

I

 0-2V

V

DD

 = 4V, V

I

 0-4V

V

DD

 = 5V, V

I

 0-5V

V

DD

 = 6V, V

I

 0-6V

CD74HCU04

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1998, Texas Instruments Incorporated