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SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

 

SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D

Typical V

OLP

 (Output Ground Bounce)

< 0.8 V at V

CC

 = 3.3 V, T

A

 = 25

°

C

D

Typical V

OHV

 (Output V

OH

 Undershoot)

> 2 V at V

CC

 = 3.3 V, T

A

 = 25

°

C

D

Inputs Accept Voltages to 5.5 V

D

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), Thin Very Small-Outline (DGV), and

Thin Shrink Small-Outline (PW) Packages

description

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V V

CC

 operation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time

requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can

perform as a toggle flip-flop by tying J and K high.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

The SN74LVC112A is characterized for operation from –40

°

C to 85

°

C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

J

K

Q

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

L

X

X

X

H†

H†

H

H

L

L

Q0

Q0

H

H

H

L

H

L

H

H

L

H

L

H

H

H

H

H

Toggle

H

H

H

X

X

Q0

Q0

† The output levels in this configuration may not meet the

minimum levels for VOH. Furthermore, this configuration is

unstable; that is, it does not persist when either PRE or CLR

returns to its inactive (high) level.

Copyright 

©

 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1CLK

1K

1J

1PRE

1Q

1Q

2Q

GND

V

CC

1CLR

2CLR

2CLK

2K

2J

2PRE

2Q

D, DB, DGV, OR PW PACKAGE

(TOP VIEW)

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SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

 

SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

1J

3

1

5

1K

2

R

15

9

10

11

13

12

6

7

1J

1CLK

1K

2PRE

1CLR

2J

2CLK

2K

1Q

1Q

2Q

2Q

14

S

4

1PRE

2CLR

C1

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram, each flip-flop (positive logic)

PRE

CLK

K

Q

Q

CLR

J

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SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

 

SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 (see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0) 

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

±

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 3): D package 

113

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DB package 

131

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DGV package 

180

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

PW package 

149

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

Operating

1.65

3.6

V

VCC

Supply voltage

Data retention only

1.5

V

VCC = 1.65 V to 1.95 V

0.65 

×

VCC

VIH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V

VCC = 2.7 V to 3.6 V

2

VCC = 1.65 V to 1.95 V

0.35 

×

VCC

VIL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V

VCC = 2.7 V to 3.6 V

0.8

VI

Input voltage

0

5.5

V

VO

Output voltage

0

VCC

V

VCC = 1.65 V

–4

IOH

High level output current

VCC = 2.3 V

–8

mA

IOH

High-level output current

VCC = 2.7 V

–12

mA

VCC = 3 V

–24

VCC = 1.65 V

4

IOL

Low level output current

VCC = 2.3 V

8

mA

IOL

Low-level output current

VCC = 2.7 V

12

mA

VCC = 3 V

24

t/

v

Input transition rise or fall rate

0

10

ns/V

TA

Operating free-air temperature

–40

85

°

C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

 

SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

IOH = –100 

µ

A

1.65 V to 3.6 V

VCC–0.2

IOH = –4 mA

1.65 V

1.2

VOH

IOH = –8 mA

2.3 V

1.7

V

VOH

IOH = 12 mA

2.7 V

2.2

V

IOH = –12 mA

3 V

2.4

IOH = –24 mA

3 V

2.2

IOL = 100 

µ

A

1.65 V to 3.6 V

0.2

IOL = 4 mA

1.65 V

0.45

VOL

IOL = 8 mA

2.3 V

0.7

V

IOL = 12 mA

2.7 V

0.4

IOL = 24 mA

3 V

0.55

II

VI = 5.5 V or GND

3.6 V

±

5

µ

A

ICC

VI = VCC or GND,

IO = 0

3.6 V

10

µ

A

ICC

One input at VCC – 0.6 V,

Other inputs at VCC or GND

2.7 V to 3.6 V

500

µ

A

Ci

VI = VCC or GND

3.3 V

4.5

pF

† All typical values are at VCC = 3.3 V, TA = 25

°

C.

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figures 1 through 3)

VCC = 1.8 V

±

0.15 V

VCC = 2.5 V

±

0.2 V

VCC = 2.7 V

VCC = 3.3 V

±

0.3 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

150

150

MHz

tw

Pulse duration, CLK high or low

3.3

3.3

ns

t

Setup time

Data before CLK

2.3

3.1

ns

tsu

Setup time

PRE or CLR inactive

1.1

2.4

ns

th

Hold time, data after CLK

0.7

2.5

ns

‡ This information was not available at the time of publication.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 1.8 V

±

0.15 V

VCC = 2.5 V

±

0.2 V

VCC = 2.7 V

VCC = 3.3 V 

±

0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

MIN

MAX

MIN

TYP

MAX

fmax

150

150

MHz

t d

CLR or PRE

Q or Q

5.5

1

3.4

4.8

ns

tpd

CLK

Q or Q

7.1

1

3.5

5.9

ns

‡ This information was not available at the time of publication.

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SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

 

SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

operating characteristics, T

= 25

°

C

PARAMETER

TEST CONDITIONS

VCC = 1.8 V

±

 0.15 V

VCC = 2.5 V

±

 0.2 V

VCC = 3.3 V

±

 0.3 V

UNIT

TYP

TYP

TYP

Cpd

Power dissipation capacitance per flip-flop

f = 10 MHz

24

pF

† This information was not available at the time of publication.

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 1.8 V 

±

 0.15 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

1 k

1 k

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

Open

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

2 ns, tf 

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 1. Load Circuit and Voltage Waveforms

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SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

 

SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.5 V 

±

 0.2 V

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOH

VOL

th

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500

 Ω

500

 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 

×

 VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

0 V

tw

VCC

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

×

 VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

2 ns, tf 

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

VCC/2

tPLH

×

 VCC

VCC

Figure 2. Load Circuit and Voltage Waveforms

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SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

 

SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

 = 2.7 V AND 3.3 V 

±

 0.3 V

VOH

VOL

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

6 V

Open

GND

500

 Ω

500

 Ω

tPLH

tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

1.5 V

1.5 V

2.7 V

0 V

1.5 V

1.5 V

VOH

VOL

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

0 V

1.5 V

2.7 V

0 V

1.5 V

1.5 V

0 V

2.7 V

0 V

1.5 V

1.5 V

tw

Input

2.7 V

2.7 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

10 MHz, ZO = 50 

, tr 

2.5 ns, tf 

2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

Figure 3. Load Circuit and Voltage Waveforms

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1998, Texas Instruments Incorporated